A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation
This paper presents a power-efficient single-loop continuous-time (CT) \Delta\Sigma modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover,...
Ausführliche Beschreibung
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| Autor*in: |
Ho, Chen-Yen [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2015 |
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| Schlagwörter: |
continuous-time delta-sigma modulator (CT DSM) continuous-time self-coupling (CTSC) Analog-to-digital converter (ADC) |
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| Übergeordnetes Werk: |
Enthalten in: IEEE journal of solid state circuits - New York, NY : IEEE, 1966, 50(2015), 12, Seite 2870-2879 |
|---|---|
| Übergeordnetes Werk: |
volume:50 ; year:2015 ; number:12 ; pages:2870-2879 |
| Links: |
|---|
| DOI / URN: |
10.1109/JSSC.2015.2475160 |
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| Katalog-ID: |
OLC1965882056 |
|---|
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| 245 | 1 | 2 | |a A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation |
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| 520 | |a This paper presents a power-efficient single-loop continuous-time (CT) \Delta\Sigma modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm ^{2} . | ||
| 650 | 4 | |a continuous-time delta-sigma modulator (CT DSM) | |
| 650 | 4 | |a Modulation | |
| 650 | 4 | |a continuous-time self-coupling (CTSC) | |
| 650 | 4 | |a Noise | |
| 650 | 4 | |a Clocks | |
| 650 | 4 | |a Analog-to-digital converter (ADC) | |
| 650 | 4 | |a Quantization (signal) | |
| 650 | 4 | |a excess loop delay (ELD) compensation | |
| 650 | 4 | |a Resistors | |
| 650 | 4 | |a Latches | |
| 650 | 4 | |a Delays | |
| 700 | 1 | |a Liu, Cong |4 oth | |
| 700 | 1 | |a Lo, Chi-Lun |4 oth | |
| 700 | 1 | |a Tsai, Hung-Chieh |4 oth | |
| 700 | 1 | |a Wang, Tze-Chien |4 oth | |
| 700 | 1 | |a Lin, Yu-Hsin |4 oth | |
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10.1109/JSSC.2015.2475160 doi PQ20160617 (DE-627)OLC1965882056 (DE-599)GBVOLC1965882056 (PRQ)c1078-8cea876bffd82e123f9d0b4970576d189cf8e91385dd02e35fda231ebfddad540 (KEY)005068422015000005000120287045mwctselfcoupleddeltasigmamodulatorwith22mhzbwand DE-627 ger DE-627 rakwb eng 620 DNB Ho, Chen-Yen verfasserin aut A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a power-efficient single-loop continuous-time (CT) \Delta\Sigma modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm ^{2} . continuous-time delta-sigma modulator (CT DSM) Modulation continuous-time self-coupling (CTSC) Noise Clocks Analog-to-digital converter (ADC) Quantization (signal) excess loop delay (ELD) compensation Resistors Latches Delays Liu, Cong oth Lo, Chi-Lun oth Tsai, Hung-Chieh oth Wang, Tze-Chien oth Lin, Yu-Hsin oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 12, Seite 2870-2879 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:12 pages:2870-2879 http://dx.doi.org/10.1109/JSSC.2015.2475160 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7284711 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 12 2870-2879 |
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10.1109/JSSC.2015.2475160 doi PQ20160617 (DE-627)OLC1965882056 (DE-599)GBVOLC1965882056 (PRQ)c1078-8cea876bffd82e123f9d0b4970576d189cf8e91385dd02e35fda231ebfddad540 (KEY)005068422015000005000120287045mwctselfcoupleddeltasigmamodulatorwith22mhzbwand DE-627 ger DE-627 rakwb eng 620 DNB Ho, Chen-Yen verfasserin aut A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a power-efficient single-loop continuous-time (CT) \Delta\Sigma modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm ^{2} . continuous-time delta-sigma modulator (CT DSM) Modulation continuous-time self-coupling (CTSC) Noise Clocks Analog-to-digital converter (ADC) Quantization (signal) excess loop delay (ELD) compensation Resistors Latches Delays Liu, Cong oth Lo, Chi-Lun oth Tsai, Hung-Chieh oth Wang, Tze-Chien oth Lin, Yu-Hsin oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 12, Seite 2870-2879 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:12 pages:2870-2879 http://dx.doi.org/10.1109/JSSC.2015.2475160 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7284711 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 12 2870-2879 |
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10.1109/JSSC.2015.2475160 doi PQ20160617 (DE-627)OLC1965882056 (DE-599)GBVOLC1965882056 (PRQ)c1078-8cea876bffd82e123f9d0b4970576d189cf8e91385dd02e35fda231ebfddad540 (KEY)005068422015000005000120287045mwctselfcoupleddeltasigmamodulatorwith22mhzbwand DE-627 ger DE-627 rakwb eng 620 DNB Ho, Chen-Yen verfasserin aut A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a power-efficient single-loop continuous-time (CT) \Delta\Sigma modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm ^{2} . continuous-time delta-sigma modulator (CT DSM) Modulation continuous-time self-coupling (CTSC) Noise Clocks Analog-to-digital converter (ADC) Quantization (signal) excess loop delay (ELD) compensation Resistors Latches Delays Liu, Cong oth Lo, Chi-Lun oth Tsai, Hung-Chieh oth Wang, Tze-Chien oth Lin, Yu-Hsin oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 12, Seite 2870-2879 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:12 pages:2870-2879 http://dx.doi.org/10.1109/JSSC.2015.2475160 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7284711 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 12 2870-2879 |
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10.1109/JSSC.2015.2475160 doi PQ20160617 (DE-627)OLC1965882056 (DE-599)GBVOLC1965882056 (PRQ)c1078-8cea876bffd82e123f9d0b4970576d189cf8e91385dd02e35fda231ebfddad540 (KEY)005068422015000005000120287045mwctselfcoupleddeltasigmamodulatorwith22mhzbwand DE-627 ger DE-627 rakwb eng 620 DNB Ho, Chen-Yen verfasserin aut A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a power-efficient single-loop continuous-time (CT) \Delta\Sigma modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm ^{2} . continuous-time delta-sigma modulator (CT DSM) Modulation continuous-time self-coupling (CTSC) Noise Clocks Analog-to-digital converter (ADC) Quantization (signal) excess loop delay (ELD) compensation Resistors Latches Delays Liu, Cong oth Lo, Chi-Lun oth Tsai, Hung-Chieh oth Wang, Tze-Chien oth Lin, Yu-Hsin oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 12, Seite 2870-2879 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:12 pages:2870-2879 http://dx.doi.org/10.1109/JSSC.2015.2475160 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7284711 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 12 2870-2879 |
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10.1109/JSSC.2015.2475160 doi PQ20160617 (DE-627)OLC1965882056 (DE-599)GBVOLC1965882056 (PRQ)c1078-8cea876bffd82e123f9d0b4970576d189cf8e91385dd02e35fda231ebfddad540 (KEY)005068422015000005000120287045mwctselfcoupleddeltasigmamodulatorwith22mhzbwand DE-627 ger DE-627 rakwb eng 620 DNB Ho, Chen-Yen verfasserin aut A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a power-efficient single-loop continuous-time (CT) \Delta\Sigma modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm ^{2} . continuous-time delta-sigma modulator (CT DSM) Modulation continuous-time self-coupling (CTSC) Noise Clocks Analog-to-digital converter (ADC) Quantization (signal) excess loop delay (ELD) compensation Resistors Latches Delays Liu, Cong oth Lo, Chi-Lun oth Tsai, Hung-Chieh oth Wang, Tze-Chien oth Lin, Yu-Hsin oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 50(2015), 12, Seite 2870-2879 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:50 year:2015 number:12 pages:2870-2879 http://dx.doi.org/10.1109/JSSC.2015.2475160 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7284711 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 50 2015 12 2870-2879 |
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Ho, Chen-Yen @@aut@@ Liu, Cong @@oth@@ Lo, Chi-Lun @@oth@@ Tsai, Hung-Chieh @@oth@@ Wang, Tze-Chien @@oth@@ Lin, Yu-Hsin @@oth@@ |
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Ho, Chen-Yen |
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Ho, Chen-Yen ddc 620 misc continuous-time delta-sigma modulator (CT DSM) misc Modulation misc continuous-time self-coupling (CTSC) misc Noise misc Clocks misc Analog-to-digital converter (ADC) misc Quantization (signal) misc excess loop delay (ELD) compensation misc Resistors misc Latches misc Delays A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation |
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620 DNB A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation continuous-time delta-sigma modulator (CT DSM) Modulation continuous-time self-coupling (CTSC) Noise Clocks Analog-to-digital converter (ADC) Quantization (signal) excess loop delay (ELD) compensation Resistors Latches Delays |
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A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation |
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A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation |
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4.5 mw ct self-coupled \delta\sigma modulator with 2.2 mhz bw and 90.4 db sndr using residual eld compensation |
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A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation |
| abstract |
This paper presents a power-efficient single-loop continuous-time (CT) \Delta\Sigma modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm ^{2} . |
| abstractGer |
This paper presents a power-efficient single-loop continuous-time (CT) \Delta\Sigma modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm ^{2} . |
| abstract_unstemmed |
This paper presents a power-efficient single-loop continuous-time (CT) \Delta\Sigma modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm ^{2} . |
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A 4.5 mW CT Self-Coupled \Delta\Sigma Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation |
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Liu, Cong Lo, Chi-Lun Tsai, Hung-Chieh Wang, Tze-Chien Lin, Yu-Hsin |
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