A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA
Recent investigations of Field Programmable Gate Array (FPGA)-based time-to-digital converters (TDCs) have predominantly focused on improving the time resolution of the device. However, the monolithic integration of multi-channel TDCs and the achievement of high measurement throughput remain challen...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Chong Liu [verfasserIn] |
|---|
| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2015 |
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| Schlagwörter: |
multi-channel time-to-digital converter (TDC) field programmable gate arrays monolithic integrated circuits |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on nuclear science - New York, NY : IEEE, 1963, 62(2015), 3, Seite 773-783 |
|---|---|
| Übergeordnetes Werk: |
volume:62 ; year:2015 ; number:3 ; pages:773-783 |
| Links: |
|---|
| DOI / URN: |
10.1109/TNS.2015.2421319 |
|---|
| Katalog-ID: |
OLC1966226047 |
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| 520 | |a Recent investigations of Field Programmable Gate Array (FPGA)-based time-to-digital converters (TDCs) have predominantly focused on improving the time resolution of the device. However, the monolithic integration of multi-channel TDCs and the achievement of high measurement throughput remain challenging issues for certain applications. In this paper, the potential of the resources provided by the Kintex-7 Xilinx FPGA is fully explored, and a new design is proposed for the implementation of a high performance multi-channel TDC system on this FPGA. Using the tapped-delay-line wave union TDC architecture, in which a negative pulse is triggered by the hit signal propagating along the carry chain, two time measurements are performed in a single carry chain within one clock cycle. The differential non-linearity and time resolution can be significantly improved by realigning the bins. The on-line calibration and on-line updating of the calibration table reduce the influence of variations of environmental conditions. The logic resources of the 6-input look-up tables in the FPGA are employed for hit signal edge detection and bubble-proof encoding, thereby allowing the TDC system to operate at the maximum allowable clock rate of the FPGA and to achieve the maximum possible measurement throughput. This resource-efficient design, in combination with a modular implementation, makes the integration of multiple channels in one FPGA practicable. Using our design, a 128-channel TDC with a dead time of 1.47 ns, a dynamic range of 360 ns, and a root-mean-square resolution of less than 10 ps was implemented in a single Kintex-7 device. | ||
| 650 | 4 | |a field programmable gate array | |
| 650 | 4 | |a time resolution | |
| 650 | 4 | |a monolithic integration | |
| 650 | 4 | |a online updating | |
| 650 | 4 | |a time-to-digital converter | |
| 650 | 4 | |a online calibration | |
| 650 | 4 | |a Calibration | |
| 650 | 4 | |a Clocks | |
| 650 | 4 | |a resource efficient design | |
| 650 | 4 | |a Delay lines | |
| 650 | 4 | |a Delays | |
| 650 | 4 | |a multi-channel time-to-digital converter (TDC) | |
| 650 | 4 | |a multichannel TDC system | |
| 650 | 4 | |a measurement throughput | |
| 650 | 4 | |a thermometer-to-binary encoder | |
| 650 | 4 | |a RMS resolution | |
| 650 | 4 | |a bubble proof encoding | |
| 650 | 4 | |a time-digital conversion | |
| 650 | 4 | |a Throughput | |
| 650 | 4 | |a field programmable gate arrays | |
| 650 | 4 | |a monolithic integrated circuits | |
| 650 | 4 | |a Field programmable gate array (FPGA) | |
| 650 | 4 | |a Kintex-7 FPGA | |
| 650 | 4 | |a Bin realignment | |
| 650 | 4 | |a Digital integrated circuits | |
| 650 | 4 | |a Innovations | |
| 700 | 0 | |a Yonggang Wang |4 oth | |
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10.1109/TNS.2015.2421319 doi PQ20160617 (DE-627)OLC1966226047 (DE-599)GBVOLC1966226047 (PRQ)c1535-2dcdb91255b1be31b67e97e1a82f46eb57c12f22de9b34d9a2576ed8f40094510 (KEY)0054996720150000062000300773128channel710msamplessecondandlessthan10psrmsresol DE-627 ger DE-627 rakwb eng 620 DNB Chong Liu verfasserin aut A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Recent investigations of Field Programmable Gate Array (FPGA)-based time-to-digital converters (TDCs) have predominantly focused on improving the time resolution of the device. However, the monolithic integration of multi-channel TDCs and the achievement of high measurement throughput remain challenging issues for certain applications. In this paper, the potential of the resources provided by the Kintex-7 Xilinx FPGA is fully explored, and a new design is proposed for the implementation of a high performance multi-channel TDC system on this FPGA. Using the tapped-delay-line wave union TDC architecture, in which a negative pulse is triggered by the hit signal propagating along the carry chain, two time measurements are performed in a single carry chain within one clock cycle. The differential non-linearity and time resolution can be significantly improved by realigning the bins. The on-line calibration and on-line updating of the calibration table reduce the influence of variations of environmental conditions. The logic resources of the 6-input look-up tables in the FPGA are employed for hit signal edge detection and bubble-proof encoding, thereby allowing the TDC system to operate at the maximum allowable clock rate of the FPGA and to achieve the maximum possible measurement throughput. This resource-efficient design, in combination with a modular implementation, makes the integration of multiple channels in one FPGA practicable. Using our design, a 128-channel TDC with a dead time of 1.47 ns, a dynamic range of 360 ns, and a root-mean-square resolution of less than 10 ps was implemented in a single Kintex-7 device. field programmable gate array time resolution monolithic integration online updating time-to-digital converter online calibration Calibration Clocks resource efficient design Delay lines Delays multi-channel time-to-digital converter (TDC) multichannel TDC system measurement throughput thermometer-to-binary encoder RMS resolution bubble proof encoding time-digital conversion Throughput field programmable gate arrays monolithic integrated circuits Field programmable gate array (FPGA) Kintex-7 FPGA Bin realignment Digital integrated circuits Innovations Yonggang Wang oth Enthalten in IEEE transactions on nuclear science New York, NY : IEEE, 1963 62(2015), 3, Seite 773-783 (DE-627)129547352 (DE-600)218510-6 (DE-576)014998238 0018-9499 nnns volume:62 year:2015 number:3 pages:773-783 http://dx.doi.org/10.1109/TNS.2015.2421319 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7100940 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-PHA GBV_ILN_70 AR 62 2015 3 773-783 |
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10.1109/TNS.2015.2421319 doi PQ20160617 (DE-627)OLC1966226047 (DE-599)GBVOLC1966226047 (PRQ)c1535-2dcdb91255b1be31b67e97e1a82f46eb57c12f22de9b34d9a2576ed8f40094510 (KEY)0054996720150000062000300773128channel710msamplessecondandlessthan10psrmsresol DE-627 ger DE-627 rakwb eng 620 DNB Chong Liu verfasserin aut A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Recent investigations of Field Programmable Gate Array (FPGA)-based time-to-digital converters (TDCs) have predominantly focused on improving the time resolution of the device. However, the monolithic integration of multi-channel TDCs and the achievement of high measurement throughput remain challenging issues for certain applications. In this paper, the potential of the resources provided by the Kintex-7 Xilinx FPGA is fully explored, and a new design is proposed for the implementation of a high performance multi-channel TDC system on this FPGA. Using the tapped-delay-line wave union TDC architecture, in which a negative pulse is triggered by the hit signal propagating along the carry chain, two time measurements are performed in a single carry chain within one clock cycle. The differential non-linearity and time resolution can be significantly improved by realigning the bins. The on-line calibration and on-line updating of the calibration table reduce the influence of variations of environmental conditions. The logic resources of the 6-input look-up tables in the FPGA are employed for hit signal edge detection and bubble-proof encoding, thereby allowing the TDC system to operate at the maximum allowable clock rate of the FPGA and to achieve the maximum possible measurement throughput. This resource-efficient design, in combination with a modular implementation, makes the integration of multiple channels in one FPGA practicable. Using our design, a 128-channel TDC with a dead time of 1.47 ns, a dynamic range of 360 ns, and a root-mean-square resolution of less than 10 ps was implemented in a single Kintex-7 device. field programmable gate array time resolution monolithic integration online updating time-to-digital converter online calibration Calibration Clocks resource efficient design Delay lines Delays multi-channel time-to-digital converter (TDC) multichannel TDC system measurement throughput thermometer-to-binary encoder RMS resolution bubble proof encoding time-digital conversion Throughput field programmable gate arrays monolithic integrated circuits Field programmable gate array (FPGA) Kintex-7 FPGA Bin realignment Digital integrated circuits Innovations Yonggang Wang oth Enthalten in IEEE transactions on nuclear science New York, NY : IEEE, 1963 62(2015), 3, Seite 773-783 (DE-627)129547352 (DE-600)218510-6 (DE-576)014998238 0018-9499 nnns volume:62 year:2015 number:3 pages:773-783 http://dx.doi.org/10.1109/TNS.2015.2421319 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7100940 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-PHA GBV_ILN_70 AR 62 2015 3 773-783 |
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10.1109/TNS.2015.2421319 doi PQ20160617 (DE-627)OLC1966226047 (DE-599)GBVOLC1966226047 (PRQ)c1535-2dcdb91255b1be31b67e97e1a82f46eb57c12f22de9b34d9a2576ed8f40094510 (KEY)0054996720150000062000300773128channel710msamplessecondandlessthan10psrmsresol DE-627 ger DE-627 rakwb eng 620 DNB Chong Liu verfasserin aut A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Recent investigations of Field Programmable Gate Array (FPGA)-based time-to-digital converters (TDCs) have predominantly focused on improving the time resolution of the device. However, the monolithic integration of multi-channel TDCs and the achievement of high measurement throughput remain challenging issues for certain applications. In this paper, the potential of the resources provided by the Kintex-7 Xilinx FPGA is fully explored, and a new design is proposed for the implementation of a high performance multi-channel TDC system on this FPGA. Using the tapped-delay-line wave union TDC architecture, in which a negative pulse is triggered by the hit signal propagating along the carry chain, two time measurements are performed in a single carry chain within one clock cycle. The differential non-linearity and time resolution can be significantly improved by realigning the bins. The on-line calibration and on-line updating of the calibration table reduce the influence of variations of environmental conditions. The logic resources of the 6-input look-up tables in the FPGA are employed for hit signal edge detection and bubble-proof encoding, thereby allowing the TDC system to operate at the maximum allowable clock rate of the FPGA and to achieve the maximum possible measurement throughput. This resource-efficient design, in combination with a modular implementation, makes the integration of multiple channels in one FPGA practicable. Using our design, a 128-channel TDC with a dead time of 1.47 ns, a dynamic range of 360 ns, and a root-mean-square resolution of less than 10 ps was implemented in a single Kintex-7 device. field programmable gate array time resolution monolithic integration online updating time-to-digital converter online calibration Calibration Clocks resource efficient design Delay lines Delays multi-channel time-to-digital converter (TDC) multichannel TDC system measurement throughput thermometer-to-binary encoder RMS resolution bubble proof encoding time-digital conversion Throughput field programmable gate arrays monolithic integrated circuits Field programmable gate array (FPGA) Kintex-7 FPGA Bin realignment Digital integrated circuits Innovations Yonggang Wang oth Enthalten in IEEE transactions on nuclear science New York, NY : IEEE, 1963 62(2015), 3, Seite 773-783 (DE-627)129547352 (DE-600)218510-6 (DE-576)014998238 0018-9499 nnns volume:62 year:2015 number:3 pages:773-783 http://dx.doi.org/10.1109/TNS.2015.2421319 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7100940 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-PHA GBV_ILN_70 AR 62 2015 3 773-783 |
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10.1109/TNS.2015.2421319 doi PQ20160617 (DE-627)OLC1966226047 (DE-599)GBVOLC1966226047 (PRQ)c1535-2dcdb91255b1be31b67e97e1a82f46eb57c12f22de9b34d9a2576ed8f40094510 (KEY)0054996720150000062000300773128channel710msamplessecondandlessthan10psrmsresol DE-627 ger DE-627 rakwb eng 620 DNB Chong Liu verfasserin aut A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Recent investigations of Field Programmable Gate Array (FPGA)-based time-to-digital converters (TDCs) have predominantly focused on improving the time resolution of the device. However, the monolithic integration of multi-channel TDCs and the achievement of high measurement throughput remain challenging issues for certain applications. In this paper, the potential of the resources provided by the Kintex-7 Xilinx FPGA is fully explored, and a new design is proposed for the implementation of a high performance multi-channel TDC system on this FPGA. Using the tapped-delay-line wave union TDC architecture, in which a negative pulse is triggered by the hit signal propagating along the carry chain, two time measurements are performed in a single carry chain within one clock cycle. The differential non-linearity and time resolution can be significantly improved by realigning the bins. The on-line calibration and on-line updating of the calibration table reduce the influence of variations of environmental conditions. The logic resources of the 6-input look-up tables in the FPGA are employed for hit signal edge detection and bubble-proof encoding, thereby allowing the TDC system to operate at the maximum allowable clock rate of the FPGA and to achieve the maximum possible measurement throughput. This resource-efficient design, in combination with a modular implementation, makes the integration of multiple channels in one FPGA practicable. Using our design, a 128-channel TDC with a dead time of 1.47 ns, a dynamic range of 360 ns, and a root-mean-square resolution of less than 10 ps was implemented in a single Kintex-7 device. field programmable gate array time resolution monolithic integration online updating time-to-digital converter online calibration Calibration Clocks resource efficient design Delay lines Delays multi-channel time-to-digital converter (TDC) multichannel TDC system measurement throughput thermometer-to-binary encoder RMS resolution bubble proof encoding time-digital conversion Throughput field programmable gate arrays monolithic integrated circuits Field programmable gate array (FPGA) Kintex-7 FPGA Bin realignment Digital integrated circuits Innovations Yonggang Wang oth Enthalten in IEEE transactions on nuclear science New York, NY : IEEE, 1963 62(2015), 3, Seite 773-783 (DE-627)129547352 (DE-600)218510-6 (DE-576)014998238 0018-9499 nnns volume:62 year:2015 number:3 pages:773-783 http://dx.doi.org/10.1109/TNS.2015.2421319 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7100940 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-PHA GBV_ILN_70 AR 62 2015 3 773-783 |
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10.1109/TNS.2015.2421319 doi PQ20160617 (DE-627)OLC1966226047 (DE-599)GBVOLC1966226047 (PRQ)c1535-2dcdb91255b1be31b67e97e1a82f46eb57c12f22de9b34d9a2576ed8f40094510 (KEY)0054996720150000062000300773128channel710msamplessecondandlessthan10psrmsresol DE-627 ger DE-627 rakwb eng 620 DNB Chong Liu verfasserin aut A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Recent investigations of Field Programmable Gate Array (FPGA)-based time-to-digital converters (TDCs) have predominantly focused on improving the time resolution of the device. However, the monolithic integration of multi-channel TDCs and the achievement of high measurement throughput remain challenging issues for certain applications. In this paper, the potential of the resources provided by the Kintex-7 Xilinx FPGA is fully explored, and a new design is proposed for the implementation of a high performance multi-channel TDC system on this FPGA. Using the tapped-delay-line wave union TDC architecture, in which a negative pulse is triggered by the hit signal propagating along the carry chain, two time measurements are performed in a single carry chain within one clock cycle. The differential non-linearity and time resolution can be significantly improved by realigning the bins. The on-line calibration and on-line updating of the calibration table reduce the influence of variations of environmental conditions. The logic resources of the 6-input look-up tables in the FPGA are employed for hit signal edge detection and bubble-proof encoding, thereby allowing the TDC system to operate at the maximum allowable clock rate of the FPGA and to achieve the maximum possible measurement throughput. This resource-efficient design, in combination with a modular implementation, makes the integration of multiple channels in one FPGA practicable. Using our design, a 128-channel TDC with a dead time of 1.47 ns, a dynamic range of 360 ns, and a root-mean-square resolution of less than 10 ps was implemented in a single Kintex-7 device. field programmable gate array time resolution monolithic integration online updating time-to-digital converter online calibration Calibration Clocks resource efficient design Delay lines Delays multi-channel time-to-digital converter (TDC) multichannel TDC system measurement throughput thermometer-to-binary encoder RMS resolution bubble proof encoding time-digital conversion Throughput field programmable gate arrays monolithic integrated circuits Field programmable gate array (FPGA) Kintex-7 FPGA Bin realignment Digital integrated circuits Innovations Yonggang Wang oth Enthalten in IEEE transactions on nuclear science New York, NY : IEEE, 1963 62(2015), 3, Seite 773-783 (DE-627)129547352 (DE-600)218510-6 (DE-576)014998238 0018-9499 nnns volume:62 year:2015 number:3 pages:773-783 http://dx.doi.org/10.1109/TNS.2015.2421319 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7100940 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-PHA GBV_ILN_70 AR 62 2015 3 773-783 |
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Chong Liu ddc 620 misc field programmable gate array misc time resolution misc monolithic integration misc online updating misc time-to-digital converter misc online calibration misc Calibration misc Clocks misc resource efficient design misc Delay lines misc Delays misc multi-channel time-to-digital converter (TDC) misc multichannel TDC system misc measurement throughput misc thermometer-to-binary encoder misc RMS resolution misc bubble proof encoding misc time-digital conversion misc Throughput misc field programmable gate arrays misc monolithic integrated circuits misc Field programmable gate array (FPGA) misc Kintex-7 FPGA misc Bin realignment misc Digital integrated circuits misc Innovations A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA |
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620 DNB A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA field programmable gate array time resolution monolithic integration online updating time-to-digital converter online calibration Calibration Clocks resource efficient design Delay lines Delays multi-channel time-to-digital converter (TDC) multichannel TDC system measurement throughput thermometer-to-binary encoder RMS resolution bubble proof encoding time-digital conversion Throughput field programmable gate arrays monolithic integrated circuits Field programmable gate array (FPGA) Kintex-7 FPGA Bin realignment Digital integrated circuits Innovations |
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ddc 620 misc field programmable gate array misc time resolution misc monolithic integration misc online updating misc time-to-digital converter misc online calibration misc Calibration misc Clocks misc resource efficient design misc Delay lines misc Delays misc multi-channel time-to-digital converter (TDC) misc multichannel TDC system misc measurement throughput misc thermometer-to-binary encoder misc RMS resolution misc bubble proof encoding misc time-digital conversion misc Throughput misc field programmable gate arrays misc monolithic integrated circuits misc Field programmable gate array (FPGA) misc Kintex-7 FPGA misc Bin realignment misc Digital integrated circuits misc Innovations |
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A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA |
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Recent investigations of Field Programmable Gate Array (FPGA)-based time-to-digital converters (TDCs) have predominantly focused on improving the time resolution of the device. However, the monolithic integration of multi-channel TDCs and the achievement of high measurement throughput remain challenging issues for certain applications. In this paper, the potential of the resources provided by the Kintex-7 Xilinx FPGA is fully explored, and a new design is proposed for the implementation of a high performance multi-channel TDC system on this FPGA. Using the tapped-delay-line wave union TDC architecture, in which a negative pulse is triggered by the hit signal propagating along the carry chain, two time measurements are performed in a single carry chain within one clock cycle. The differential non-linearity and time resolution can be significantly improved by realigning the bins. The on-line calibration and on-line updating of the calibration table reduce the influence of variations of environmental conditions. The logic resources of the 6-input look-up tables in the FPGA are employed for hit signal edge detection and bubble-proof encoding, thereby allowing the TDC system to operate at the maximum allowable clock rate of the FPGA and to achieve the maximum possible measurement throughput. This resource-efficient design, in combination with a modular implementation, makes the integration of multiple channels in one FPGA practicable. Using our design, a 128-channel TDC with a dead time of 1.47 ns, a dynamic range of 360 ns, and a root-mean-square resolution of less than 10 ps was implemented in a single Kintex-7 device. |
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Recent investigations of Field Programmable Gate Array (FPGA)-based time-to-digital converters (TDCs) have predominantly focused on improving the time resolution of the device. However, the monolithic integration of multi-channel TDCs and the achievement of high measurement throughput remain challenging issues for certain applications. In this paper, the potential of the resources provided by the Kintex-7 Xilinx FPGA is fully explored, and a new design is proposed for the implementation of a high performance multi-channel TDC system on this FPGA. Using the tapped-delay-line wave union TDC architecture, in which a negative pulse is triggered by the hit signal propagating along the carry chain, two time measurements are performed in a single carry chain within one clock cycle. The differential non-linearity and time resolution can be significantly improved by realigning the bins. The on-line calibration and on-line updating of the calibration table reduce the influence of variations of environmental conditions. The logic resources of the 6-input look-up tables in the FPGA are employed for hit signal edge detection and bubble-proof encoding, thereby allowing the TDC system to operate at the maximum allowable clock rate of the FPGA and to achieve the maximum possible measurement throughput. This resource-efficient design, in combination with a modular implementation, makes the integration of multiple channels in one FPGA practicable. Using our design, a 128-channel TDC with a dead time of 1.47 ns, a dynamic range of 360 ns, and a root-mean-square resolution of less than 10 ps was implemented in a single Kintex-7 device. |
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Recent investigations of Field Programmable Gate Array (FPGA)-based time-to-digital converters (TDCs) have predominantly focused on improving the time resolution of the device. However, the monolithic integration of multi-channel TDCs and the achievement of high measurement throughput remain challenging issues for certain applications. In this paper, the potential of the resources provided by the Kintex-7 Xilinx FPGA is fully explored, and a new design is proposed for the implementation of a high performance multi-channel TDC system on this FPGA. Using the tapped-delay-line wave union TDC architecture, in which a negative pulse is triggered by the hit signal propagating along the carry chain, two time measurements are performed in a single carry chain within one clock cycle. The differential non-linearity and time resolution can be significantly improved by realigning the bins. The on-line calibration and on-line updating of the calibration table reduce the influence of variations of environmental conditions. The logic resources of the 6-input look-up tables in the FPGA are employed for hit signal edge detection and bubble-proof encoding, thereby allowing the TDC system to operate at the maximum allowable clock rate of the FPGA and to achieve the maximum possible measurement throughput. This resource-efficient design, in combination with a modular implementation, makes the integration of multiple channels in one FPGA practicable. Using our design, a 128-channel TDC with a dead time of 1.47 ns, a dynamic range of 360 ns, and a root-mean-square resolution of less than 10 ps was implemented in a single Kintex-7 device. |
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A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA |
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