High-Resolution Synthesizable Digitally-Controlled Delay Lines
Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary to add an open-loop fine-grained programmable phase delay to distributed clocks and/or data lines. In this work, w...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Giordano, R [verfasserIn] |
|---|
| Format: |
Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
2015 |
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| Schlagwörter: |
Digitally-controlled delay line (DCDL) |
|---|
| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on nuclear science - New York, NY : IEEE, 1963, 62(2015), 6, Seite 3163-3171 |
|---|---|
| Übergeordnetes Werk: |
volume:62 ; year:2015 ; number:6 ; pages:3163-3171 |
| Links: |
|---|
| DOI / URN: |
10.1109/TNS.2015.2497539 |
|---|
| Katalog-ID: |
OLC1966227000 |
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10.1109/TNS.2015.2497539 doi PQ20160617 (DE-627)OLC1966227000 (DE-599)GBVOLC1966227000 (PRQ)i577-276db218c1af86cb25930aa5b961ae7b69ca408b5a0ab28eaa408f6cc20f89040 (KEY)0054996720150000062000603163highresolutionsynthesizabledigitallycontrolleddela DE-627 ger DE-627 rakwb eng 620 DNB Giordano, R verfasserin aut High-Resolution Synthesizable Digitally-Controlled Delay Lines 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary to add an open-loop fine-grained programmable phase delay to distributed clocks and/or data lines. In this work, we present the performance of DCDLs implemented according to an all-digital novel architecture. The architecture is completely technology-independent, it is described by means of a hardware description language and it can be placed and routed with automatic tools. Our solution is aimed at being used as a synthesizable block in FPGAs, as a proof-of-concept we implemented a prototype in a Xilinx Kintex-7 FPGA. We discuss the measured performance of the implemented delay line in terms of delay range, resolution and linearity. The logic utilization of the delay lines is also presented in the view of a scalable implementation. Digitally-controlled delay line (DCDL) delay line Digital systems Field programmable gate arrays Data acquisition FPGA Delay lines Ameli, F oth Bifulco, P oth Bocci, V oth Cadeddu, S oth Izzo, V oth Lai, A oth Mastroianni, S oth Aloisio, A oth Enthalten in IEEE transactions on nuclear science New York, NY : IEEE, 1963 62(2015), 6, Seite 3163-3171 (DE-627)129547352 (DE-600)218510-6 (DE-576)014998238 0018-9499 nnns volume:62 year:2015 number:6 pages:3163-3171 http://dx.doi.org/10.1109/TNS.2015.2497539 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7348815 http://search.proquest.com/docview/1750085937 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-PHA GBV_ILN_70 AR 62 2015 6 3163-3171 |
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10.1109/TNS.2015.2497539 doi PQ20160617 (DE-627)OLC1966227000 (DE-599)GBVOLC1966227000 (PRQ)i577-276db218c1af86cb25930aa5b961ae7b69ca408b5a0ab28eaa408f6cc20f89040 (KEY)0054996720150000062000603163highresolutionsynthesizabledigitallycontrolleddela DE-627 ger DE-627 rakwb eng 620 DNB Giordano, R verfasserin aut High-Resolution Synthesizable Digitally-Controlled Delay Lines 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary to add an open-loop fine-grained programmable phase delay to distributed clocks and/or data lines. In this work, we present the performance of DCDLs implemented according to an all-digital novel architecture. The architecture is completely technology-independent, it is described by means of a hardware description language and it can be placed and routed with automatic tools. Our solution is aimed at being used as a synthesizable block in FPGAs, as a proof-of-concept we implemented a prototype in a Xilinx Kintex-7 FPGA. We discuss the measured performance of the implemented delay line in terms of delay range, resolution and linearity. The logic utilization of the delay lines is also presented in the view of a scalable implementation. Digitally-controlled delay line (DCDL) delay line Digital systems Field programmable gate arrays Data acquisition FPGA Delay lines Ameli, F oth Bifulco, P oth Bocci, V oth Cadeddu, S oth Izzo, V oth Lai, A oth Mastroianni, S oth Aloisio, A oth Enthalten in IEEE transactions on nuclear science New York, NY : IEEE, 1963 62(2015), 6, Seite 3163-3171 (DE-627)129547352 (DE-600)218510-6 (DE-576)014998238 0018-9499 nnns volume:62 year:2015 number:6 pages:3163-3171 http://dx.doi.org/10.1109/TNS.2015.2497539 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7348815 http://search.proquest.com/docview/1750085937 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-PHA GBV_ILN_70 AR 62 2015 6 3163-3171 |
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10.1109/TNS.2015.2497539 doi PQ20160617 (DE-627)OLC1966227000 (DE-599)GBVOLC1966227000 (PRQ)i577-276db218c1af86cb25930aa5b961ae7b69ca408b5a0ab28eaa408f6cc20f89040 (KEY)0054996720150000062000603163highresolutionsynthesizabledigitallycontrolleddela DE-627 ger DE-627 rakwb eng 620 DNB Giordano, R verfasserin aut High-Resolution Synthesizable Digitally-Controlled Delay Lines 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary to add an open-loop fine-grained programmable phase delay to distributed clocks and/or data lines. In this work, we present the performance of DCDLs implemented according to an all-digital novel architecture. The architecture is completely technology-independent, it is described by means of a hardware description language and it can be placed and routed with automatic tools. Our solution is aimed at being used as a synthesizable block in FPGAs, as a proof-of-concept we implemented a prototype in a Xilinx Kintex-7 FPGA. We discuss the measured performance of the implemented delay line in terms of delay range, resolution and linearity. The logic utilization of the delay lines is also presented in the view of a scalable implementation. Digitally-controlled delay line (DCDL) delay line Digital systems Field programmable gate arrays Data acquisition FPGA Delay lines Ameli, F oth Bifulco, P oth Bocci, V oth Cadeddu, S oth Izzo, V oth Lai, A oth Mastroianni, S oth Aloisio, A oth Enthalten in IEEE transactions on nuclear science New York, NY : IEEE, 1963 62(2015), 6, Seite 3163-3171 (DE-627)129547352 (DE-600)218510-6 (DE-576)014998238 0018-9499 nnns volume:62 year:2015 number:6 pages:3163-3171 http://dx.doi.org/10.1109/TNS.2015.2497539 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7348815 http://search.proquest.com/docview/1750085937 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-PHA GBV_ILN_70 AR 62 2015 6 3163-3171 |
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10.1109/TNS.2015.2497539 doi PQ20160617 (DE-627)OLC1966227000 (DE-599)GBVOLC1966227000 (PRQ)i577-276db218c1af86cb25930aa5b961ae7b69ca408b5a0ab28eaa408f6cc20f89040 (KEY)0054996720150000062000603163highresolutionsynthesizabledigitallycontrolleddela DE-627 ger DE-627 rakwb eng 620 DNB Giordano, R verfasserin aut High-Resolution Synthesizable Digitally-Controlled Delay Lines 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary to add an open-loop fine-grained programmable phase delay to distributed clocks and/or data lines. In this work, we present the performance of DCDLs implemented according to an all-digital novel architecture. The architecture is completely technology-independent, it is described by means of a hardware description language and it can be placed and routed with automatic tools. Our solution is aimed at being used as a synthesizable block in FPGAs, as a proof-of-concept we implemented a prototype in a Xilinx Kintex-7 FPGA. We discuss the measured performance of the implemented delay line in terms of delay range, resolution and linearity. The logic utilization of the delay lines is also presented in the view of a scalable implementation. Digitally-controlled delay line (DCDL) delay line Digital systems Field programmable gate arrays Data acquisition FPGA Delay lines Ameli, F oth Bifulco, P oth Bocci, V oth Cadeddu, S oth Izzo, V oth Lai, A oth Mastroianni, S oth Aloisio, A oth Enthalten in IEEE transactions on nuclear science New York, NY : IEEE, 1963 62(2015), 6, Seite 3163-3171 (DE-627)129547352 (DE-600)218510-6 (DE-576)014998238 0018-9499 nnns volume:62 year:2015 number:6 pages:3163-3171 http://dx.doi.org/10.1109/TNS.2015.2497539 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7348815 http://search.proquest.com/docview/1750085937 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-PHA GBV_ILN_70 AR 62 2015 6 3163-3171 |
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10.1109/TNS.2015.2497539 doi PQ20160617 (DE-627)OLC1966227000 (DE-599)GBVOLC1966227000 (PRQ)i577-276db218c1af86cb25930aa5b961ae7b69ca408b5a0ab28eaa408f6cc20f89040 (KEY)0054996720150000062000603163highresolutionsynthesizabledigitallycontrolleddela DE-627 ger DE-627 rakwb eng 620 DNB Giordano, R verfasserin aut High-Resolution Synthesizable Digitally-Controlled Delay Lines 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary to add an open-loop fine-grained programmable phase delay to distributed clocks and/or data lines. In this work, we present the performance of DCDLs implemented according to an all-digital novel architecture. The architecture is completely technology-independent, it is described by means of a hardware description language and it can be placed and routed with automatic tools. Our solution is aimed at being used as a synthesizable block in FPGAs, as a proof-of-concept we implemented a prototype in a Xilinx Kintex-7 FPGA. We discuss the measured performance of the implemented delay line in terms of delay range, resolution and linearity. The logic utilization of the delay lines is also presented in the view of a scalable implementation. Digitally-controlled delay line (DCDL) delay line Digital systems Field programmable gate arrays Data acquisition FPGA Delay lines Ameli, F oth Bifulco, P oth Bocci, V oth Cadeddu, S oth Izzo, V oth Lai, A oth Mastroianni, S oth Aloisio, A oth Enthalten in IEEE transactions on nuclear science New York, NY : IEEE, 1963 62(2015), 6, Seite 3163-3171 (DE-627)129547352 (DE-600)218510-6 (DE-576)014998238 0018-9499 nnns volume:62 year:2015 number:6 pages:3163-3171 http://dx.doi.org/10.1109/TNS.2015.2497539 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7348815 http://search.proquest.com/docview/1750085937 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-PHA GBV_ILN_70 AR 62 2015 6 3163-3171 |
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620 DNB High-Resolution Synthesizable Digitally-Controlled Delay Lines Digitally-controlled delay line (DCDL) delay line Digital systems Field programmable gate arrays Data acquisition FPGA Delay lines |
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ddc 620 misc Digitally-controlled delay line (DCDL) misc delay line misc Digital systems misc Field programmable gate arrays misc Data acquisition misc FPGA misc Delay lines |
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ddc 620 misc Digitally-controlled delay line (DCDL) misc delay line misc Digital systems misc Field programmable gate arrays misc Data acquisition misc FPGA misc Delay lines |
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High-Resolution Synthesizable Digitally-Controlled Delay Lines |
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High-Resolution Synthesizable Digitally-Controlled Delay Lines |
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Giordano, R |
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high-resolution synthesizable digitally-controlled delay lines |
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High-Resolution Synthesizable Digitally-Controlled Delay Lines |
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Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary to add an open-loop fine-grained programmable phase delay to distributed clocks and/or data lines. In this work, we present the performance of DCDLs implemented according to an all-digital novel architecture. The architecture is completely technology-independent, it is described by means of a hardware description language and it can be placed and routed with automatic tools. Our solution is aimed at being used as a synthesizable block in FPGAs, as a proof-of-concept we implemented a prototype in a Xilinx Kintex-7 FPGA. We discuss the measured performance of the implemented delay line in terms of delay range, resolution and linearity. The logic utilization of the delay lines is also presented in the view of a scalable implementation. |
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Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary to add an open-loop fine-grained programmable phase delay to distributed clocks and/or data lines. In this work, we present the performance of DCDLs implemented according to an all-digital novel architecture. The architecture is completely technology-independent, it is described by means of a hardware description language and it can be placed and routed with automatic tools. Our solution is aimed at being used as a synthesizable block in FPGAs, as a proof-of-concept we implemented a prototype in a Xilinx Kintex-7 FPGA. We discuss the measured performance of the implemented delay line in terms of delay range, resolution and linearity. The logic utilization of the delay lines is also presented in the view of a scalable implementation. |
| abstract_unstemmed |
Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary to add an open-loop fine-grained programmable phase delay to distributed clocks and/or data lines. In this work, we present the performance of DCDLs implemented according to an all-digital novel architecture. The architecture is completely technology-independent, it is described by means of a hardware description language and it can be placed and routed with automatic tools. Our solution is aimed at being used as a synthesizable block in FPGAs, as a proof-of-concept we implemented a prototype in a Xilinx Kintex-7 FPGA. We discuss the measured performance of the implemented delay line in terms of delay range, resolution and linearity. The logic utilization of the delay lines is also presented in the view of a scalable implementation. |
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High-Resolution Synthesizable Digitally-Controlled Delay Lines |
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http://dx.doi.org/10.1109/TNS.2015.2497539 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7348815 http://search.proquest.com/docview/1750085937 |
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Ameli, F Bifulco, P Bocci, V Cadeddu, S Izzo, V Lai, A Mastroianni, S Aloisio, A |
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