Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications
A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with...
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| Autor*in: |
Milani, Luca [verfasserIn] |
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| Format: |
Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
2015 |
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| Schlagwörter: |
multiple-time programable memory Band-to-band hot electrons (BBHEs) Fowler-Nordheim (FN) tunneling |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on electron devices - New York, NY : IEEE, 1963, 62(2015), 10, Seite 3237-3243 |
|---|---|
| Übergeordnetes Werk: |
volume:62 ; year:2015 ; number:10 ; pages:3237-3243 |
| Links: |
|---|
| DOI / URN: |
10.1109/TED.2015.2461660 |
|---|
| Katalog-ID: |
OLC1967766746 |
|---|
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| 245 | 1 | 0 | |a Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications |
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| 520 | |a A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with the gate oxide of the input/output transistors. This improves the coupling capacitance, minimizes the area consumption, and guarantees the retention. The memory cell is programmed by band-to-band hot electrons and erased by Fowler-Nordheim tunneling. Thanks to the proposed writing scheme, the memory cell requires only a single triple-well. This further reduces the area consumption, and ensures, at the same time, fast and reliable memory operations. The measurements on programming, erasing, reading, cycling endurance, and data retention are provided using a 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> standard CMOS process. The memory cell area is 5.91 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{2}\vphantom {\sum ^{R^{r}}} </tex-math></inline-formula> in an array, and it can be programmed in <inline-formula> <tex-math notation="LaTeX">t_{P}=1 </tex-math></inline-formula> ms, erased in <inline-formula> <tex-math notation="LaTeX">t_{E}=10 </tex-math></inline-formula> ms, and cycled for >10k times with a voltage window greater than 2 V. | ||
| 650 | 4 | |a multiple-time programable memory | |
| 650 | 4 | |a CMOS process | |
| 650 | 4 | |a Logic gates | |
| 650 | 4 | |a Programming | |
| 650 | 4 | |a Temperature measurement | |
| 650 | 4 | |a Memory management | |
| 650 | 4 | |a Band-to-band hot electrons (BBHEs) | |
| 650 | 4 | |a single-polysilicon EEPROM | |
| 650 | 4 | |a Tunneling | |
| 650 | 4 | |a Fowler-Nordheim (FN) tunneling | |
| 650 | 4 | |a Arrays | |
| 650 | 4 | |a Semiconductors | |
| 650 | 4 | |a Random access memory | |
| 650 | 4 | |a Transistors | |
| 650 | 4 | |a Complementary metal oxide semiconductors | |
| 650 | 4 | |a Temperature measurements | |
| 650 | 4 | |a Gates (Electronics) | |
| 650 | 4 | |a Analysis | |
| 650 | 4 | |a Usage | |
| 700 | 1 | |a Torricelli, Fabrizio |4 oth | |
| 700 | 1 | |a Kovacs-Vajna, Zsolt Miklos |4 oth | |
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| 773 | 1 | 8 | |g volume:62 |g year:2015 |g number:10 |g pages:3237-3243 |
| 856 | 4 | 1 | |u http://dx.doi.org/10.1109/TED.2015.2461660 |3 Volltext |
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10.1109/TED.2015.2461660 doi PQ20160617 (DE-627)OLC1967766746 (DE-599)GBVOLC1967766746 (PRQ)c2338-1d1ff35ce438a22313de9955cfc479a2c7545ff8b207c8ad6ec670065b4bd530 (KEY)0079428720150000062001003237singlepolyeepromcellinstandardcmosprocessformedium DE-627 ger DE-627 rakwb eng 620 DNB Milani, Luca verfasserin aut Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with the gate oxide of the input/output transistors. This improves the coupling capacitance, minimizes the area consumption, and guarantees the retention. The memory cell is programmed by band-to-band hot electrons and erased by Fowler-Nordheim tunneling. Thanks to the proposed writing scheme, the memory cell requires only a single triple-well. This further reduces the area consumption, and ensures, at the same time, fast and reliable memory operations. The measurements on programming, erasing, reading, cycling endurance, and data retention are provided using a 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> standard CMOS process. The memory cell area is 5.91 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{2}\vphantom {\sum ^{R^{r}}} </tex-math></inline-formula> in an array, and it can be programmed in <inline-formula> <tex-math notation="LaTeX">t_{P}=1 </tex-math></inline-formula> ms, erased in <inline-formula> <tex-math notation="LaTeX">t_{E}=10 </tex-math></inline-formula> ms, and cycled for >10k times with a voltage window greater than 2 V. multiple-time programable memory CMOS process Logic gates Programming Temperature measurement Memory management Band-to-band hot electrons (BBHEs) single-polysilicon EEPROM Tunneling Fowler-Nordheim (FN) tunneling Arrays Semiconductors Random access memory Transistors Complementary metal oxide semiconductors Temperature measurements Gates (Electronics) Analysis Usage Torricelli, Fabrizio oth Kovacs-Vajna, Zsolt Miklos oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 62(2015), 10, Seite 3237-3243 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:62 year:2015 number:10 pages:3237-3243 http://dx.doi.org/10.1109/TED.2015.2461660 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7185390 http://search.proquest.com/docview/1729173757 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_170 GBV_ILN_2004 GBV_ILN_4313 GBV_ILN_4314 AR 62 2015 10 3237-3243 |
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10.1109/TED.2015.2461660 doi PQ20160617 (DE-627)OLC1967766746 (DE-599)GBVOLC1967766746 (PRQ)c2338-1d1ff35ce438a22313de9955cfc479a2c7545ff8b207c8ad6ec670065b4bd530 (KEY)0079428720150000062001003237singlepolyeepromcellinstandardcmosprocessformedium DE-627 ger DE-627 rakwb eng 620 DNB Milani, Luca verfasserin aut Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with the gate oxide of the input/output transistors. This improves the coupling capacitance, minimizes the area consumption, and guarantees the retention. The memory cell is programmed by band-to-band hot electrons and erased by Fowler-Nordheim tunneling. Thanks to the proposed writing scheme, the memory cell requires only a single triple-well. This further reduces the area consumption, and ensures, at the same time, fast and reliable memory operations. The measurements on programming, erasing, reading, cycling endurance, and data retention are provided using a 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> standard CMOS process. The memory cell area is 5.91 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{2}\vphantom {\sum ^{R^{r}}} </tex-math></inline-formula> in an array, and it can be programmed in <inline-formula> <tex-math notation="LaTeX">t_{P}=1 </tex-math></inline-formula> ms, erased in <inline-formula> <tex-math notation="LaTeX">t_{E}=10 </tex-math></inline-formula> ms, and cycled for >10k times with a voltage window greater than 2 V. multiple-time programable memory CMOS process Logic gates Programming Temperature measurement Memory management Band-to-band hot electrons (BBHEs) single-polysilicon EEPROM Tunneling Fowler-Nordheim (FN) tunneling Arrays Semiconductors Random access memory Transistors Complementary metal oxide semiconductors Temperature measurements Gates (Electronics) Analysis Usage Torricelli, Fabrizio oth Kovacs-Vajna, Zsolt Miklos oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 62(2015), 10, Seite 3237-3243 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:62 year:2015 number:10 pages:3237-3243 http://dx.doi.org/10.1109/TED.2015.2461660 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7185390 http://search.proquest.com/docview/1729173757 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_170 GBV_ILN_2004 GBV_ILN_4313 GBV_ILN_4314 AR 62 2015 10 3237-3243 |
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10.1109/TED.2015.2461660 doi PQ20160617 (DE-627)OLC1967766746 (DE-599)GBVOLC1967766746 (PRQ)c2338-1d1ff35ce438a22313de9955cfc479a2c7545ff8b207c8ad6ec670065b4bd530 (KEY)0079428720150000062001003237singlepolyeepromcellinstandardcmosprocessformedium DE-627 ger DE-627 rakwb eng 620 DNB Milani, Luca verfasserin aut Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with the gate oxide of the input/output transistors. This improves the coupling capacitance, minimizes the area consumption, and guarantees the retention. The memory cell is programmed by band-to-band hot electrons and erased by Fowler-Nordheim tunneling. Thanks to the proposed writing scheme, the memory cell requires only a single triple-well. This further reduces the area consumption, and ensures, at the same time, fast and reliable memory operations. The measurements on programming, erasing, reading, cycling endurance, and data retention are provided using a 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> standard CMOS process. The memory cell area is 5.91 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{2}\vphantom {\sum ^{R^{r}}} </tex-math></inline-formula> in an array, and it can be programmed in <inline-formula> <tex-math notation="LaTeX">t_{P}=1 </tex-math></inline-formula> ms, erased in <inline-formula> <tex-math notation="LaTeX">t_{E}=10 </tex-math></inline-formula> ms, and cycled for >10k times with a voltage window greater than 2 V. multiple-time programable memory CMOS process Logic gates Programming Temperature measurement Memory management Band-to-band hot electrons (BBHEs) single-polysilicon EEPROM Tunneling Fowler-Nordheim (FN) tunneling Arrays Semiconductors Random access memory Transistors Complementary metal oxide semiconductors Temperature measurements Gates (Electronics) Analysis Usage Torricelli, Fabrizio oth Kovacs-Vajna, Zsolt Miklos oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 62(2015), 10, Seite 3237-3243 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:62 year:2015 number:10 pages:3237-3243 http://dx.doi.org/10.1109/TED.2015.2461660 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7185390 http://search.proquest.com/docview/1729173757 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_170 GBV_ILN_2004 GBV_ILN_4313 GBV_ILN_4314 AR 62 2015 10 3237-3243 |
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10.1109/TED.2015.2461660 doi PQ20160617 (DE-627)OLC1967766746 (DE-599)GBVOLC1967766746 (PRQ)c2338-1d1ff35ce438a22313de9955cfc479a2c7545ff8b207c8ad6ec670065b4bd530 (KEY)0079428720150000062001003237singlepolyeepromcellinstandardcmosprocessformedium DE-627 ger DE-627 rakwb eng 620 DNB Milani, Luca verfasserin aut Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with the gate oxide of the input/output transistors. This improves the coupling capacitance, minimizes the area consumption, and guarantees the retention. The memory cell is programmed by band-to-band hot electrons and erased by Fowler-Nordheim tunneling. Thanks to the proposed writing scheme, the memory cell requires only a single triple-well. This further reduces the area consumption, and ensures, at the same time, fast and reliable memory operations. The measurements on programming, erasing, reading, cycling endurance, and data retention are provided using a 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> standard CMOS process. The memory cell area is 5.91 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{2}\vphantom {\sum ^{R^{r}}} </tex-math></inline-formula> in an array, and it can be programmed in <inline-formula> <tex-math notation="LaTeX">t_{P}=1 </tex-math></inline-formula> ms, erased in <inline-formula> <tex-math notation="LaTeX">t_{E}=10 </tex-math></inline-formula> ms, and cycled for >10k times with a voltage window greater than 2 V. multiple-time programable memory CMOS process Logic gates Programming Temperature measurement Memory management Band-to-band hot electrons (BBHEs) single-polysilicon EEPROM Tunneling Fowler-Nordheim (FN) tunneling Arrays Semiconductors Random access memory Transistors Complementary metal oxide semiconductors Temperature measurements Gates (Electronics) Analysis Usage Torricelli, Fabrizio oth Kovacs-Vajna, Zsolt Miklos oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 62(2015), 10, Seite 3237-3243 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:62 year:2015 number:10 pages:3237-3243 http://dx.doi.org/10.1109/TED.2015.2461660 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7185390 http://search.proquest.com/docview/1729173757 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_170 GBV_ILN_2004 GBV_ILN_4313 GBV_ILN_4314 AR 62 2015 10 3237-3243 |
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10.1109/TED.2015.2461660 doi PQ20160617 (DE-627)OLC1967766746 (DE-599)GBVOLC1967766746 (PRQ)c2338-1d1ff35ce438a22313de9955cfc479a2c7545ff8b207c8ad6ec670065b4bd530 (KEY)0079428720150000062001003237singlepolyeepromcellinstandardcmosprocessformedium DE-627 ger DE-627 rakwb eng 620 DNB Milani, Luca verfasserin aut Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with the gate oxide of the input/output transistors. This improves the coupling capacitance, minimizes the area consumption, and guarantees the retention. The memory cell is programmed by band-to-band hot electrons and erased by Fowler-Nordheim tunneling. Thanks to the proposed writing scheme, the memory cell requires only a single triple-well. This further reduces the area consumption, and ensures, at the same time, fast and reliable memory operations. The measurements on programming, erasing, reading, cycling endurance, and data retention are provided using a 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> standard CMOS process. The memory cell area is 5.91 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{2}\vphantom {\sum ^{R^{r}}} </tex-math></inline-formula> in an array, and it can be programmed in <inline-formula> <tex-math notation="LaTeX">t_{P}=1 </tex-math></inline-formula> ms, erased in <inline-formula> <tex-math notation="LaTeX">t_{E}=10 </tex-math></inline-formula> ms, and cycled for >10k times with a voltage window greater than 2 V. multiple-time programable memory CMOS process Logic gates Programming Temperature measurement Memory management Band-to-band hot electrons (BBHEs) single-polysilicon EEPROM Tunneling Fowler-Nordheim (FN) tunneling Arrays Semiconductors Random access memory Transistors Complementary metal oxide semiconductors Temperature measurements Gates (Electronics) Analysis Usage Torricelli, Fabrizio oth Kovacs-Vajna, Zsolt Miklos oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 62(2015), 10, Seite 3237-3243 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:62 year:2015 number:10 pages:3237-3243 http://dx.doi.org/10.1109/TED.2015.2461660 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7185390 http://search.proquest.com/docview/1729173757 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_170 GBV_ILN_2004 GBV_ILN_4313 GBV_ILN_4314 AR 62 2015 10 3237-3243 |
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Milani, Luca |
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Milani, Luca ddc 620 misc multiple-time programable memory misc CMOS process misc Logic gates misc Programming misc Temperature measurement misc Memory management misc Band-to-band hot electrons (BBHEs) misc single-polysilicon EEPROM misc Tunneling misc Fowler-Nordheim (FN) tunneling misc Arrays misc Semiconductors misc Random access memory misc Transistors misc Complementary metal oxide semiconductors misc Temperature measurements misc Gates (Electronics) misc Analysis misc Usage Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications |
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620 DNB Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications multiple-time programable memory CMOS process Logic gates Programming Temperature measurement Memory management Band-to-band hot electrons (BBHEs) single-polysilicon EEPROM Tunneling Fowler-Nordheim (FN) tunneling Arrays Semiconductors Random access memory Transistors Complementary metal oxide semiconductors Temperature measurements Gates (Electronics) Analysis Usage |
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single-poly-eeprom cell in standard cmos process for medium-density applications |
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Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications |
| abstract |
A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with the gate oxide of the input/output transistors. This improves the coupling capacitance, minimizes the area consumption, and guarantees the retention. The memory cell is programmed by band-to-band hot electrons and erased by Fowler-Nordheim tunneling. Thanks to the proposed writing scheme, the memory cell requires only a single triple-well. This further reduces the area consumption, and ensures, at the same time, fast and reliable memory operations. The measurements on programming, erasing, reading, cycling endurance, and data retention are provided using a 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> standard CMOS process. The memory cell area is 5.91 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{2}\vphantom {\sum ^{R^{r}}} </tex-math></inline-formula> in an array, and it can be programmed in <inline-formula> <tex-math notation="LaTeX">t_{P}=1 </tex-math></inline-formula> ms, erased in <inline-formula> <tex-math notation="LaTeX">t_{E}=10 </tex-math></inline-formula> ms, and cycled for >10k times with a voltage window greater than 2 V. |
| abstractGer |
A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with the gate oxide of the input/output transistors. This improves the coupling capacitance, minimizes the area consumption, and guarantees the retention. The memory cell is programmed by band-to-band hot electrons and erased by Fowler-Nordheim tunneling. Thanks to the proposed writing scheme, the memory cell requires only a single triple-well. This further reduces the area consumption, and ensures, at the same time, fast and reliable memory operations. The measurements on programming, erasing, reading, cycling endurance, and data retention are provided using a 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> standard CMOS process. The memory cell area is 5.91 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{2}\vphantom {\sum ^{R^{r}}} </tex-math></inline-formula> in an array, and it can be programmed in <inline-formula> <tex-math notation="LaTeX">t_{P}=1 </tex-math></inline-formula> ms, erased in <inline-formula> <tex-math notation="LaTeX">t_{E}=10 </tex-math></inline-formula> ms, and cycled for >10k times with a voltage window greater than 2 V. |
| abstract_unstemmed |
A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with the gate oxide of the input/output transistors. This improves the coupling capacitance, minimizes the area consumption, and guarantees the retention. The memory cell is programmed by band-to-band hot electrons and erased by Fowler-Nordheim tunneling. Thanks to the proposed writing scheme, the memory cell requires only a single triple-well. This further reduces the area consumption, and ensures, at the same time, fast and reliable memory operations. The measurements on programming, erasing, reading, cycling endurance, and data retention are provided using a 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> standard CMOS process. The memory cell area is 5.91 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{2}\vphantom {\sum ^{R^{r}}} </tex-math></inline-formula> in an array, and it can be programmed in <inline-formula> <tex-math notation="LaTeX">t_{P}=1 </tex-math></inline-formula> ms, erased in <inline-formula> <tex-math notation="LaTeX">t_{E}=10 </tex-math></inline-formula> ms, and cycled for >10k times with a voltage window greater than 2 V. |
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Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications |
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http://dx.doi.org/10.1109/TED.2015.2461660 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7185390 http://search.proquest.com/docview/1729173757 |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1967766746</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210716042057.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">160206s2015 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/TED.2015.2461660</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20160617</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1967766746</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1967766746</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)c2338-1d1ff35ce438a22313de9955cfc479a2c7545ff8b207c8ad6ec670065b4bd530</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)0079428720150000062001003237singlepolyeepromcellinstandardcmosprocessformedium</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Milani, Luca</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2015</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with the gate oxide of the input/output transistors. This improves the coupling capacitance, minimizes the area consumption, and guarantees the retention. The memory cell is programmed by band-to-band hot electrons and erased by Fowler-Nordheim tunneling. Thanks to the proposed writing scheme, the memory cell requires only a single triple-well. This further reduces the area consumption, and ensures, at the same time, fast and reliable memory operations. The measurements on programming, erasing, reading, cycling endurance, and data retention are provided using a 0.18-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> standard CMOS process. The memory cell area is 5.91 <inline-formula> <tex-math notation="LaTeX">\mu \text{m}^{2}\vphantom {\sum ^{R^{r}}} </tex-math></inline-formula> in an array, and it can be programmed in <inline-formula> <tex-math notation="LaTeX">t_{P}=1 </tex-math></inline-formula> ms, erased in <inline-formula> <tex-math notation="LaTeX">t_{E}=10 </tex-math></inline-formula> ms, and cycled for >10k times with a voltage window greater than 2 V.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">multiple-time programable memory</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">CMOS process</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic gates</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Programming</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Temperature measurement</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Memory management</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Band-to-band hot electrons (BBHEs)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">single-polysilicon EEPROM</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Tunneling</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fowler-Nordheim (FN) tunneling</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Arrays</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Semiconductors</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Random access memory</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Transistors</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Complementary metal oxide semiconductors</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Temperature measurements</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Gates (Electronics)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Analysis</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Usage</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Torricelli, Fabrizio</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kovacs-Vajna, Zsolt Miklos</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE transactions on electron devices</subfield><subfield code="d">New York, NY : IEEE, 1963</subfield><subfield code="g">62(2015), 10, Seite 3237-3243</subfield><subfield code="w">(DE-627)129602922</subfield><subfield code="w">(DE-600)241634-7</subfield><subfield code="w">(DE-576)015096734</subfield><subfield code="x">0018-9383</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:62</subfield><subfield code="g">year:2015</subfield><subfield code="g">number:10</subfield><subfield code="g">pages:3237-3243</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/TED.2015.2461660</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7185390</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://search.proquest.com/docview/1729173757</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-MAT</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_170</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4314</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">62</subfield><subfield code="j">2015</subfield><subfield code="e">10</subfield><subfield code="h">3237-3243</subfield></datafield></record></collection>
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