A fast‐corrected all‐digital DCC with synchronous input clock
This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 M...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Kao, Shao‐Ku [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2015 |
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| Rechteinformationen: |
Nutzungsrecht: Copyright © 2014 John Wiley & Sons, Ltd. |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: International journal of circuit theory and applications - London : Wiley, 1973, 43(2015), 12, Seite 1845-1860 |
|---|---|
| Übergeordnetes Werk: |
volume:43 ; year:2015 ; number:12 ; pages:1845-1860 |
| Links: |
|---|
| DOI / URN: |
10.1002/cta.2042 |
|---|
| Katalog-ID: |
OLC1967821682 |
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| 520 | |a This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between −2.4 and 2.7%. The largest static phase error between the input and output clock is −44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm 2 and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd. This paper proposes a duty cycle corrector circuit complying with an all‐digital approach, an output clock synchronized with an input clock, and a correction within four clock cycles. | ||
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10.1002/cta.2042 doi PQ20160617 (DE-627)OLC1967821682 (DE-599)GBVOLC1967821682 (PRQ)c1282-9b4cac1263eebb51f886d6282d7b7340d8c11ff86c34a62e3c362899f069379e3 (KEY)0080156920150000043001201845fastcorrectedalldigitaldccwithsynchronousinputcloc DE-627 ger DE-627 rakwb eng 620 ZDB Kao, Shao‐Ku verfasserin aut A fast‐corrected all‐digital DCC with synchronous input clock 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between −2.4 and 2.7%. The largest static phase error between the input and output clock is −44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm 2 and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd. This paper proposes a duty cycle corrector circuit complying with an all‐digital approach, an output clock synchronized with an input clock, and a correction within four clock cycles. Nutzungsrecht: Copyright © 2014 John Wiley & Sons, Ltd. synchronization DCC duty cycle fast locked phase error all digital Hsueh, Sheng‐Hung oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 43(2015), 12, Seite 1845-1860 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:43 year:2015 number:12 pages:1845-1860 http://dx.doi.org/10.1002/cta.2042 Volltext http://onlinelibrary.wiley.com/doi/10.1002/cta.2042/abstract http://search.proquest.com/docview/1757171015 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 43 2015 12 1845-1860 |
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10.1002/cta.2042 doi PQ20160617 (DE-627)OLC1967821682 (DE-599)GBVOLC1967821682 (PRQ)c1282-9b4cac1263eebb51f886d6282d7b7340d8c11ff86c34a62e3c362899f069379e3 (KEY)0080156920150000043001201845fastcorrectedalldigitaldccwithsynchronousinputcloc DE-627 ger DE-627 rakwb eng 620 ZDB Kao, Shao‐Ku verfasserin aut A fast‐corrected all‐digital DCC with synchronous input clock 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between −2.4 and 2.7%. The largest static phase error between the input and output clock is −44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm 2 and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd. This paper proposes a duty cycle corrector circuit complying with an all‐digital approach, an output clock synchronized with an input clock, and a correction within four clock cycles. Nutzungsrecht: Copyright © 2014 John Wiley & Sons, Ltd. synchronization DCC duty cycle fast locked phase error all digital Hsueh, Sheng‐Hung oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 43(2015), 12, Seite 1845-1860 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:43 year:2015 number:12 pages:1845-1860 http://dx.doi.org/10.1002/cta.2042 Volltext http://onlinelibrary.wiley.com/doi/10.1002/cta.2042/abstract http://search.proquest.com/docview/1757171015 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 43 2015 12 1845-1860 |
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10.1002/cta.2042 doi PQ20160617 (DE-627)OLC1967821682 (DE-599)GBVOLC1967821682 (PRQ)c1282-9b4cac1263eebb51f886d6282d7b7340d8c11ff86c34a62e3c362899f069379e3 (KEY)0080156920150000043001201845fastcorrectedalldigitaldccwithsynchronousinputcloc DE-627 ger DE-627 rakwb eng 620 ZDB Kao, Shao‐Ku verfasserin aut A fast‐corrected all‐digital DCC with synchronous input clock 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between −2.4 and 2.7%. The largest static phase error between the input and output clock is −44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm 2 and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd. This paper proposes a duty cycle corrector circuit complying with an all‐digital approach, an output clock synchronized with an input clock, and a correction within four clock cycles. Nutzungsrecht: Copyright © 2014 John Wiley & Sons, Ltd. synchronization DCC duty cycle fast locked phase error all digital Hsueh, Sheng‐Hung oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 43(2015), 12, Seite 1845-1860 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:43 year:2015 number:12 pages:1845-1860 http://dx.doi.org/10.1002/cta.2042 Volltext http://onlinelibrary.wiley.com/doi/10.1002/cta.2042/abstract http://search.proquest.com/docview/1757171015 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 43 2015 12 1845-1860 |
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10.1002/cta.2042 doi PQ20160617 (DE-627)OLC1967821682 (DE-599)GBVOLC1967821682 (PRQ)c1282-9b4cac1263eebb51f886d6282d7b7340d8c11ff86c34a62e3c362899f069379e3 (KEY)0080156920150000043001201845fastcorrectedalldigitaldccwithsynchronousinputcloc DE-627 ger DE-627 rakwb eng 620 ZDB Kao, Shao‐Ku verfasserin aut A fast‐corrected all‐digital DCC with synchronous input clock 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between −2.4 and 2.7%. The largest static phase error between the input and output clock is −44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm 2 and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd. This paper proposes a duty cycle corrector circuit complying with an all‐digital approach, an output clock synchronized with an input clock, and a correction within four clock cycles. Nutzungsrecht: Copyright © 2014 John Wiley & Sons, Ltd. synchronization DCC duty cycle fast locked phase error all digital Hsueh, Sheng‐Hung oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 43(2015), 12, Seite 1845-1860 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:43 year:2015 number:12 pages:1845-1860 http://dx.doi.org/10.1002/cta.2042 Volltext http://onlinelibrary.wiley.com/doi/10.1002/cta.2042/abstract http://search.proquest.com/docview/1757171015 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 43 2015 12 1845-1860 |
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10.1002/cta.2042 doi PQ20160617 (DE-627)OLC1967821682 (DE-599)GBVOLC1967821682 (PRQ)c1282-9b4cac1263eebb51f886d6282d7b7340d8c11ff86c34a62e3c362899f069379e3 (KEY)0080156920150000043001201845fastcorrectedalldigitaldccwithsynchronousinputcloc DE-627 ger DE-627 rakwb eng 620 ZDB Kao, Shao‐Ku verfasserin aut A fast‐corrected all‐digital DCC with synchronous input clock 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between −2.4 and 2.7%. The largest static phase error between the input and output clock is −44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm 2 and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd. This paper proposes a duty cycle corrector circuit complying with an all‐digital approach, an output clock synchronized with an input clock, and a correction within four clock cycles. Nutzungsrecht: Copyright © 2014 John Wiley & Sons, Ltd. synchronization DCC duty cycle fast locked phase error all digital Hsueh, Sheng‐Hung oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 43(2015), 12, Seite 1845-1860 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:43 year:2015 number:12 pages:1845-1860 http://dx.doi.org/10.1002/cta.2042 Volltext http://onlinelibrary.wiley.com/doi/10.1002/cta.2042/abstract http://search.proquest.com/docview/1757171015 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 43 2015 12 1845-1860 |
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Kao, Shao‐Ku |
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10.1002/cta.2042 |
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620 |
| title_sort |
fast‐corrected all‐digital dcc with synchronous input clock |
| title_auth |
A fast‐corrected all‐digital DCC with synchronous input clock |
| abstract |
This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between −2.4 and 2.7%. The largest static phase error between the input and output clock is −44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm 2 and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd. This paper proposes a duty cycle corrector circuit complying with an all‐digital approach, an output clock synchronized with an input clock, and a correction within four clock cycles. |
| abstractGer |
This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between −2.4 and 2.7%. The largest static phase error between the input and output clock is −44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm 2 and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd. This paper proposes a duty cycle corrector circuit complying with an all‐digital approach, an output clock synchronized with an input clock, and a correction within four clock cycles. |
| abstract_unstemmed |
This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between −2.4 and 2.7%. The largest static phase error between the input and output clock is −44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm 2 and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd. This paper proposes a duty cycle corrector circuit complying with an all‐digital approach, an output clock synchronized with an input clock, and a correction within four clock cycles. |
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| title_short |
A fast‐corrected all‐digital DCC with synchronous input clock |
| url |
http://dx.doi.org/10.1002/cta.2042 http://onlinelibrary.wiley.com/doi/10.1002/cta.2042/abstract http://search.proquest.com/docview/1757171015 |
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Hsueh, Sheng‐Hung |
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2024-07-04T02:00:18.706Z |
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