Variation-aware clock network design methodology for Ultralow Voltage circuits

Gespeichert in:

Autor*in:	Xin Zhao [verfasserIn] Tolbert, J.R Mukhopadhyay, S Sung Kyu Lim

Format:	Artikel
Sprache:	Englisch

Erschienen:	2015

Schlagwörter:	Integrated circuits Logic design Research Semiconductor chips

Übergeordnetes Werk:	Enthalten in: IEEE transactions on computer-aided design of integrated circuits and systems - New York, NY : Institute of Electrical and Electronics Engineers, 1982, 34(2015), 8, Seite 1222
Übergeordnetes Werk:	volume:34 ; year:2015 ; number:8 ; pages:1222

Katalog-ID:	OLC196904876X

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