ShiDianNao
In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency and performance of such accelerators remain l...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Du, Zidong [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2016 |
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| Übergeordnetes Werk: |
Enthalten in: Computer architecture news - New York, NY : ACM, 1972, 43(2016), 3, Seite 92-104 |
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| Übergeordnetes Werk: |
volume:43 ; year:2016 ; number:3 ; pages:92-104 |
| Links: |
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| DOI / URN: |
10.1145/2872887.2750389 |
|---|
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OLC1973673711 |
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| 520 | |a In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency and performance of such accelerators remain limited by memory accesses. In this paper, we focus on image applications, arguably the most important category among recognition and mining applications. The neural networks which are state-of-the-art for these applications are Convolutional Neural Networks (CNN), and they have an important property: weights are shared among many neurons, considerably reducing the neural network memory footprint. This property allows to entirely map a CNN within an SRAM, eliminating all DRAM accesses for weights. By further hoisting this accelerator next to the image sensor, it is possible to eliminate all remaining DRAM accesses, i.e., for inputs and outputs. In this paper, we propose such a CNN accelerator, placed next to a CMOS or CCD sensor. The absence of DRAM accesses combined with a careful exploitation of the specific data access patterns within CNNs allows us to design an accelerator which is 60× more energy efficient than the previous state-of-the-art neural network accelerator. We present a full design down to the layout at 65 nm, with a modest footprint of 4.86mm 2 and consuming only 320mW, but still about 30× faster than high-end GPUs. | ||
| 700 | 1 | |a Fasthuber, Robert |4 oth | |
| 700 | 1 | |a Chen, Tianshi |4 oth | |
| 700 | 1 | |a Ienne, Paolo |4 oth | |
| 700 | 1 | |a Li, Ling |4 oth | |
| 700 | 1 | |a Luo, Tao |4 oth | |
| 700 | 1 | |a Feng, Xiaobing |4 oth | |
| 700 | 1 | |a Chen, Yunji |4 oth | |
| 700 | 1 | |a Temam, Olivier |4 oth | |
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10.1145/2872887.2750389 doi PQ20160430 (DE-627)OLC1973673711 (DE-599)GBVOLC1973673711 (PRQ)acm_primary_27503890 (KEY)0040085820160000043000300092shidiannao DE-627 ger DE-627 rakwb eng 004 DNB Du, Zidong verfasserin aut ShiDianNao 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency and performance of such accelerators remain limited by memory accesses. In this paper, we focus on image applications, arguably the most important category among recognition and mining applications. The neural networks which are state-of-the-art for these applications are Convolutional Neural Networks (CNN), and they have an important property: weights are shared among many neurons, considerably reducing the neural network memory footprint. This property allows to entirely map a CNN within an SRAM, eliminating all DRAM accesses for weights. By further hoisting this accelerator next to the image sensor, it is possible to eliminate all remaining DRAM accesses, i.e., for inputs and outputs. In this paper, we propose such a CNN accelerator, placed next to a CMOS or CCD sensor. The absence of DRAM accesses combined with a careful exploitation of the specific data access patterns within CNNs allows us to design an accelerator which is 60× more energy efficient than the previous state-of-the-art neural network accelerator. We present a full design down to the layout at 65 nm, with a modest footprint of 4.86mm 2 and consuming only 320mW, but still about 30× faster than high-end GPUs. Fasthuber, Robert oth Chen, Tianshi oth Ienne, Paolo oth Li, Ling oth Luo, Tao oth Feng, Xiaobing oth Chen, Yunji oth Temam, Olivier oth Enthalten in Computer architecture news New York, NY : ACM, 1972 43(2016), 3, Seite 92-104 (DE-627)129397881 (DE-600)186012-4 (DE-576)014781093 0163-5964 nnns volume:43 year:2016 number:3 pages:92-104 http://dx.doi.org/10.1145/2872887.2750389 Volltext http://dl.acm.org/citation.cfm?id=2750389 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_134 GBV_ILN_2021 GBV_ILN_2190 AR 43 2016 3 92-104 |
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10.1145/2872887.2750389 doi PQ20160430 (DE-627)OLC1973673711 (DE-599)GBVOLC1973673711 (PRQ)acm_primary_27503890 (KEY)0040085820160000043000300092shidiannao DE-627 ger DE-627 rakwb eng 004 DNB Du, Zidong verfasserin aut ShiDianNao 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency and performance of such accelerators remain limited by memory accesses. In this paper, we focus on image applications, arguably the most important category among recognition and mining applications. The neural networks which are state-of-the-art for these applications are Convolutional Neural Networks (CNN), and they have an important property: weights are shared among many neurons, considerably reducing the neural network memory footprint. This property allows to entirely map a CNN within an SRAM, eliminating all DRAM accesses for weights. By further hoisting this accelerator next to the image sensor, it is possible to eliminate all remaining DRAM accesses, i.e., for inputs and outputs. In this paper, we propose such a CNN accelerator, placed next to a CMOS or CCD sensor. The absence of DRAM accesses combined with a careful exploitation of the specific data access patterns within CNNs allows us to design an accelerator which is 60× more energy efficient than the previous state-of-the-art neural network accelerator. We present a full design down to the layout at 65 nm, with a modest footprint of 4.86mm 2 and consuming only 320mW, but still about 30× faster than high-end GPUs. Fasthuber, Robert oth Chen, Tianshi oth Ienne, Paolo oth Li, Ling oth Luo, Tao oth Feng, Xiaobing oth Chen, Yunji oth Temam, Olivier oth Enthalten in Computer architecture news New York, NY : ACM, 1972 43(2016), 3, Seite 92-104 (DE-627)129397881 (DE-600)186012-4 (DE-576)014781093 0163-5964 nnns volume:43 year:2016 number:3 pages:92-104 http://dx.doi.org/10.1145/2872887.2750389 Volltext http://dl.acm.org/citation.cfm?id=2750389 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_134 GBV_ILN_2021 GBV_ILN_2190 AR 43 2016 3 92-104 |
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10.1145/2872887.2750389 doi PQ20160430 (DE-627)OLC1973673711 (DE-599)GBVOLC1973673711 (PRQ)acm_primary_27503890 (KEY)0040085820160000043000300092shidiannao DE-627 ger DE-627 rakwb eng 004 DNB Du, Zidong verfasserin aut ShiDianNao 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency and performance of such accelerators remain limited by memory accesses. In this paper, we focus on image applications, arguably the most important category among recognition and mining applications. The neural networks which are state-of-the-art for these applications are Convolutional Neural Networks (CNN), and they have an important property: weights are shared among many neurons, considerably reducing the neural network memory footprint. This property allows to entirely map a CNN within an SRAM, eliminating all DRAM accesses for weights. By further hoisting this accelerator next to the image sensor, it is possible to eliminate all remaining DRAM accesses, i.e., for inputs and outputs. In this paper, we propose such a CNN accelerator, placed next to a CMOS or CCD sensor. The absence of DRAM accesses combined with a careful exploitation of the specific data access patterns within CNNs allows us to design an accelerator which is 60× more energy efficient than the previous state-of-the-art neural network accelerator. We present a full design down to the layout at 65 nm, with a modest footprint of 4.86mm 2 and consuming only 320mW, but still about 30× faster than high-end GPUs. Fasthuber, Robert oth Chen, Tianshi oth Ienne, Paolo oth Li, Ling oth Luo, Tao oth Feng, Xiaobing oth Chen, Yunji oth Temam, Olivier oth Enthalten in Computer architecture news New York, NY : ACM, 1972 43(2016), 3, Seite 92-104 (DE-627)129397881 (DE-600)186012-4 (DE-576)014781093 0163-5964 nnns volume:43 year:2016 number:3 pages:92-104 http://dx.doi.org/10.1145/2872887.2750389 Volltext http://dl.acm.org/citation.cfm?id=2750389 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_134 GBV_ILN_2021 GBV_ILN_2190 AR 43 2016 3 92-104 |
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10.1145/2872887.2750389 doi PQ20160430 (DE-627)OLC1973673711 (DE-599)GBVOLC1973673711 (PRQ)acm_primary_27503890 (KEY)0040085820160000043000300092shidiannao DE-627 ger DE-627 rakwb eng 004 DNB Du, Zidong verfasserin aut ShiDianNao 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency and performance of such accelerators remain limited by memory accesses. In this paper, we focus on image applications, arguably the most important category among recognition and mining applications. The neural networks which are state-of-the-art for these applications are Convolutional Neural Networks (CNN), and they have an important property: weights are shared among many neurons, considerably reducing the neural network memory footprint. This property allows to entirely map a CNN within an SRAM, eliminating all DRAM accesses for weights. By further hoisting this accelerator next to the image sensor, it is possible to eliminate all remaining DRAM accesses, i.e., for inputs and outputs. In this paper, we propose such a CNN accelerator, placed next to a CMOS or CCD sensor. The absence of DRAM accesses combined with a careful exploitation of the specific data access patterns within CNNs allows us to design an accelerator which is 60× more energy efficient than the previous state-of-the-art neural network accelerator. We present a full design down to the layout at 65 nm, with a modest footprint of 4.86mm 2 and consuming only 320mW, but still about 30× faster than high-end GPUs. Fasthuber, Robert oth Chen, Tianshi oth Ienne, Paolo oth Li, Ling oth Luo, Tao oth Feng, Xiaobing oth Chen, Yunji oth Temam, Olivier oth Enthalten in Computer architecture news New York, NY : ACM, 1972 43(2016), 3, Seite 92-104 (DE-627)129397881 (DE-600)186012-4 (DE-576)014781093 0163-5964 nnns volume:43 year:2016 number:3 pages:92-104 http://dx.doi.org/10.1145/2872887.2750389 Volltext http://dl.acm.org/citation.cfm?id=2750389 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_134 GBV_ILN_2021 GBV_ILN_2190 AR 43 2016 3 92-104 |
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10.1145/2872887.2750389 doi PQ20160430 (DE-627)OLC1973673711 (DE-599)GBVOLC1973673711 (PRQ)acm_primary_27503890 (KEY)0040085820160000043000300092shidiannao DE-627 ger DE-627 rakwb eng 004 DNB Du, Zidong verfasserin aut ShiDianNao 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency and performance of such accelerators remain limited by memory accesses. In this paper, we focus on image applications, arguably the most important category among recognition and mining applications. The neural networks which are state-of-the-art for these applications are Convolutional Neural Networks (CNN), and they have an important property: weights are shared among many neurons, considerably reducing the neural network memory footprint. This property allows to entirely map a CNN within an SRAM, eliminating all DRAM accesses for weights. By further hoisting this accelerator next to the image sensor, it is possible to eliminate all remaining DRAM accesses, i.e., for inputs and outputs. In this paper, we propose such a CNN accelerator, placed next to a CMOS or CCD sensor. The absence of DRAM accesses combined with a careful exploitation of the specific data access patterns within CNNs allows us to design an accelerator which is 60× more energy efficient than the previous state-of-the-art neural network accelerator. We present a full design down to the layout at 65 nm, with a modest footprint of 4.86mm 2 and consuming only 320mW, but still about 30× faster than high-end GPUs. Fasthuber, Robert oth Chen, Tianshi oth Ienne, Paolo oth Li, Ling oth Luo, Tao oth Feng, Xiaobing oth Chen, Yunji oth Temam, Olivier oth Enthalten in Computer architecture news New York, NY : ACM, 1972 43(2016), 3, Seite 92-104 (DE-627)129397881 (DE-600)186012-4 (DE-576)014781093 0163-5964 nnns volume:43 year:2016 number:3 pages:92-104 http://dx.doi.org/10.1145/2872887.2750389 Volltext http://dl.acm.org/citation.cfm?id=2750389 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_134 GBV_ILN_2021 GBV_ILN_2190 AR 43 2016 3 92-104 |
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ShiDianNao |
| abstract |
In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency and performance of such accelerators remain limited by memory accesses. In this paper, we focus on image applications, arguably the most important category among recognition and mining applications. The neural networks which are state-of-the-art for these applications are Convolutional Neural Networks (CNN), and they have an important property: weights are shared among many neurons, considerably reducing the neural network memory footprint. This property allows to entirely map a CNN within an SRAM, eliminating all DRAM accesses for weights. By further hoisting this accelerator next to the image sensor, it is possible to eliminate all remaining DRAM accesses, i.e., for inputs and outputs. In this paper, we propose such a CNN accelerator, placed next to a CMOS or CCD sensor. The absence of DRAM accesses combined with a careful exploitation of the specific data access patterns within CNNs allows us to design an accelerator which is 60× more energy efficient than the previous state-of-the-art neural network accelerator. We present a full design down to the layout at 65 nm, with a modest footprint of 4.86mm 2 and consuming only 320mW, but still about 30× faster than high-end GPUs. |
| abstractGer |
In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency and performance of such accelerators remain limited by memory accesses. In this paper, we focus on image applications, arguably the most important category among recognition and mining applications. The neural networks which are state-of-the-art for these applications are Convolutional Neural Networks (CNN), and they have an important property: weights are shared among many neurons, considerably reducing the neural network memory footprint. This property allows to entirely map a CNN within an SRAM, eliminating all DRAM accesses for weights. By further hoisting this accelerator next to the image sensor, it is possible to eliminate all remaining DRAM accesses, i.e., for inputs and outputs. In this paper, we propose such a CNN accelerator, placed next to a CMOS or CCD sensor. The absence of DRAM accesses combined with a careful exploitation of the specific data access patterns within CNNs allows us to design an accelerator which is 60× more energy efficient than the previous state-of-the-art neural network accelerator. We present a full design down to the layout at 65 nm, with a modest footprint of 4.86mm 2 and consuming only 320mW, but still about 30× faster than high-end GPUs. |
| abstract_unstemmed |
In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency and performance of such accelerators remain limited by memory accesses. In this paper, we focus on image applications, arguably the most important category among recognition and mining applications. The neural networks which are state-of-the-art for these applications are Convolutional Neural Networks (CNN), and they have an important property: weights are shared among many neurons, considerably reducing the neural network memory footprint. This property allows to entirely map a CNN within an SRAM, eliminating all DRAM accesses for weights. By further hoisting this accelerator next to the image sensor, it is possible to eliminate all remaining DRAM accesses, i.e., for inputs and outputs. In this paper, we propose such a CNN accelerator, placed next to a CMOS or CCD sensor. The absence of DRAM accesses combined with a careful exploitation of the specific data access patterns within CNNs allows us to design an accelerator which is 60× more energy efficient than the previous state-of-the-art neural network accelerator. We present a full design down to the layout at 65 nm, with a modest footprint of 4.86mm 2 and consuming only 320mW, but still about 30× faster than high-end GPUs. |
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| title_short |
ShiDianNao |
| url |
http://dx.doi.org/10.1145/2872887.2750389 http://dl.acm.org/citation.cfm?id=2750389 |
| remote_bool |
false |
| author2 |
Fasthuber, Robert Chen, Tianshi Ienne, Paolo Li, Ling Luo, Tao Feng, Xiaobing Chen, Yunji Temam, Olivier |
| author2Str |
Fasthuber, Robert Chen, Tianshi Ienne, Paolo Li, Ling Luo, Tao Feng, Xiaobing Chen, Yunji Temam, Olivier |
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| doi_str |
10.1145/2872887.2750389 |
| up_date |
2024-07-04T02:55:17.852Z |
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