A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC
This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Kim, Shinwoong [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2016 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: IEEE journal of solid state circuits - New York, NY : IEEE, 1966, 51(2016), 2, Seite 391-400 |
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| Übergeordnetes Werk: |
volume:51 ; year:2016 ; number:2 ; pages:391-400 |
| Links: |
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| DOI / URN: |
10.1109/JSSC.2015.2494365 |
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| Katalog-ID: |
OLC1973727692 |
|---|
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| 100 | 1 | |a Kim, Shinwoong |e verfasserin |4 aut | |
| 245 | 1 | 2 | |a A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC |
| 264 | 1 | |c 2016 | |
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| 520 | |a This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of <inline-formula><tex-math notation="LaTeX">{0}.{047}\;\text{mm}^{2}</tex-math></inline-formula> and achieves a stable in-band phase noise of lower than <inline-formula><tex-math notation="LaTeX">- {100}\ \text{dBc}{/}\text{Hz}</tex-math></inline-formula> in a wide range of supply voltage from 1 to 1.4 V. | ||
| 650 | 4 | |a All-digital | |
| 650 | 4 | |a Temperature measurement | |
| 650 | 4 | |a Linearity | |
| 650 | 4 | |a standard cell | |
| 650 | 4 | |a Calibration | |
| 650 | 4 | |a time-to-digital converter (TDC) | |
| 650 | 4 | |a Phase locked loops | |
| 650 | 4 | |a fractional-N | |
| 650 | 4 | |a Phase noise | |
| 650 | 4 | |a Delays | |
| 650 | 4 | |a Interpolation | |
| 650 | 4 | |a phase-locked loop | |
| 650 | 4 | |a frequency synthesizer | |
| 650 | 4 | |a synthesis | |
| 700 | 1 | |a Hong, Seunghwan |4 oth | |
| 700 | 1 | |a Chang, Kapseok |4 oth | |
| 700 | 1 | |a Ju, Hyungsik |4 oth | |
| 700 | 1 | |a Shin, Jaewook |4 oth | |
| 700 | 1 | |a Kim, Byungsub |4 oth | |
| 700 | 1 | |a Park, Hong-June |4 oth | |
| 700 | 1 | |a Sim, Jae-Yoon |4 oth | |
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10.1109/JSSC.2015.2494365 doi PQ20160430 (DE-627)OLC1973727692 (DE-599)GBVOLC1973727692 (PRQ)c1607-45eb9d247b8520a78214b1f0c32ea49a60f68e72de2d9d3055a5e99a963cf2c90 (KEY)00506842201600000510002003912ghzsynthesizedfractionalnadpllwithdualreferencedi DE-627 ger DE-627 rakwb eng 620 DNB Kim, Shinwoong verfasserin aut A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of <inline-formula><tex-math notation="LaTeX">{0}.{047}\;\text{mm}^{2}</tex-math></inline-formula> and achieves a stable in-band phase noise of lower than <inline-formula><tex-math notation="LaTeX">- {100}\ \text{dBc}{/}\text{Hz}</tex-math></inline-formula> in a wide range of supply voltage from 1 to 1.4 V. All-digital Temperature measurement Linearity standard cell Calibration time-to-digital converter (TDC) Phase locked loops fractional-N Phase noise Delays Interpolation phase-locked loop frequency synthesizer synthesis Hong, Seunghwan oth Chang, Kapseok oth Ju, Hyungsik oth Shin, Jaewook oth Kim, Byungsub oth Park, Hong-June oth Sim, Jae-Yoon oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 2, Seite 391-400 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:2 pages:391-400 http://dx.doi.org/10.1109/JSSC.2015.2494365 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7323794 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 2 391-400 |
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10.1109/JSSC.2015.2494365 doi PQ20160430 (DE-627)OLC1973727692 (DE-599)GBVOLC1973727692 (PRQ)c1607-45eb9d247b8520a78214b1f0c32ea49a60f68e72de2d9d3055a5e99a963cf2c90 (KEY)00506842201600000510002003912ghzsynthesizedfractionalnadpllwithdualreferencedi DE-627 ger DE-627 rakwb eng 620 DNB Kim, Shinwoong verfasserin aut A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of <inline-formula><tex-math notation="LaTeX">{0}.{047}\;\text{mm}^{2}</tex-math></inline-formula> and achieves a stable in-band phase noise of lower than <inline-formula><tex-math notation="LaTeX">- {100}\ \text{dBc}{/}\text{Hz}</tex-math></inline-formula> in a wide range of supply voltage from 1 to 1.4 V. All-digital Temperature measurement Linearity standard cell Calibration time-to-digital converter (TDC) Phase locked loops fractional-N Phase noise Delays Interpolation phase-locked loop frequency synthesizer synthesis Hong, Seunghwan oth Chang, Kapseok oth Ju, Hyungsik oth Shin, Jaewook oth Kim, Byungsub oth Park, Hong-June oth Sim, Jae-Yoon oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 2, Seite 391-400 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:2 pages:391-400 http://dx.doi.org/10.1109/JSSC.2015.2494365 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7323794 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 2 391-400 |
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10.1109/JSSC.2015.2494365 doi PQ20160430 (DE-627)OLC1973727692 (DE-599)GBVOLC1973727692 (PRQ)c1607-45eb9d247b8520a78214b1f0c32ea49a60f68e72de2d9d3055a5e99a963cf2c90 (KEY)00506842201600000510002003912ghzsynthesizedfractionalnadpllwithdualreferencedi DE-627 ger DE-627 rakwb eng 620 DNB Kim, Shinwoong verfasserin aut A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of <inline-formula><tex-math notation="LaTeX">{0}.{047}\;\text{mm}^{2}</tex-math></inline-formula> and achieves a stable in-band phase noise of lower than <inline-formula><tex-math notation="LaTeX">- {100}\ \text{dBc}{/}\text{Hz}</tex-math></inline-formula> in a wide range of supply voltage from 1 to 1.4 V. All-digital Temperature measurement Linearity standard cell Calibration time-to-digital converter (TDC) Phase locked loops fractional-N Phase noise Delays Interpolation phase-locked loop frequency synthesizer synthesis Hong, Seunghwan oth Chang, Kapseok oth Ju, Hyungsik oth Shin, Jaewook oth Kim, Byungsub oth Park, Hong-June oth Sim, Jae-Yoon oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 2, Seite 391-400 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:2 pages:391-400 http://dx.doi.org/10.1109/JSSC.2015.2494365 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7323794 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 2 391-400 |
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10.1109/JSSC.2015.2494365 doi PQ20160430 (DE-627)OLC1973727692 (DE-599)GBVOLC1973727692 (PRQ)c1607-45eb9d247b8520a78214b1f0c32ea49a60f68e72de2d9d3055a5e99a963cf2c90 (KEY)00506842201600000510002003912ghzsynthesizedfractionalnadpllwithdualreferencedi DE-627 ger DE-627 rakwb eng 620 DNB Kim, Shinwoong verfasserin aut A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of <inline-formula><tex-math notation="LaTeX">{0}.{047}\;\text{mm}^{2}</tex-math></inline-formula> and achieves a stable in-band phase noise of lower than <inline-formula><tex-math notation="LaTeX">- {100}\ \text{dBc}{/}\text{Hz}</tex-math></inline-formula> in a wide range of supply voltage from 1 to 1.4 V. All-digital Temperature measurement Linearity standard cell Calibration time-to-digital converter (TDC) Phase locked loops fractional-N Phase noise Delays Interpolation phase-locked loop frequency synthesizer synthesis Hong, Seunghwan oth Chang, Kapseok oth Ju, Hyungsik oth Shin, Jaewook oth Kim, Byungsub oth Park, Hong-June oth Sim, Jae-Yoon oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 2, Seite 391-400 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:2 pages:391-400 http://dx.doi.org/10.1109/JSSC.2015.2494365 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7323794 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 2 391-400 |
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10.1109/JSSC.2015.2494365 doi PQ20160430 (DE-627)OLC1973727692 (DE-599)GBVOLC1973727692 (PRQ)c1607-45eb9d247b8520a78214b1f0c32ea49a60f68e72de2d9d3055a5e99a963cf2c90 (KEY)00506842201600000510002003912ghzsynthesizedfractionalnadpllwithdualreferencedi DE-627 ger DE-627 rakwb eng 620 DNB Kim, Shinwoong verfasserin aut A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of <inline-formula><tex-math notation="LaTeX">{0}.{047}\;\text{mm}^{2}</tex-math></inline-formula> and achieves a stable in-band phase noise of lower than <inline-formula><tex-math notation="LaTeX">- {100}\ \text{dBc}{/}\text{Hz}</tex-math></inline-formula> in a wide range of supply voltage from 1 to 1.4 V. All-digital Temperature measurement Linearity standard cell Calibration time-to-digital converter (TDC) Phase locked loops fractional-N Phase noise Delays Interpolation phase-locked loop frequency synthesizer synthesis Hong, Seunghwan oth Chang, Kapseok oth Ju, Hyungsik oth Shin, Jaewook oth Kim, Byungsub oth Park, Hong-June oth Sim, Jae-Yoon oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 2, Seite 391-400 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:2 pages:391-400 http://dx.doi.org/10.1109/JSSC.2015.2494365 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7323794 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 2 391-400 |
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Enthalten in IEEE journal of solid state circuits 51(2016), 2, Seite 391-400 volume:51 year:2016 number:2 pages:391-400 |
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All-digital Temperature measurement Linearity standard cell Calibration time-to-digital converter (TDC) Phase locked loops fractional-N Phase noise Delays Interpolation phase-locked loop frequency synthesizer synthesis |
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Kim, Shinwoong @@aut@@ Hong, Seunghwan @@oth@@ Chang, Kapseok @@oth@@ Ju, Hyungsik @@oth@@ Shin, Jaewook @@oth@@ Kim, Byungsub @@oth@@ Park, Hong-June @@oth@@ Sim, Jae-Yoon @@oth@@ |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1973727692</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210716083107.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">160430s2016 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/JSSC.2015.2494365</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20160430</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1973727692</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1973727692</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)c1607-45eb9d247b8520a78214b1f0c32ea49a60f68e72de2d9d3055a5e99a963cf2c90</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)00506842201600000510002003912ghzsynthesizedfractionalnadpllwithdualreferencedi</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kim, Shinwoong</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2016</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. 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Kim, Shinwoong |
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Kim, Shinwoong ddc 620 misc All-digital misc Temperature measurement misc Linearity misc standard cell misc Calibration misc time-to-digital converter (TDC) misc Phase locked loops misc fractional-N misc Phase noise misc Delays misc Interpolation misc phase-locked loop misc frequency synthesizer misc synthesis A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC |
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620 DNB A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC All-digital Temperature measurement Linearity standard cell Calibration time-to-digital converter (TDC) Phase locked loops fractional-N Phase noise Delays Interpolation phase-locked loop frequency synthesizer synthesis |
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2 ghz synthesized fractional-n adpll with dual-referenced interpolating tdc |
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A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC |
| abstract |
This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of <inline-formula><tex-math notation="LaTeX">{0}.{047}\;\text{mm}^{2}</tex-math></inline-formula> and achieves a stable in-band phase noise of lower than <inline-formula><tex-math notation="LaTeX">- {100}\ \text{dBc}{/}\text{Hz}</tex-math></inline-formula> in a wide range of supply voltage from 1 to 1.4 V. |
| abstractGer |
This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of <inline-formula><tex-math notation="LaTeX">{0}.{047}\;\text{mm}^{2}</tex-math></inline-formula> and achieves a stable in-band phase noise of lower than <inline-formula><tex-math notation="LaTeX">- {100}\ \text{dBc}{/}\text{Hz}</tex-math></inline-formula> in a wide range of supply voltage from 1 to 1.4 V. |
| abstract_unstemmed |
This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of <inline-formula><tex-math notation="LaTeX">{0}.{047}\;\text{mm}^{2}</tex-math></inline-formula> and achieves a stable in-band phase noise of lower than <inline-formula><tex-math notation="LaTeX">- {100}\ \text{dBc}{/}\text{Hz}</tex-math></inline-formula> in a wide range of supply voltage from 1 to 1.4 V. |
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A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC |
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Hong, Seunghwan Chang, Kapseok Ju, Hyungsik Shin, Jaewook Kim, Byungsub Park, Hong-June Sim, Jae-Yoon |
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