An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate
Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no grou...
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| Autor*in: |
Weerasekera, Roshan [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2016 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on electron devices - New York, NY : IEEE, 1963, 63(2016), 3, Seite 1182-1188 |
|---|---|
| Übergeordnetes Werk: |
volume:63 ; year:2016 ; number:3 ; pages:1182-1188 |
| Links: |
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| DOI / URN: |
10.1109/TED.2016.2522501 |
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| Katalog-ID: |
OLC1973864266 |
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| 520 | |a Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs. | ||
| 650 | 4 | |a 2.5-D | |
| 650 | 4 | |a Silicon | |
| 650 | 4 | |a through-silicon via (TSV) | |
| 650 | 4 | |a Integrated circuit modeling | |
| 650 | 4 | |a Substrates | |
| 650 | 4 | |a compact modeling | |
| 650 | 4 | |a Crosstalk | |
| 650 | 4 | |a Capacitance | |
| 650 | 4 | |a Analytical models | |
| 650 | 4 | |a Through-silicon vias | |
| 650 | 4 | |a through-silicon interposer (TSI) | |
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| 700 | 1 | |a Dutta, Rahul |4 oth | |
| 700 | 1 | |a Zhang, Songbai |4 oth | |
| 700 | 1 | |a Chang, Ka Fai |4 oth | |
| 700 | 1 | |a Zhou, Jun |4 oth | |
| 700 | 1 | |a Bhattacharya, Surya |4 oth | |
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10.1109/TED.2016.2522501 doi PQ20160430 (DE-627)OLC1973864266 (DE-599)GBVOLC1973864266 (PRQ)i530-3170bd9a3c2e5d8aac70dd132b0908771dbb1897f0db41650c516d7389a96e590 (KEY)0079428720160000063000301182analyticalcapacitancemodelforthroughsiliconviasinf DE-627 ger DE-627 rakwb eng 620 DNB Weerasekera, Roshan verfasserin aut An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs. 2.5-D Silicon through-silicon via (TSV) Integrated circuit modeling Substrates compact modeling Crosstalk Capacitance Analytical models Through-silicon vias through-silicon interposer (TSI) Katti, Guruprasad oth Dutta, Rahul oth Zhang, Songbai oth Chang, Ka Fai oth Zhou, Jun oth Bhattacharya, Surya oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 63(2016), 3, Seite 1182-1188 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:63 year:2016 number:3 pages:1182-1188 http://dx.doi.org/10.1109/TED.2016.2522501 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407376 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 63 2016 3 1182-1188 |
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10.1109/TED.2016.2522501 doi PQ20160430 (DE-627)OLC1973864266 (DE-599)GBVOLC1973864266 (PRQ)i530-3170bd9a3c2e5d8aac70dd132b0908771dbb1897f0db41650c516d7389a96e590 (KEY)0079428720160000063000301182analyticalcapacitancemodelforthroughsiliconviasinf DE-627 ger DE-627 rakwb eng 620 DNB Weerasekera, Roshan verfasserin aut An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs. 2.5-D Silicon through-silicon via (TSV) Integrated circuit modeling Substrates compact modeling Crosstalk Capacitance Analytical models Through-silicon vias through-silicon interposer (TSI) Katti, Guruprasad oth Dutta, Rahul oth Zhang, Songbai oth Chang, Ka Fai oth Zhou, Jun oth Bhattacharya, Surya oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 63(2016), 3, Seite 1182-1188 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:63 year:2016 number:3 pages:1182-1188 http://dx.doi.org/10.1109/TED.2016.2522501 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407376 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 63 2016 3 1182-1188 |
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10.1109/TED.2016.2522501 doi PQ20160430 (DE-627)OLC1973864266 (DE-599)GBVOLC1973864266 (PRQ)i530-3170bd9a3c2e5d8aac70dd132b0908771dbb1897f0db41650c516d7389a96e590 (KEY)0079428720160000063000301182analyticalcapacitancemodelforthroughsiliconviasinf DE-627 ger DE-627 rakwb eng 620 DNB Weerasekera, Roshan verfasserin aut An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs. 2.5-D Silicon through-silicon via (TSV) Integrated circuit modeling Substrates compact modeling Crosstalk Capacitance Analytical models Through-silicon vias through-silicon interposer (TSI) Katti, Guruprasad oth Dutta, Rahul oth Zhang, Songbai oth Chang, Ka Fai oth Zhou, Jun oth Bhattacharya, Surya oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 63(2016), 3, Seite 1182-1188 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:63 year:2016 number:3 pages:1182-1188 http://dx.doi.org/10.1109/TED.2016.2522501 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407376 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 63 2016 3 1182-1188 |
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10.1109/TED.2016.2522501 doi PQ20160430 (DE-627)OLC1973864266 (DE-599)GBVOLC1973864266 (PRQ)i530-3170bd9a3c2e5d8aac70dd132b0908771dbb1897f0db41650c516d7389a96e590 (KEY)0079428720160000063000301182analyticalcapacitancemodelforthroughsiliconviasinf DE-627 ger DE-627 rakwb eng 620 DNB Weerasekera, Roshan verfasserin aut An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs. 2.5-D Silicon through-silicon via (TSV) Integrated circuit modeling Substrates compact modeling Crosstalk Capacitance Analytical models Through-silicon vias through-silicon interposer (TSI) Katti, Guruprasad oth Dutta, Rahul oth Zhang, Songbai oth Chang, Ka Fai oth Zhou, Jun oth Bhattacharya, Surya oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 63(2016), 3, Seite 1182-1188 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:63 year:2016 number:3 pages:1182-1188 http://dx.doi.org/10.1109/TED.2016.2522501 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407376 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 63 2016 3 1182-1188 |
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10.1109/TED.2016.2522501 doi PQ20160430 (DE-627)OLC1973864266 (DE-599)GBVOLC1973864266 (PRQ)i530-3170bd9a3c2e5d8aac70dd132b0908771dbb1897f0db41650c516d7389a96e590 (KEY)0079428720160000063000301182analyticalcapacitancemodelforthroughsiliconviasinf DE-627 ger DE-627 rakwb eng 620 DNB Weerasekera, Roshan verfasserin aut An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs. 2.5-D Silicon through-silicon via (TSV) Integrated circuit modeling Substrates compact modeling Crosstalk Capacitance Analytical models Through-silicon vias through-silicon interposer (TSI) Katti, Guruprasad oth Dutta, Rahul oth Zhang, Songbai oth Chang, Ka Fai oth Zhou, Jun oth Bhattacharya, Surya oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 63(2016), 3, Seite 1182-1188 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:63 year:2016 number:3 pages:1182-1188 http://dx.doi.org/10.1109/TED.2016.2522501 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407376 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 63 2016 3 1182-1188 |
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Weerasekera, Roshan |
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Weerasekera, Roshan ddc 620 misc 2.5-D misc Silicon misc through-silicon via (TSV) misc Integrated circuit modeling misc Substrates misc compact modeling misc Crosstalk misc Capacitance misc Analytical models misc Through-silicon vias misc through-silicon interposer (TSI) An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate |
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620 DNB An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate 2.5-D Silicon through-silicon via (TSV) Integrated circuit modeling Substrates compact modeling Crosstalk Capacitance Analytical models Through-silicon vias through-silicon interposer (TSI) |
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analytical capacitance model for through-silicon vias in floating silicon substrate |
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An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate |
| abstract |
Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs. |
| abstractGer |
Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs. |
| abstract_unstemmed |
Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs. |
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An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate |
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Katti, Guruprasad Dutta, Rahul Zhang, Songbai Chang, Ka Fai Zhou, Jun Bhattacharya, Surya |
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