Capacitance-Enhanced Through-Silicon Via for Power Distribution Networks in 3D ICs
The through-silicon via (TSV) structure with enhanced capacitance is proposed for the power distribution network in 3D ICs, where an n+ contact on the top surface surrounding the oxide-silicon interface of the power TSV is used, instead of a p-substrate. The n+ contact supplies the majority carrier...
Ausführliche Beschreibung
Autor*in: |
Hwang, Chulsoon [verfasserIn] |
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Artikel |
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Sprache: |
Englisch |
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2016 |
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Übergeordnetes Werk: |
Enthalten in: IEEE electron device letters - New York, NY : IEEE, 1980, 37(2016), 4, Seite 478-481 |
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Übergeordnetes Werk: |
volume:37 ; year:2016 ; number:4 ; pages:478-481 |
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DOI / URN: |
10.1109/LED.2016.2535123 |
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Katalog-ID: |
OLC1973909634 |
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520 | |a The through-silicon via (TSV) structure with enhanced capacitance is proposed for the power distribution network in 3D ICs, where an n+ contact on the top surface surrounding the oxide-silicon interface of the power TSV is used, instead of a p-substrate. The n+ contact supplies the majority carrier to the channel, so the inversion layer can be formed at high frequencies. Since power TSVs are always biased to a voltage higher than the threshold voltage, changing the depletion layer to an inversion layer enables the larger capacitance in the proposed TSV. The voltage and frequency characteristics of the proposed TSV structure are simulated and compared with the conventional structure. In addition, a model based on <inline-formula> <tex-math notation="LaTeX">RC </tex-math></inline-formula> transmission line is proposed to estimate the capacitance degeneration at high frequencies. The model showed a good match with simulated results over a wide frequency range. | ||
650 | 4 | |a Metals | |
650 | 4 | |a Through-silicon via (TSV) | |
650 | 4 | |a Silicon | |
650 | 4 | |a Threshold voltage | |
650 | 4 | |a power distribution network | |
650 | 4 | |a 3D ICs | |
650 | 4 | |a Substrates | |
650 | 4 | |a Capacitance | |
650 | 4 | |a Through-silicon vias | |
650 | 4 | |a enhanced TSV capacitance | |
650 | 4 | |a Doping | |
700 | 1 | |a Achkir, Brice |4 oth | |
700 | 1 | |a Fan, Jun |4 oth | |
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10.1109/LED.2016.2535123 doi PQ20160430 (DE-627)OLC1973909634 (DE-599)GBVOLC1973909634 (PRQ)ieee_primary_0b00006484fb88380 (KEY)0101063820160000037000400478capacitanceenhancedthroughsiliconviaforpowerdistri DE-627 ger DE-627 rakwb eng 620 DNB Hwang, Chulsoon verfasserin aut Capacitance-Enhanced Through-Silicon Via for Power Distribution Networks in 3D ICs 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The through-silicon via (TSV) structure with enhanced capacitance is proposed for the power distribution network in 3D ICs, where an n+ contact on the top surface surrounding the oxide-silicon interface of the power TSV is used, instead of a p-substrate. The n+ contact supplies the majority carrier to the channel, so the inversion layer can be formed at high frequencies. Since power TSVs are always biased to a voltage higher than the threshold voltage, changing the depletion layer to an inversion layer enables the larger capacitance in the proposed TSV. The voltage and frequency characteristics of the proposed TSV structure are simulated and compared with the conventional structure. In addition, a model based on <inline-formula> <tex-math notation="LaTeX">RC </tex-math></inline-formula> transmission line is proposed to estimate the capacitance degeneration at high frequencies. The model showed a good match with simulated results over a wide frequency range. Metals Through-silicon via (TSV) Silicon Threshold voltage power distribution network 3D ICs Substrates Capacitance Through-silicon vias enhanced TSV capacitance Doping Achkir, Brice oth Fan, Jun oth Enthalten in IEEE electron device letters New York, NY : IEEE, 1980 37(2016), 4, Seite 478-481 (DE-627)129618993 (DE-600)245158-X (DE-576)015122115 0193-8576 nnns volume:37 year:2016 number:4 pages:478-481 http://dx.doi.org/10.1109/LED.2016.2535123 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7420586 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2061 GBV_ILN_4266 AR 37 2016 4 478-481 |
spelling |
10.1109/LED.2016.2535123 doi PQ20160430 (DE-627)OLC1973909634 (DE-599)GBVOLC1973909634 (PRQ)ieee_primary_0b00006484fb88380 (KEY)0101063820160000037000400478capacitanceenhancedthroughsiliconviaforpowerdistri DE-627 ger DE-627 rakwb eng 620 DNB Hwang, Chulsoon verfasserin aut Capacitance-Enhanced Through-Silicon Via for Power Distribution Networks in 3D ICs 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The through-silicon via (TSV) structure with enhanced capacitance is proposed for the power distribution network in 3D ICs, where an n+ contact on the top surface surrounding the oxide-silicon interface of the power TSV is used, instead of a p-substrate. The n+ contact supplies the majority carrier to the channel, so the inversion layer can be formed at high frequencies. Since power TSVs are always biased to a voltage higher than the threshold voltage, changing the depletion layer to an inversion layer enables the larger capacitance in the proposed TSV. The voltage and frequency characteristics of the proposed TSV structure are simulated and compared with the conventional structure. In addition, a model based on <inline-formula> <tex-math notation="LaTeX">RC </tex-math></inline-formula> transmission line is proposed to estimate the capacitance degeneration at high frequencies. The model showed a good match with simulated results over a wide frequency range. Metals Through-silicon via (TSV) Silicon Threshold voltage power distribution network 3D ICs Substrates Capacitance Through-silicon vias enhanced TSV capacitance Doping Achkir, Brice oth Fan, Jun oth Enthalten in IEEE electron device letters New York, NY : IEEE, 1980 37(2016), 4, Seite 478-481 (DE-627)129618993 (DE-600)245158-X (DE-576)015122115 0193-8576 nnns volume:37 year:2016 number:4 pages:478-481 http://dx.doi.org/10.1109/LED.2016.2535123 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7420586 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2061 GBV_ILN_4266 AR 37 2016 4 478-481 |
allfields_unstemmed |
10.1109/LED.2016.2535123 doi PQ20160430 (DE-627)OLC1973909634 (DE-599)GBVOLC1973909634 (PRQ)ieee_primary_0b00006484fb88380 (KEY)0101063820160000037000400478capacitanceenhancedthroughsiliconviaforpowerdistri DE-627 ger DE-627 rakwb eng 620 DNB Hwang, Chulsoon verfasserin aut Capacitance-Enhanced Through-Silicon Via for Power Distribution Networks in 3D ICs 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The through-silicon via (TSV) structure with enhanced capacitance is proposed for the power distribution network in 3D ICs, where an n+ contact on the top surface surrounding the oxide-silicon interface of the power TSV is used, instead of a p-substrate. The n+ contact supplies the majority carrier to the channel, so the inversion layer can be formed at high frequencies. Since power TSVs are always biased to a voltage higher than the threshold voltage, changing the depletion layer to an inversion layer enables the larger capacitance in the proposed TSV. The voltage and frequency characteristics of the proposed TSV structure are simulated and compared with the conventional structure. In addition, a model based on <inline-formula> <tex-math notation="LaTeX">RC </tex-math></inline-formula> transmission line is proposed to estimate the capacitance degeneration at high frequencies. The model showed a good match with simulated results over a wide frequency range. Metals Through-silicon via (TSV) Silicon Threshold voltage power distribution network 3D ICs Substrates Capacitance Through-silicon vias enhanced TSV capacitance Doping Achkir, Brice oth Fan, Jun oth Enthalten in IEEE electron device letters New York, NY : IEEE, 1980 37(2016), 4, Seite 478-481 (DE-627)129618993 (DE-600)245158-X (DE-576)015122115 0193-8576 nnns volume:37 year:2016 number:4 pages:478-481 http://dx.doi.org/10.1109/LED.2016.2535123 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7420586 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2061 GBV_ILN_4266 AR 37 2016 4 478-481 |
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10.1109/LED.2016.2535123 doi PQ20160430 (DE-627)OLC1973909634 (DE-599)GBVOLC1973909634 (PRQ)ieee_primary_0b00006484fb88380 (KEY)0101063820160000037000400478capacitanceenhancedthroughsiliconviaforpowerdistri DE-627 ger DE-627 rakwb eng 620 DNB Hwang, Chulsoon verfasserin aut Capacitance-Enhanced Through-Silicon Via for Power Distribution Networks in 3D ICs 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The through-silicon via (TSV) structure with enhanced capacitance is proposed for the power distribution network in 3D ICs, where an n+ contact on the top surface surrounding the oxide-silicon interface of the power TSV is used, instead of a p-substrate. The n+ contact supplies the majority carrier to the channel, so the inversion layer can be formed at high frequencies. Since power TSVs are always biased to a voltage higher than the threshold voltage, changing the depletion layer to an inversion layer enables the larger capacitance in the proposed TSV. The voltage and frequency characteristics of the proposed TSV structure are simulated and compared with the conventional structure. In addition, a model based on <inline-formula> <tex-math notation="LaTeX">RC </tex-math></inline-formula> transmission line is proposed to estimate the capacitance degeneration at high frequencies. The model showed a good match with simulated results over a wide frequency range. Metals Through-silicon via (TSV) Silicon Threshold voltage power distribution network 3D ICs Substrates Capacitance Through-silicon vias enhanced TSV capacitance Doping Achkir, Brice oth Fan, Jun oth Enthalten in IEEE electron device letters New York, NY : IEEE, 1980 37(2016), 4, Seite 478-481 (DE-627)129618993 (DE-600)245158-X (DE-576)015122115 0193-8576 nnns volume:37 year:2016 number:4 pages:478-481 http://dx.doi.org/10.1109/LED.2016.2535123 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7420586 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2061 GBV_ILN_4266 AR 37 2016 4 478-481 |
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10.1109/LED.2016.2535123 doi PQ20160430 (DE-627)OLC1973909634 (DE-599)GBVOLC1973909634 (PRQ)ieee_primary_0b00006484fb88380 (KEY)0101063820160000037000400478capacitanceenhancedthroughsiliconviaforpowerdistri DE-627 ger DE-627 rakwb eng 620 DNB Hwang, Chulsoon verfasserin aut Capacitance-Enhanced Through-Silicon Via for Power Distribution Networks in 3D ICs 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The through-silicon via (TSV) structure with enhanced capacitance is proposed for the power distribution network in 3D ICs, where an n+ contact on the top surface surrounding the oxide-silicon interface of the power TSV is used, instead of a p-substrate. The n+ contact supplies the majority carrier to the channel, so the inversion layer can be formed at high frequencies. Since power TSVs are always biased to a voltage higher than the threshold voltage, changing the depletion layer to an inversion layer enables the larger capacitance in the proposed TSV. The voltage and frequency characteristics of the proposed TSV structure are simulated and compared with the conventional structure. In addition, a model based on <inline-formula> <tex-math notation="LaTeX">RC </tex-math></inline-formula> transmission line is proposed to estimate the capacitance degeneration at high frequencies. The model showed a good match with simulated results over a wide frequency range. Metals Through-silicon via (TSV) Silicon Threshold voltage power distribution network 3D ICs Substrates Capacitance Through-silicon vias enhanced TSV capacitance Doping Achkir, Brice oth Fan, Jun oth Enthalten in IEEE electron device letters New York, NY : IEEE, 1980 37(2016), 4, Seite 478-481 (DE-627)129618993 (DE-600)245158-X (DE-576)015122115 0193-8576 nnns volume:37 year:2016 number:4 pages:478-481 http://dx.doi.org/10.1109/LED.2016.2535123 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7420586 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2061 GBV_ILN_4266 AR 37 2016 4 478-481 |
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Capacitance-Enhanced Through-Silicon Via for Power Distribution Networks in 3D ICs |
abstract |
The through-silicon via (TSV) structure with enhanced capacitance is proposed for the power distribution network in 3D ICs, where an n+ contact on the top surface surrounding the oxide-silicon interface of the power TSV is used, instead of a p-substrate. The n+ contact supplies the majority carrier to the channel, so the inversion layer can be formed at high frequencies. Since power TSVs are always biased to a voltage higher than the threshold voltage, changing the depletion layer to an inversion layer enables the larger capacitance in the proposed TSV. The voltage and frequency characteristics of the proposed TSV structure are simulated and compared with the conventional structure. In addition, a model based on <inline-formula> <tex-math notation="LaTeX">RC </tex-math></inline-formula> transmission line is proposed to estimate the capacitance degeneration at high frequencies. The model showed a good match with simulated results over a wide frequency range. |
abstractGer |
The through-silicon via (TSV) structure with enhanced capacitance is proposed for the power distribution network in 3D ICs, where an n+ contact on the top surface surrounding the oxide-silicon interface of the power TSV is used, instead of a p-substrate. The n+ contact supplies the majority carrier to the channel, so the inversion layer can be formed at high frequencies. Since power TSVs are always biased to a voltage higher than the threshold voltage, changing the depletion layer to an inversion layer enables the larger capacitance in the proposed TSV. The voltage and frequency characteristics of the proposed TSV structure are simulated and compared with the conventional structure. In addition, a model based on <inline-formula> <tex-math notation="LaTeX">RC </tex-math></inline-formula> transmission line is proposed to estimate the capacitance degeneration at high frequencies. The model showed a good match with simulated results over a wide frequency range. |
abstract_unstemmed |
The through-silicon via (TSV) structure with enhanced capacitance is proposed for the power distribution network in 3D ICs, where an n+ contact on the top surface surrounding the oxide-silicon interface of the power TSV is used, instead of a p-substrate. The n+ contact supplies the majority carrier to the channel, so the inversion layer can be formed at high frequencies. Since power TSVs are always biased to a voltage higher than the threshold voltage, changing the depletion layer to an inversion layer enables the larger capacitance in the proposed TSV. The voltage and frequency characteristics of the proposed TSV structure are simulated and compared with the conventional structure. In addition, a model based on <inline-formula> <tex-math notation="LaTeX">RC </tex-math></inline-formula> transmission line is proposed to estimate the capacitance degeneration at high frequencies. The model showed a good match with simulated results over a wide frequency range. |
collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2061 GBV_ILN_4266 |
container_issue |
4 |
title_short |
Capacitance-Enhanced Through-Silicon Via for Power Distribution Networks in 3D ICs |
url |
http://dx.doi.org/10.1109/LED.2016.2535123 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7420586 |
remote_bool |
false |
author2 |
Achkir, Brice Fan, Jun |
author2Str |
Achkir, Brice Fan, Jun |
ppnlink |
129618993 |
mediatype_str_mv |
n |
isOA_txt |
false |
hochschulschrift_bool |
false |
author2_role |
oth oth |
doi_str |
10.1109/LED.2016.2535123 |
up_date |
2024-07-04T03:23:00.144Z |
_version_ |
1803617178905214976 |
fullrecord_marcxml |
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7.40018 |