A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad
This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save batter...
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| Autor*in: |
Teerachot Siriburanon [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2016 |
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| Übergeordnetes Werk: |
Enthalten in: IEEE journal of solid state circuits - New York, NY : IEEE, 1966, 51(2016), 5, Seite 1246 |
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| Übergeordnetes Werk: |
volume:51 ; year:2016 ; number:5 ; pages:1246 |
| Links: |
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| DOI / URN: |
10.1109/JSSC.2016.2529004 |
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| Katalog-ID: |
OLC1974982920 |
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| 245 | 1 | 2 | |a A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad |
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| 520 | |a This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance [Formula Omitted] of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves [Formula Omitted] at 100 kHz offset, [Formula Omitted] at 10 MHz offset, and a figure-of-merit (FoM) of [Formula Omitted]. | ||
| 650 | 4 | |a Synthesizers | |
| 650 | 4 | |a injection-locking | |
| 650 | 4 | |a phase-locked loop (PLL) | |
| 650 | 4 | |a CMOS | |
| 650 | 4 | |a Calibration | |
| 650 | 4 | |a subsampling | |
| 650 | 4 | |a Phase locked loops | |
| 650 | 4 | |a Phase noise | |
| 650 | 4 | |a IEEE 802.11ad | |
| 650 | 4 | |a quadrature injection-locked oscillator (QILO) | |
| 650 | 4 | |a 60 GHz | |
| 650 | 4 | |a Signal to noise ratio | |
| 650 | 4 | |a ILFD | |
| 650 | 4 | |a WiGig | |
| 650 | 4 | |a low-power | |
| 650 | 4 | |a mm-wave | |
| 650 | 4 | |a Bandwidth | |
| 700 | 0 | |a Satoshi Kondo |4 oth | |
| 700 | 0 | |a Makihiko Katsuragi |4 oth | |
| 700 | 0 | |a Hanli Liu |4 oth | |
| 700 | 0 | |a Kento Kimura |4 oth | |
| 700 | 0 | |a Wei Deng |4 oth | |
| 700 | 0 | |a Kenichi Okada |4 oth | |
| 700 | 0 | |a Akira Matsuzawa |4 oth | |
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10.1109/JSSC.2016.2529004 doi PQ20160610 (DE-627)OLC1974982920 (DE-599)GBVOLC1974982920 (PRQ)p530-b79a3517a772bdbd979897947925cd965d5b49ea12788799855c9a070c0a9e890 (KEY)0050684220160000051000501246lowpowerlownoisemmwavesubsamplingpllusingdualstepm DE-627 ger DE-627 rakwb eng 620 DNB Teerachot Siriburanon verfasserin aut A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance [Formula Omitted] of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves [Formula Omitted] at 100 kHz offset, [Formula Omitted] at 10 MHz offset, and a figure-of-merit (FoM) of [Formula Omitted]. Synthesizers injection-locking phase-locked loop (PLL) CMOS Calibration subsampling Phase locked loops Phase noise IEEE 802.11ad quadrature injection-locked oscillator (QILO) 60 GHz Signal to noise ratio ILFD WiGig low-power mm-wave Bandwidth Satoshi Kondo oth Makihiko Katsuragi oth Hanli Liu oth Kento Kimura oth Wei Deng oth Kenichi Okada oth Akira Matsuzawa oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 5, Seite 1246 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:5 pages:1246 http://dx.doi.org/10.1109/JSSC.2016.2529004 Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 5 1246 |
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10.1109/JSSC.2016.2529004 doi PQ20160610 (DE-627)OLC1974982920 (DE-599)GBVOLC1974982920 (PRQ)p530-b79a3517a772bdbd979897947925cd965d5b49ea12788799855c9a070c0a9e890 (KEY)0050684220160000051000501246lowpowerlownoisemmwavesubsamplingpllusingdualstepm DE-627 ger DE-627 rakwb eng 620 DNB Teerachot Siriburanon verfasserin aut A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance [Formula Omitted] of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves [Formula Omitted] at 100 kHz offset, [Formula Omitted] at 10 MHz offset, and a figure-of-merit (FoM) of [Formula Omitted]. Synthesizers injection-locking phase-locked loop (PLL) CMOS Calibration subsampling Phase locked loops Phase noise IEEE 802.11ad quadrature injection-locked oscillator (QILO) 60 GHz Signal to noise ratio ILFD WiGig low-power mm-wave Bandwidth Satoshi Kondo oth Makihiko Katsuragi oth Hanli Liu oth Kento Kimura oth Wei Deng oth Kenichi Okada oth Akira Matsuzawa oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 5, Seite 1246 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:5 pages:1246 http://dx.doi.org/10.1109/JSSC.2016.2529004 Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 5 1246 |
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10.1109/JSSC.2016.2529004 doi PQ20160610 (DE-627)OLC1974982920 (DE-599)GBVOLC1974982920 (PRQ)p530-b79a3517a772bdbd979897947925cd965d5b49ea12788799855c9a070c0a9e890 (KEY)0050684220160000051000501246lowpowerlownoisemmwavesubsamplingpllusingdualstepm DE-627 ger DE-627 rakwb eng 620 DNB Teerachot Siriburanon verfasserin aut A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance [Formula Omitted] of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves [Formula Omitted] at 100 kHz offset, [Formula Omitted] at 10 MHz offset, and a figure-of-merit (FoM) of [Formula Omitted]. Synthesizers injection-locking phase-locked loop (PLL) CMOS Calibration subsampling Phase locked loops Phase noise IEEE 802.11ad quadrature injection-locked oscillator (QILO) 60 GHz Signal to noise ratio ILFD WiGig low-power mm-wave Bandwidth Satoshi Kondo oth Makihiko Katsuragi oth Hanli Liu oth Kento Kimura oth Wei Deng oth Kenichi Okada oth Akira Matsuzawa oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 5, Seite 1246 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:5 pages:1246 http://dx.doi.org/10.1109/JSSC.2016.2529004 Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 5 1246 |
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10.1109/JSSC.2016.2529004 doi PQ20160610 (DE-627)OLC1974982920 (DE-599)GBVOLC1974982920 (PRQ)p530-b79a3517a772bdbd979897947925cd965d5b49ea12788799855c9a070c0a9e890 (KEY)0050684220160000051000501246lowpowerlownoisemmwavesubsamplingpllusingdualstepm DE-627 ger DE-627 rakwb eng 620 DNB Teerachot Siriburanon verfasserin aut A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance [Formula Omitted] of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves [Formula Omitted] at 100 kHz offset, [Formula Omitted] at 10 MHz offset, and a figure-of-merit (FoM) of [Formula Omitted]. Synthesizers injection-locking phase-locked loop (PLL) CMOS Calibration subsampling Phase locked loops Phase noise IEEE 802.11ad quadrature injection-locked oscillator (QILO) 60 GHz Signal to noise ratio ILFD WiGig low-power mm-wave Bandwidth Satoshi Kondo oth Makihiko Katsuragi oth Hanli Liu oth Kento Kimura oth Wei Deng oth Kenichi Okada oth Akira Matsuzawa oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 5, Seite 1246 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:5 pages:1246 http://dx.doi.org/10.1109/JSSC.2016.2529004 Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 5 1246 |
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10.1109/JSSC.2016.2529004 doi PQ20160610 (DE-627)OLC1974982920 (DE-599)GBVOLC1974982920 (PRQ)p530-b79a3517a772bdbd979897947925cd965d5b49ea12788799855c9a070c0a9e890 (KEY)0050684220160000051000501246lowpowerlownoisemmwavesubsamplingpllusingdualstepm DE-627 ger DE-627 rakwb eng 620 DNB Teerachot Siriburanon verfasserin aut A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance [Formula Omitted] of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves [Formula Omitted] at 100 kHz offset, [Formula Omitted] at 10 MHz offset, and a figure-of-merit (FoM) of [Formula Omitted]. Synthesizers injection-locking phase-locked loop (PLL) CMOS Calibration subsampling Phase locked loops Phase noise IEEE 802.11ad quadrature injection-locked oscillator (QILO) 60 GHz Signal to noise ratio ILFD WiGig low-power mm-wave Bandwidth Satoshi Kondo oth Makihiko Katsuragi oth Hanli Liu oth Kento Kimura oth Wei Deng oth Kenichi Okada oth Akira Matsuzawa oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 5, Seite 1246 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:5 pages:1246 http://dx.doi.org/10.1109/JSSC.2016.2529004 Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 5 1246 |
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Synthesizers injection-locking phase-locked loop (PLL) CMOS Calibration subsampling Phase locked loops Phase noise IEEE 802.11ad quadrature injection-locked oscillator (QILO) 60 GHz Signal to noise ratio ILFD WiGig low-power mm-wave Bandwidth |
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Teerachot Siriburanon @@aut@@ Satoshi Kondo @@oth@@ Makihiko Katsuragi @@oth@@ Hanli Liu @@oth@@ Kento Kimura @@oth@@ Wei Deng @@oth@@ Kenichi Okada @@oth@@ Akira Matsuzawa @@oth@@ |
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Teerachot Siriburanon |
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Teerachot Siriburanon ddc 620 misc Synthesizers misc injection-locking misc phase-locked loop (PLL) misc CMOS misc Calibration misc subsampling misc Phase locked loops misc Phase noise misc IEEE 802.11ad misc quadrature injection-locked oscillator (QILO) misc 60 GHz misc Signal to noise ratio misc ILFD misc WiGig misc low-power misc mm-wave misc Bandwidth A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad |
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620 DNB A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad Synthesizers injection-locking phase-locked loop (PLL) CMOS Calibration subsampling Phase locked loops Phase noise IEEE 802.11ad quadrature injection-locked oscillator (QILO) 60 GHz Signal to noise ratio ILFD WiGig low-power mm-wave Bandwidth |
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ddc 620 misc Synthesizers misc injection-locking misc phase-locked loop (PLL) misc CMOS misc Calibration misc subsampling misc Phase locked loops misc Phase noise misc IEEE 802.11ad misc quadrature injection-locked oscillator (QILO) misc 60 GHz misc Signal to noise ratio misc ILFD misc WiGig misc low-power misc mm-wave misc Bandwidth |
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ddc 620 misc Synthesizers misc injection-locking misc phase-locked loop (PLL) misc CMOS misc Calibration misc subsampling misc Phase locked loops misc Phase noise misc IEEE 802.11ad misc quadrature injection-locked oscillator (QILO) misc 60 GHz misc Signal to noise ratio misc ILFD misc WiGig misc low-power misc mm-wave misc Bandwidth |
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ddc 620 misc Synthesizers misc injection-locking misc phase-locked loop (PLL) misc CMOS misc Calibration misc subsampling misc Phase locked loops misc Phase noise misc IEEE 802.11ad misc quadrature injection-locked oscillator (QILO) misc 60 GHz misc Signal to noise ratio misc ILFD misc WiGig misc low-power misc mm-wave misc Bandwidth |
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A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad |
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A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad |
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10.1109/JSSC.2016.2529004 |
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low-power low-noise mm-wave subsampling pll using dual-step-mixing ilfd and tail-coupling quadrature injection-locked oscillator for ieee 802.11ad |
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A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad |
| abstract |
This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance [Formula Omitted] of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves [Formula Omitted] at 100 kHz offset, [Formula Omitted] at 10 MHz offset, and a figure-of-merit (FoM) of [Formula Omitted]. |
| abstractGer |
This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance [Formula Omitted] of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves [Formula Omitted] at 100 kHz offset, [Formula Omitted] at 10 MHz offset, and a figure-of-merit (FoM) of [Formula Omitted]. |
| abstract_unstemmed |
This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance [Formula Omitted] of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves [Formula Omitted] at 100 kHz offset, [Formula Omitted] at 10 MHz offset, and a figure-of-merit (FoM) of [Formula Omitted]. |
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| title_short |
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad |
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http://dx.doi.org/10.1109/JSSC.2016.2529004 |
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Satoshi Kondo Makihiko Katsuragi Hanli Liu Kento Kimura Wei Deng Kenichi Okada Akira Matsuzawa |
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Satoshi Kondo Makihiko Katsuragi Hanli Liu Kento Kimura Wei Deng Kenichi Okada Akira Matsuzawa |
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