Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey
Time-triggered architectures form an important component of many distributed computing platforms for safety-critical real-time applications such as avionics and automotive control systems. TTA, FlexRay, and TTCAN are examples of such time-triggered architectures that have been popular in recent time...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Saha, Indranil [verfasserIn] |
|---|
| Format: |
Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
2016 |
|---|
| Schlagwörter: |
|---|
| Übergeordnetes Werk: |
Enthalten in: Proceedings of the IEEE - New York, NY [u.a.] : IEEE, 1963, 104(2016), 5, Seite 904-922 |
|---|---|
| Übergeordnetes Werk: |
volume:104 ; year:2016 ; number:5 ; pages:904-922 |
| Links: |
|---|
| DOI / URN: |
10.1109/JPROC.2016.2519247 |
|---|
| Katalog-ID: |
OLC1975219643 |
|---|
| LEADER | 01000caa a2200265 4500 | ||
|---|---|---|---|
| 001 | OLC1975219643 | ||
| 003 | DE-627 | ||
| 005 | 20220216172202.0 | ||
| 007 | tu | ||
| 008 | 160609s2016 xx ||||| 00| ||eng c | ||
| 024 | 7 | |a 10.1109/JPROC.2016.2519247 |2 doi | |
| 028 | 5 | 2 | |a PQ20160719 |
| 035 | |a (DE-627)OLC1975219643 | ||
| 035 | |a (DE-599)GBVOLC1975219643 | ||
| 035 | |a (PRQ)i824-9d821ee4f5d2b7cb7f30260774c7e8bc4955b29a4343fee8d2ed016c04c85d9f0 | ||
| 035 | |a (KEY)0074176020160000104000500904formalverificationoffaulttolerantstartupalgorithms | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 082 | 0 | 4 | |a 620 |q DNB |
| 084 | |a 53.00 |2 bkl | ||
| 084 | |a 53.70 |2 bkl | ||
| 084 | |a 05.42 |2 bkl | ||
| 084 | |a 53.76 |2 bkl | ||
| 100 | 1 | |a Saha, Indranil |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey |
| 264 | 1 | |c 2016 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a ohne Hilfsmittel zu benutzen |b n |2 rdamedia | ||
| 338 | |a Band |b nc |2 rdacarrier | ||
| 520 | |a Time-triggered architectures form an important component of many distributed computing platforms for safety-critical real-time applications such as avionics and automotive control systems. TTA, FlexRay, and TTCAN are examples of such time-triggered architectures that have been popular in recent times. These architectures involve a number of algorithms for synchronizing a set of distributed computing nodes for meaningful exchange of data among them. The algorithms include a startup algorithm whose job is to integrate one or more nodes into the group of communicating nodes. The startup algorithm runs on every node when the system is powered up, and again after a failure occurs. Some critical issues need to be considered in the design of the startup algorithms, for example, the algorithms should be robust under reasonable assumptions of failures of nodes and channels. The safety-critical nature of the applications where these algorithms are used demands rigorous verification of these algorithms, and there have been numerous attempts to use formal verification techniques for this purpose. This paper focuses on various formal verification efforts carried out for ensuring the correctness of the startup algorithms. In particular, the verification of different startup algorithms used in three time-triggered architectures, TTA, FlexRay, and TTCAN, is studied, compared, and contrasted. Besides presenting the various verification approaches for these algorithms, the gaps and possible improvements on the verification efforts are also indicated. | ||
| 650 | 4 | |a Fault tolerant systems | |
| 650 | 4 | |a TTA | |
| 650 | 4 | |a Computer architecture | |
| 650 | 4 | |a Synchronization | |
| 650 | 4 | |a Algorithm design and analysis | |
| 650 | 4 | |a Cyber-physical systems | |
| 650 | 4 | |a TTCAN | |
| 650 | 4 | |a startup algorithms | |
| 650 | 4 | |a verification | |
| 650 | 4 | |a time-triggered architectures | |
| 650 | 4 | |a modeling | |
| 650 | 4 | |a FlexRay | |
| 650 | 4 | |a Fault tolerance | |
| 650 | 4 | |a Formal verification | |
| 650 | 4 | |a Distributed processing | |
| 650 | 4 | |a Electronic design automation | |
| 650 | 4 | |a Algorithms | |
| 700 | 1 | |a Roy, Suman |4 oth | |
| 700 | 1 | |a Ramesh, S |4 oth | |
| 773 | 0 | 8 | |i Enthalten in |t Proceedings of the IEEE |d New York, NY [u.a.] : IEEE, 1963 |g 104(2016), 5, Seite 904-922 |w (DE-627)129505404 |w (DE-600)209133-1 |w (DE-576)014909421 |x 0018-9219 |7 nnns |
| 773 | 1 | 8 | |g volume:104 |g year:2016 |g number:5 |g pages:904-922 |
| 856 | 4 | 1 | |u http://dx.doi.org/10.1109/JPROC.2016.2519247 |3 Volltext |
| 856 | 4 | 2 | |u http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440778 |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_OLC | ||
| 912 | |a SSG-OLC-TEC | ||
| 912 | |a GBV_ILN_20 | ||
| 912 | |a GBV_ILN_40 | ||
| 912 | |a GBV_ILN_59 | ||
| 912 | |a GBV_ILN_65 | ||
| 912 | |a GBV_ILN_70 | ||
| 912 | |a GBV_ILN_170 | ||
| 912 | |a GBV_ILN_2002 | ||
| 912 | |a GBV_ILN_2004 | ||
| 912 | |a GBV_ILN_2005 | ||
| 912 | |a GBV_ILN_2014 | ||
| 912 | |a GBV_ILN_2045 | ||
| 912 | |a GBV_ILN_2061 | ||
| 912 | |a GBV_ILN_4311 | ||
| 936 | b | k | |a 53.00 |q AVZ |
| 936 | b | k | |a 53.70 |q AVZ |
| 936 | b | k | |a 05.42 |q AVZ |
| 936 | b | k | |a 53.76 |q AVZ |
| 951 | |a AR | ||
| 952 | |d 104 |j 2016 |e 5 |h 904-922 | ||
| author_variant |
i s is |
|---|---|
| matchkey_str |
article:00189219:2016----::omleiiainfaltlrnsatploihsotmtig |
| hierarchy_sort_str |
2016 |
| bklnumber |
53.00 53.70 05.42 53.76 |
| publishDate |
2016 |
| allfields |
10.1109/JPROC.2016.2519247 doi PQ20160719 (DE-627)OLC1975219643 (DE-599)GBVOLC1975219643 (PRQ)i824-9d821ee4f5d2b7cb7f30260774c7e8bc4955b29a4343fee8d2ed016c04c85d9f0 (KEY)0074176020160000104000500904formalverificationoffaulttolerantstartupalgorithms DE-627 ger DE-627 rakwb eng 620 DNB 53.00 bkl 53.70 bkl 05.42 bkl 53.76 bkl Saha, Indranil verfasserin aut Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Time-triggered architectures form an important component of many distributed computing platforms for safety-critical real-time applications such as avionics and automotive control systems. TTA, FlexRay, and TTCAN are examples of such time-triggered architectures that have been popular in recent times. These architectures involve a number of algorithms for synchronizing a set of distributed computing nodes for meaningful exchange of data among them. The algorithms include a startup algorithm whose job is to integrate one or more nodes into the group of communicating nodes. The startup algorithm runs on every node when the system is powered up, and again after a failure occurs. Some critical issues need to be considered in the design of the startup algorithms, for example, the algorithms should be robust under reasonable assumptions of failures of nodes and channels. The safety-critical nature of the applications where these algorithms are used demands rigorous verification of these algorithms, and there have been numerous attempts to use formal verification techniques for this purpose. This paper focuses on various formal verification efforts carried out for ensuring the correctness of the startup algorithms. In particular, the verification of different startup algorithms used in three time-triggered architectures, TTA, FlexRay, and TTCAN, is studied, compared, and contrasted. Besides presenting the various verification approaches for these algorithms, the gaps and possible improvements on the verification efforts are also indicated. Fault tolerant systems TTA Computer architecture Synchronization Algorithm design and analysis Cyber-physical systems TTCAN startup algorithms verification time-triggered architectures modeling FlexRay Fault tolerance Formal verification Distributed processing Electronic design automation Algorithms Roy, Suman oth Ramesh, S oth Enthalten in Proceedings of the IEEE New York, NY [u.a.] : IEEE, 1963 104(2016), 5, Seite 904-922 (DE-627)129505404 (DE-600)209133-1 (DE-576)014909421 0018-9219 nnns volume:104 year:2016 number:5 pages:904-922 http://dx.doi.org/10.1109/JPROC.2016.2519247 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440778 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_20 GBV_ILN_40 GBV_ILN_59 GBV_ILN_65 GBV_ILN_70 GBV_ILN_170 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2014 GBV_ILN_2045 GBV_ILN_2061 GBV_ILN_4311 53.00 AVZ 53.70 AVZ 05.42 AVZ 53.76 AVZ AR 104 2016 5 904-922 |
| spelling |
10.1109/JPROC.2016.2519247 doi PQ20160719 (DE-627)OLC1975219643 (DE-599)GBVOLC1975219643 (PRQ)i824-9d821ee4f5d2b7cb7f30260774c7e8bc4955b29a4343fee8d2ed016c04c85d9f0 (KEY)0074176020160000104000500904formalverificationoffaulttolerantstartupalgorithms DE-627 ger DE-627 rakwb eng 620 DNB 53.00 bkl 53.70 bkl 05.42 bkl 53.76 bkl Saha, Indranil verfasserin aut Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Time-triggered architectures form an important component of many distributed computing platforms for safety-critical real-time applications such as avionics and automotive control systems. TTA, FlexRay, and TTCAN are examples of such time-triggered architectures that have been popular in recent times. These architectures involve a number of algorithms for synchronizing a set of distributed computing nodes for meaningful exchange of data among them. The algorithms include a startup algorithm whose job is to integrate one or more nodes into the group of communicating nodes. The startup algorithm runs on every node when the system is powered up, and again after a failure occurs. Some critical issues need to be considered in the design of the startup algorithms, for example, the algorithms should be robust under reasonable assumptions of failures of nodes and channels. The safety-critical nature of the applications where these algorithms are used demands rigorous verification of these algorithms, and there have been numerous attempts to use formal verification techniques for this purpose. This paper focuses on various formal verification efforts carried out for ensuring the correctness of the startup algorithms. In particular, the verification of different startup algorithms used in three time-triggered architectures, TTA, FlexRay, and TTCAN, is studied, compared, and contrasted. Besides presenting the various verification approaches for these algorithms, the gaps and possible improvements on the verification efforts are also indicated. Fault tolerant systems TTA Computer architecture Synchronization Algorithm design and analysis Cyber-physical systems TTCAN startup algorithms verification time-triggered architectures modeling FlexRay Fault tolerance Formal verification Distributed processing Electronic design automation Algorithms Roy, Suman oth Ramesh, S oth Enthalten in Proceedings of the IEEE New York, NY [u.a.] : IEEE, 1963 104(2016), 5, Seite 904-922 (DE-627)129505404 (DE-600)209133-1 (DE-576)014909421 0018-9219 nnns volume:104 year:2016 number:5 pages:904-922 http://dx.doi.org/10.1109/JPROC.2016.2519247 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440778 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_20 GBV_ILN_40 GBV_ILN_59 GBV_ILN_65 GBV_ILN_70 GBV_ILN_170 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2014 GBV_ILN_2045 GBV_ILN_2061 GBV_ILN_4311 53.00 AVZ 53.70 AVZ 05.42 AVZ 53.76 AVZ AR 104 2016 5 904-922 |
| allfields_unstemmed |
10.1109/JPROC.2016.2519247 doi PQ20160719 (DE-627)OLC1975219643 (DE-599)GBVOLC1975219643 (PRQ)i824-9d821ee4f5d2b7cb7f30260774c7e8bc4955b29a4343fee8d2ed016c04c85d9f0 (KEY)0074176020160000104000500904formalverificationoffaulttolerantstartupalgorithms DE-627 ger DE-627 rakwb eng 620 DNB 53.00 bkl 53.70 bkl 05.42 bkl 53.76 bkl Saha, Indranil verfasserin aut Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Time-triggered architectures form an important component of many distributed computing platforms for safety-critical real-time applications such as avionics and automotive control systems. TTA, FlexRay, and TTCAN are examples of such time-triggered architectures that have been popular in recent times. These architectures involve a number of algorithms for synchronizing a set of distributed computing nodes for meaningful exchange of data among them. The algorithms include a startup algorithm whose job is to integrate one or more nodes into the group of communicating nodes. The startup algorithm runs on every node when the system is powered up, and again after a failure occurs. Some critical issues need to be considered in the design of the startup algorithms, for example, the algorithms should be robust under reasonable assumptions of failures of nodes and channels. The safety-critical nature of the applications where these algorithms are used demands rigorous verification of these algorithms, and there have been numerous attempts to use formal verification techniques for this purpose. This paper focuses on various formal verification efforts carried out for ensuring the correctness of the startup algorithms. In particular, the verification of different startup algorithms used in three time-triggered architectures, TTA, FlexRay, and TTCAN, is studied, compared, and contrasted. Besides presenting the various verification approaches for these algorithms, the gaps and possible improvements on the verification efforts are also indicated. Fault tolerant systems TTA Computer architecture Synchronization Algorithm design and analysis Cyber-physical systems TTCAN startup algorithms verification time-triggered architectures modeling FlexRay Fault tolerance Formal verification Distributed processing Electronic design automation Algorithms Roy, Suman oth Ramesh, S oth Enthalten in Proceedings of the IEEE New York, NY [u.a.] : IEEE, 1963 104(2016), 5, Seite 904-922 (DE-627)129505404 (DE-600)209133-1 (DE-576)014909421 0018-9219 nnns volume:104 year:2016 number:5 pages:904-922 http://dx.doi.org/10.1109/JPROC.2016.2519247 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440778 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_20 GBV_ILN_40 GBV_ILN_59 GBV_ILN_65 GBV_ILN_70 GBV_ILN_170 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2014 GBV_ILN_2045 GBV_ILN_2061 GBV_ILN_4311 53.00 AVZ 53.70 AVZ 05.42 AVZ 53.76 AVZ AR 104 2016 5 904-922 |
| allfieldsGer |
10.1109/JPROC.2016.2519247 doi PQ20160719 (DE-627)OLC1975219643 (DE-599)GBVOLC1975219643 (PRQ)i824-9d821ee4f5d2b7cb7f30260774c7e8bc4955b29a4343fee8d2ed016c04c85d9f0 (KEY)0074176020160000104000500904formalverificationoffaulttolerantstartupalgorithms DE-627 ger DE-627 rakwb eng 620 DNB 53.00 bkl 53.70 bkl 05.42 bkl 53.76 bkl Saha, Indranil verfasserin aut Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Time-triggered architectures form an important component of many distributed computing platforms for safety-critical real-time applications such as avionics and automotive control systems. TTA, FlexRay, and TTCAN are examples of such time-triggered architectures that have been popular in recent times. These architectures involve a number of algorithms for synchronizing a set of distributed computing nodes for meaningful exchange of data among them. The algorithms include a startup algorithm whose job is to integrate one or more nodes into the group of communicating nodes. The startup algorithm runs on every node when the system is powered up, and again after a failure occurs. Some critical issues need to be considered in the design of the startup algorithms, for example, the algorithms should be robust under reasonable assumptions of failures of nodes and channels. The safety-critical nature of the applications where these algorithms are used demands rigorous verification of these algorithms, and there have been numerous attempts to use formal verification techniques for this purpose. This paper focuses on various formal verification efforts carried out for ensuring the correctness of the startup algorithms. In particular, the verification of different startup algorithms used in three time-triggered architectures, TTA, FlexRay, and TTCAN, is studied, compared, and contrasted. Besides presenting the various verification approaches for these algorithms, the gaps and possible improvements on the verification efforts are also indicated. Fault tolerant systems TTA Computer architecture Synchronization Algorithm design and analysis Cyber-physical systems TTCAN startup algorithms verification time-triggered architectures modeling FlexRay Fault tolerance Formal verification Distributed processing Electronic design automation Algorithms Roy, Suman oth Ramesh, S oth Enthalten in Proceedings of the IEEE New York, NY [u.a.] : IEEE, 1963 104(2016), 5, Seite 904-922 (DE-627)129505404 (DE-600)209133-1 (DE-576)014909421 0018-9219 nnns volume:104 year:2016 number:5 pages:904-922 http://dx.doi.org/10.1109/JPROC.2016.2519247 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440778 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_20 GBV_ILN_40 GBV_ILN_59 GBV_ILN_65 GBV_ILN_70 GBV_ILN_170 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2014 GBV_ILN_2045 GBV_ILN_2061 GBV_ILN_4311 53.00 AVZ 53.70 AVZ 05.42 AVZ 53.76 AVZ AR 104 2016 5 904-922 |
| allfieldsSound |
10.1109/JPROC.2016.2519247 doi PQ20160719 (DE-627)OLC1975219643 (DE-599)GBVOLC1975219643 (PRQ)i824-9d821ee4f5d2b7cb7f30260774c7e8bc4955b29a4343fee8d2ed016c04c85d9f0 (KEY)0074176020160000104000500904formalverificationoffaulttolerantstartupalgorithms DE-627 ger DE-627 rakwb eng 620 DNB 53.00 bkl 53.70 bkl 05.42 bkl 53.76 bkl Saha, Indranil verfasserin aut Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Time-triggered architectures form an important component of many distributed computing platforms for safety-critical real-time applications such as avionics and automotive control systems. TTA, FlexRay, and TTCAN are examples of such time-triggered architectures that have been popular in recent times. These architectures involve a number of algorithms for synchronizing a set of distributed computing nodes for meaningful exchange of data among them. The algorithms include a startup algorithm whose job is to integrate one or more nodes into the group of communicating nodes. The startup algorithm runs on every node when the system is powered up, and again after a failure occurs. Some critical issues need to be considered in the design of the startup algorithms, for example, the algorithms should be robust under reasonable assumptions of failures of nodes and channels. The safety-critical nature of the applications where these algorithms are used demands rigorous verification of these algorithms, and there have been numerous attempts to use formal verification techniques for this purpose. This paper focuses on various formal verification efforts carried out for ensuring the correctness of the startup algorithms. In particular, the verification of different startup algorithms used in three time-triggered architectures, TTA, FlexRay, and TTCAN, is studied, compared, and contrasted. Besides presenting the various verification approaches for these algorithms, the gaps and possible improvements on the verification efforts are also indicated. Fault tolerant systems TTA Computer architecture Synchronization Algorithm design and analysis Cyber-physical systems TTCAN startup algorithms verification time-triggered architectures modeling FlexRay Fault tolerance Formal verification Distributed processing Electronic design automation Algorithms Roy, Suman oth Ramesh, S oth Enthalten in Proceedings of the IEEE New York, NY [u.a.] : IEEE, 1963 104(2016), 5, Seite 904-922 (DE-627)129505404 (DE-600)209133-1 (DE-576)014909421 0018-9219 nnns volume:104 year:2016 number:5 pages:904-922 http://dx.doi.org/10.1109/JPROC.2016.2519247 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440778 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_20 GBV_ILN_40 GBV_ILN_59 GBV_ILN_65 GBV_ILN_70 GBV_ILN_170 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2014 GBV_ILN_2045 GBV_ILN_2061 GBV_ILN_4311 53.00 AVZ 53.70 AVZ 05.42 AVZ 53.76 AVZ AR 104 2016 5 904-922 |
| language |
English |
| source |
Enthalten in Proceedings of the IEEE 104(2016), 5, Seite 904-922 volume:104 year:2016 number:5 pages:904-922 |
| sourceStr |
Enthalten in Proceedings of the IEEE 104(2016), 5, Seite 904-922 volume:104 year:2016 number:5 pages:904-922 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Fault tolerant systems TTA Computer architecture Synchronization Algorithm design and analysis Cyber-physical systems TTCAN startup algorithms verification time-triggered architectures modeling FlexRay Fault tolerance Formal verification Distributed processing Electronic design automation Algorithms |
| dewey-raw |
620 |
| isfreeaccess_bool |
false |
| container_title |
Proceedings of the IEEE |
| authorswithroles_txt_mv |
Saha, Indranil @@aut@@ Roy, Suman @@oth@@ Ramesh, S @@oth@@ |
| publishDateDaySort_date |
2016-01-01T00:00:00Z |
| hierarchy_top_id |
129505404 |
| dewey-sort |
3620 |
| id |
OLC1975219643 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1975219643</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20220216172202.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">160609s2016 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/JPROC.2016.2519247</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20160719</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1975219643</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1975219643</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)i824-9d821ee4f5d2b7cb7f30260774c7e8bc4955b29a4343fee8d2ed016c04c85d9f0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)0074176020160000104000500904formalverificationoffaulttolerantstartupalgorithms</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.00</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.70</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">05.42</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.76</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Saha, Indranil</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2016</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Time-triggered architectures form an important component of many distributed computing platforms for safety-critical real-time applications such as avionics and automotive control systems. TTA, FlexRay, and TTCAN are examples of such time-triggered architectures that have been popular in recent times. These architectures involve a number of algorithms for synchronizing a set of distributed computing nodes for meaningful exchange of data among them. The algorithms include a startup algorithm whose job is to integrate one or more nodes into the group of communicating nodes. The startup algorithm runs on every node when the system is powered up, and again after a failure occurs. Some critical issues need to be considered in the design of the startup algorithms, for example, the algorithms should be robust under reasonable assumptions of failures of nodes and channels. The safety-critical nature of the applications where these algorithms are used demands rigorous verification of these algorithms, and there have been numerous attempts to use formal verification techniques for this purpose. This paper focuses on various formal verification efforts carried out for ensuring the correctness of the startup algorithms. In particular, the verification of different startup algorithms used in three time-triggered architectures, TTA, FlexRay, and TTCAN, is studied, compared, and contrasted. Besides presenting the various verification approaches for these algorithms, the gaps and possible improvements on the verification efforts are also indicated.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fault tolerant systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">TTA</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer architecture</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Synchronization</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Algorithm design and analysis</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Cyber-physical systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">TTCAN</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">startup algorithms</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">verification</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">time-triggered architectures</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">modeling</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">FlexRay</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fault tolerance</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Formal verification</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Distributed processing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic design automation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Algorithms</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Roy, Suman</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Ramesh, S</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Proceedings of the IEEE</subfield><subfield code="d">New York, NY [u.a.] : IEEE, 1963</subfield><subfield code="g">104(2016), 5, Seite 904-922</subfield><subfield code="w">(DE-627)129505404</subfield><subfield code="w">(DE-600)209133-1</subfield><subfield code="w">(DE-576)014909421</subfield><subfield code="x">0018-9219</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:104</subfield><subfield code="g">year:2016</subfield><subfield code="g">number:5</subfield><subfield code="g">pages:904-922</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/JPROC.2016.2519247</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440778</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_20</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_59</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_65</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_170</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2002</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2014</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2045</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2061</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4311</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">53.00</subfield><subfield code="q">AVZ</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">53.70</subfield><subfield code="q">AVZ</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">05.42</subfield><subfield code="q">AVZ</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">53.76</subfield><subfield code="q">AVZ</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">104</subfield><subfield code="j">2016</subfield><subfield code="e">5</subfield><subfield code="h">904-922</subfield></datafield></record></collection>
|
| author |
Saha, Indranil |
| spellingShingle |
Saha, Indranil ddc 620 bkl 53.00 bkl 53.70 bkl 05.42 bkl 53.76 misc Fault tolerant systems misc TTA misc Computer architecture misc Synchronization misc Algorithm design and analysis misc Cyber-physical systems misc TTCAN misc startup algorithms misc verification misc time-triggered architectures misc modeling misc FlexRay misc Fault tolerance misc Formal verification misc Distributed processing misc Electronic design automation misc Algorithms Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey |
| authorStr |
Saha, Indranil |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)129505404 |
| format |
Article |
| dewey-ones |
620 - Engineering & allied operations |
| delete_txt_mv |
keep |
| author_role |
aut |
| collection |
OLC |
| remote_str |
false |
| illustrated |
Not Illustrated |
| issn |
0018-9219 |
| topic_title |
620 DNB 53.00 bkl 53.70 bkl 05.42 bkl 53.76 bkl Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey Fault tolerant systems TTA Computer architecture Synchronization Algorithm design and analysis Cyber-physical systems TTCAN startup algorithms verification time-triggered architectures modeling FlexRay Fault tolerance Formal verification Distributed processing Electronic design automation Algorithms |
| topic |
ddc 620 bkl 53.00 bkl 53.70 bkl 05.42 bkl 53.76 misc Fault tolerant systems misc TTA misc Computer architecture misc Synchronization misc Algorithm design and analysis misc Cyber-physical systems misc TTCAN misc startup algorithms misc verification misc time-triggered architectures misc modeling misc FlexRay misc Fault tolerance misc Formal verification misc Distributed processing misc Electronic design automation misc Algorithms |
| topic_unstemmed |
ddc 620 bkl 53.00 bkl 53.70 bkl 05.42 bkl 53.76 misc Fault tolerant systems misc TTA misc Computer architecture misc Synchronization misc Algorithm design and analysis misc Cyber-physical systems misc TTCAN misc startup algorithms misc verification misc time-triggered architectures misc modeling misc FlexRay misc Fault tolerance misc Formal verification misc Distributed processing misc Electronic design automation misc Algorithms |
| topic_browse |
ddc 620 bkl 53.00 bkl 53.70 bkl 05.42 bkl 53.76 misc Fault tolerant systems misc TTA misc Computer architecture misc Synchronization misc Algorithm design and analysis misc Cyber-physical systems misc TTCAN misc startup algorithms misc verification misc time-triggered architectures misc modeling misc FlexRay misc Fault tolerance misc Formal verification misc Distributed processing misc Electronic design automation misc Algorithms |
| format_facet |
Aufsätze Gedruckte Aufsätze |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
nc |
| author2_variant |
s r sr s r sr |
| hierarchy_parent_title |
Proceedings of the IEEE |
| hierarchy_parent_id |
129505404 |
| dewey-tens |
620 - Engineering |
| hierarchy_top_title |
Proceedings of the IEEE |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)129505404 (DE-600)209133-1 (DE-576)014909421 |
| title |
Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey |
| ctrlnum |
(DE-627)OLC1975219643 (DE-599)GBVOLC1975219643 (PRQ)i824-9d821ee4f5d2b7cb7f30260774c7e8bc4955b29a4343fee8d2ed016c04c85d9f0 (KEY)0074176020160000104000500904formalverificationoffaulttolerantstartupalgorithms |
| title_full |
Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey |
| author_sort |
Saha, Indranil |
| journal |
Proceedings of the IEEE |
| journalStr |
Proceedings of the IEEE |
| lang_code |
eng |
| isOA_bool |
false |
| dewey-hundreds |
600 - Technology |
| recordtype |
marc |
| publishDateSort |
2016 |
| contenttype_str_mv |
txt |
| container_start_page |
904 |
| author_browse |
Saha, Indranil |
| container_volume |
104 |
| class |
620 DNB 53.00 bkl 53.70 bkl 05.42 bkl 53.76 bkl |
| format_se |
Aufsätze |
| author-letter |
Saha, Indranil |
| doi_str_mv |
10.1109/JPROC.2016.2519247 |
| dewey-full |
620 |
| title_sort |
formal verification of fault-tolerant startup algorithms for time-triggered architectures: a survey |
| title_auth |
Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey |
| abstract |
Time-triggered architectures form an important component of many distributed computing platforms for safety-critical real-time applications such as avionics and automotive control systems. TTA, FlexRay, and TTCAN are examples of such time-triggered architectures that have been popular in recent times. These architectures involve a number of algorithms for synchronizing a set of distributed computing nodes for meaningful exchange of data among them. The algorithms include a startup algorithm whose job is to integrate one or more nodes into the group of communicating nodes. The startup algorithm runs on every node when the system is powered up, and again after a failure occurs. Some critical issues need to be considered in the design of the startup algorithms, for example, the algorithms should be robust under reasonable assumptions of failures of nodes and channels. The safety-critical nature of the applications where these algorithms are used demands rigorous verification of these algorithms, and there have been numerous attempts to use formal verification techniques for this purpose. This paper focuses on various formal verification efforts carried out for ensuring the correctness of the startup algorithms. In particular, the verification of different startup algorithms used in three time-triggered architectures, TTA, FlexRay, and TTCAN, is studied, compared, and contrasted. Besides presenting the various verification approaches for these algorithms, the gaps and possible improvements on the verification efforts are also indicated. |
| abstractGer |
Time-triggered architectures form an important component of many distributed computing platforms for safety-critical real-time applications such as avionics and automotive control systems. TTA, FlexRay, and TTCAN are examples of such time-triggered architectures that have been popular in recent times. These architectures involve a number of algorithms for synchronizing a set of distributed computing nodes for meaningful exchange of data among them. The algorithms include a startup algorithm whose job is to integrate one or more nodes into the group of communicating nodes. The startup algorithm runs on every node when the system is powered up, and again after a failure occurs. Some critical issues need to be considered in the design of the startup algorithms, for example, the algorithms should be robust under reasonable assumptions of failures of nodes and channels. The safety-critical nature of the applications where these algorithms are used demands rigorous verification of these algorithms, and there have been numerous attempts to use formal verification techniques for this purpose. This paper focuses on various formal verification efforts carried out for ensuring the correctness of the startup algorithms. In particular, the verification of different startup algorithms used in three time-triggered architectures, TTA, FlexRay, and TTCAN, is studied, compared, and contrasted. Besides presenting the various verification approaches for these algorithms, the gaps and possible improvements on the verification efforts are also indicated. |
| abstract_unstemmed |
Time-triggered architectures form an important component of many distributed computing platforms for safety-critical real-time applications such as avionics and automotive control systems. TTA, FlexRay, and TTCAN are examples of such time-triggered architectures that have been popular in recent times. These architectures involve a number of algorithms for synchronizing a set of distributed computing nodes for meaningful exchange of data among them. The algorithms include a startup algorithm whose job is to integrate one or more nodes into the group of communicating nodes. The startup algorithm runs on every node when the system is powered up, and again after a failure occurs. Some critical issues need to be considered in the design of the startup algorithms, for example, the algorithms should be robust under reasonable assumptions of failures of nodes and channels. The safety-critical nature of the applications where these algorithms are used demands rigorous verification of these algorithms, and there have been numerous attempts to use formal verification techniques for this purpose. This paper focuses on various formal verification efforts carried out for ensuring the correctness of the startup algorithms. In particular, the verification of different startup algorithms used in three time-triggered architectures, TTA, FlexRay, and TTCAN, is studied, compared, and contrasted. Besides presenting the various verification approaches for these algorithms, the gaps and possible improvements on the verification efforts are also indicated. |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_20 GBV_ILN_40 GBV_ILN_59 GBV_ILN_65 GBV_ILN_70 GBV_ILN_170 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2014 GBV_ILN_2045 GBV_ILN_2061 GBV_ILN_4311 |
| container_issue |
5 |
| title_short |
Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey |
| url |
http://dx.doi.org/10.1109/JPROC.2016.2519247 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440778 |
| remote_bool |
false |
| author2 |
Roy, Suman Ramesh, S |
| author2Str |
Roy, Suman Ramesh, S |
| ppnlink |
129505404 |
| mediatype_str_mv |
n |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| author2_role |
oth oth |
| doi_str |
10.1109/JPROC.2016.2519247 |
| up_date |
2024-07-04T06:03:35.995Z |
| _version_ |
1803627282822070272 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1975219643</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20220216172202.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">160609s2016 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/JPROC.2016.2519247</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20160719</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1975219643</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1975219643</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)i824-9d821ee4f5d2b7cb7f30260774c7e8bc4955b29a4343fee8d2ed016c04c85d9f0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)0074176020160000104000500904formalverificationoffaulttolerantstartupalgorithms</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.00</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.70</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">05.42</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.76</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Saha, Indranil</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Formal Verification of Fault-Tolerant Startup Algorithms for Time-Triggered Architectures: A Survey</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2016</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Time-triggered architectures form an important component of many distributed computing platforms for safety-critical real-time applications such as avionics and automotive control systems. TTA, FlexRay, and TTCAN are examples of such time-triggered architectures that have been popular in recent times. These architectures involve a number of algorithms for synchronizing a set of distributed computing nodes for meaningful exchange of data among them. The algorithms include a startup algorithm whose job is to integrate one or more nodes into the group of communicating nodes. The startup algorithm runs on every node when the system is powered up, and again after a failure occurs. Some critical issues need to be considered in the design of the startup algorithms, for example, the algorithms should be robust under reasonable assumptions of failures of nodes and channels. The safety-critical nature of the applications where these algorithms are used demands rigorous verification of these algorithms, and there have been numerous attempts to use formal verification techniques for this purpose. This paper focuses on various formal verification efforts carried out for ensuring the correctness of the startup algorithms. In particular, the verification of different startup algorithms used in three time-triggered architectures, TTA, FlexRay, and TTCAN, is studied, compared, and contrasted. Besides presenting the various verification approaches for these algorithms, the gaps and possible improvements on the verification efforts are also indicated.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fault tolerant systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">TTA</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer architecture</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Synchronization</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Algorithm design and analysis</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Cyber-physical systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">TTCAN</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">startup algorithms</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">verification</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">time-triggered architectures</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">modeling</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">FlexRay</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fault tolerance</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Formal verification</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Distributed processing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic design automation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Algorithms</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Roy, Suman</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Ramesh, S</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Proceedings of the IEEE</subfield><subfield code="d">New York, NY [u.a.] : IEEE, 1963</subfield><subfield code="g">104(2016), 5, Seite 904-922</subfield><subfield code="w">(DE-627)129505404</subfield><subfield code="w">(DE-600)209133-1</subfield><subfield code="w">(DE-576)014909421</subfield><subfield code="x">0018-9219</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:104</subfield><subfield code="g">year:2016</subfield><subfield code="g">number:5</subfield><subfield code="g">pages:904-922</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/JPROC.2016.2519247</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440778</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_20</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_59</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_65</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_170</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2002</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2014</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2045</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2061</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4311</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">53.00</subfield><subfield code="q">AVZ</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">53.70</subfield><subfield code="q">AVZ</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">05.42</subfield><subfield code="q">AVZ</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">53.76</subfield><subfield code="q">AVZ</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">104</subfield><subfield code="j">2016</subfield><subfield code="e">5</subfield><subfield code="h">904-922</subfield></datafield></record></collection>
|
| score |
7.400728 |