A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measure...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Raja, Immanuel [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2016 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on very large scale integration (VLSI) systems - New York, NY : Institute of Electrical and Electronics Engineers, 1993, 24(2016), 5, Seite 1975-1983 |
|---|---|
| Übergeordnetes Werk: |
volume:24 ; year:2016 ; number:5 ; pages:1975-1983 |
| Links: |
|---|
| DOI / URN: |
10.1109/TVLSI.2015.2478804 |
|---|
| Katalog-ID: |
OLC1975956966 |
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| 520 | |a A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS technology and occupies an area of 0.011 mm 2 . It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies. | ||
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| 650 | 4 | |a Frequency measurement | |
| 650 | 4 | |a Harmonic analysis | |
| 650 | 4 | |a frequency domain measurements | |
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| 650 | 4 | |a 50% duty cycle | |
| 650 | 4 | |a duty-cycle measurements | |
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| 700 | 1 | |a Abraham, Jacob A |4 oth | |
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10.1109/TVLSI.2015.2478804 doi PQ20160719 (DE-627)OLC1975956966 (DE-599)GBVOLC1975956966 (PRQ)i537-f2ebf414107ca1eb0fae4bba8a5964c036c9461fb6f3b10b76fba3bd9d9a9dab0 (KEY)02262649201600000240005019750135ghzdutycyclemeasurementandcorrectiontechniquei DE-627 ger DE-627 rakwb eng 004 620 DNB Raja, Immanuel verfasserin aut A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS technology and occupies an area of 0.011 mm 2 . It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies. Voltage control CMOS integrated circuits Clocks CMOS duty-cycle correction (DCC) correction loop Frequency measurement Harmonic analysis frequency domain measurements rise/fall time measurements 50% duty cycle duty-cycle measurements Bandwidth Banerjee, Gaurab oth Zeidan, Mohamad A oth Abraham, Jacob A oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 24(2016), 5, Seite 1975-1983 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:24 year:2016 number:5 pages:1975-1983 http://dx.doi.org/10.1109/TVLSI.2015.2478804 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7294695 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 24 2016 5 1975-1983 |
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10.1109/TVLSI.2015.2478804 doi PQ20160719 (DE-627)OLC1975956966 (DE-599)GBVOLC1975956966 (PRQ)i537-f2ebf414107ca1eb0fae4bba8a5964c036c9461fb6f3b10b76fba3bd9d9a9dab0 (KEY)02262649201600000240005019750135ghzdutycyclemeasurementandcorrectiontechniquei DE-627 ger DE-627 rakwb eng 004 620 DNB Raja, Immanuel verfasserin aut A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS technology and occupies an area of 0.011 mm 2 . It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies. Voltage control CMOS integrated circuits Clocks CMOS duty-cycle correction (DCC) correction loop Frequency measurement Harmonic analysis frequency domain measurements rise/fall time measurements 50% duty cycle duty-cycle measurements Bandwidth Banerjee, Gaurab oth Zeidan, Mohamad A oth Abraham, Jacob A oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 24(2016), 5, Seite 1975-1983 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:24 year:2016 number:5 pages:1975-1983 http://dx.doi.org/10.1109/TVLSI.2015.2478804 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7294695 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 24 2016 5 1975-1983 |
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10.1109/TVLSI.2015.2478804 doi PQ20160719 (DE-627)OLC1975956966 (DE-599)GBVOLC1975956966 (PRQ)i537-f2ebf414107ca1eb0fae4bba8a5964c036c9461fb6f3b10b76fba3bd9d9a9dab0 (KEY)02262649201600000240005019750135ghzdutycyclemeasurementandcorrectiontechniquei DE-627 ger DE-627 rakwb eng 004 620 DNB Raja, Immanuel verfasserin aut A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS technology and occupies an area of 0.011 mm 2 . It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies. Voltage control CMOS integrated circuits Clocks CMOS duty-cycle correction (DCC) correction loop Frequency measurement Harmonic analysis frequency domain measurements rise/fall time measurements 50% duty cycle duty-cycle measurements Bandwidth Banerjee, Gaurab oth Zeidan, Mohamad A oth Abraham, Jacob A oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 24(2016), 5, Seite 1975-1983 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:24 year:2016 number:5 pages:1975-1983 http://dx.doi.org/10.1109/TVLSI.2015.2478804 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7294695 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 24 2016 5 1975-1983 |
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10.1109/TVLSI.2015.2478804 doi PQ20160719 (DE-627)OLC1975956966 (DE-599)GBVOLC1975956966 (PRQ)i537-f2ebf414107ca1eb0fae4bba8a5964c036c9461fb6f3b10b76fba3bd9d9a9dab0 (KEY)02262649201600000240005019750135ghzdutycyclemeasurementandcorrectiontechniquei DE-627 ger DE-627 rakwb eng 004 620 DNB Raja, Immanuel verfasserin aut A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS technology and occupies an area of 0.011 mm 2 . It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies. Voltage control CMOS integrated circuits Clocks CMOS duty-cycle correction (DCC) correction loop Frequency measurement Harmonic analysis frequency domain measurements rise/fall time measurements 50% duty cycle duty-cycle measurements Bandwidth Banerjee, Gaurab oth Zeidan, Mohamad A oth Abraham, Jacob A oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 24(2016), 5, Seite 1975-1983 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:24 year:2016 number:5 pages:1975-1983 http://dx.doi.org/10.1109/TVLSI.2015.2478804 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7294695 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 24 2016 5 1975-1983 |
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ddc 004 misc Voltage control misc CMOS integrated circuits misc Clocks misc CMOS misc duty-cycle correction (DCC) misc correction loop misc Frequency measurement misc Harmonic analysis misc frequency domain measurements misc rise/fall time measurements misc 50% duty cycle misc duty-cycle measurements misc Bandwidth |
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ddc 004 misc Voltage control misc CMOS integrated circuits misc Clocks misc CMOS misc duty-cycle correction (DCC) misc correction loop misc Frequency measurement misc Harmonic analysis misc frequency domain measurements misc rise/fall time measurements misc 50% duty cycle misc duty-cycle measurements misc Bandwidth |
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ddc 004 misc Voltage control misc CMOS integrated circuits misc Clocks misc CMOS misc duty-cycle correction (DCC) misc correction loop misc Frequency measurement misc Harmonic analysis misc frequency domain measurements misc rise/fall time measurements misc 50% duty cycle misc duty-cycle measurements misc Bandwidth |
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A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS |
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A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS |
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Raja, Immanuel |
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0.1-3.5-ghz duty-cycle measurement and correction technique in 130-nm cmos |
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A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS |
| abstract |
A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS technology and occupies an area of 0.011 mm 2 . It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies. |
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A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS technology and occupies an area of 0.011 mm 2 . It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies. |
| abstract_unstemmed |
A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS technology and occupies an area of 0.011 mm 2 . It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies. |
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A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS |
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http://dx.doi.org/10.1109/TVLSI.2015.2478804 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7294695 |
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Banerjee, Gaurab Zeidan, Mohamad A Abraham, Jacob A |
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