Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System
Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory is an attractive spintronic memory based on this phenomenon, which can store and transfer a series of data along a magnet...
Ausführliche Beschreibung
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| Autor*in: |
Zhang, Yue [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2016 |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on circuits and systems / 1 - New York, NY : Institute of Electrical and Electronics Engineers, 1992, 63(2016), 5, Seite 629-638 |
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| Übergeordnetes Werk: |
volume:63 ; year:2016 ; number:5 ; pages:629-638 |
| Links: |
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| DOI / URN: |
10.1109/TCSI.2016.2529240 |
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OLC1978330855 |
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| 520 | |a Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory is an attractive spintronic memory based on this phenomenon, which can store and transfer a series of data along a magnetic nanowire. However, storage capacity issue is always one of the most serious bottlenecks hindering its application for practical systems. This paper focuses on the potential of racetrack memory towards large capacity. The investigations covering from device level to system level have been carried out. Various alternative mechanisms to improve the capacity of racetrack memory have been proposed and elucidated, e.g., magnetic field assistance, chiral DW motion and voltage-controlled flexible DW pinning. All of them can increase nanowire length, allowing enhanced feasibility of large-capacity racetrack memory. By using SPICE-compatible racetrack memory electrical model and commercial CMOS 28 nm design kit, mixed simulations are performed to validate their functionalities and analyze their performance. System-level evaluations demonstrate the impact of capacity improvement on overall system. Compared with traditional SRAM based cache, racetrack memory based cache shows its advantages in terms of execution time and energy consumption. | ||
| 650 | 4 | |a Chiral domain wall motion | |
| 650 | 4 | |a Magnetic domain walls | |
| 650 | 4 | |a Magnetic domains | |
| 650 | 4 | |a racetrack memory | |
| 650 | 4 | |a Magnetic separation | |
| 650 | 4 | |a Magnetic heads | |
| 650 | 4 | |a Thermal stability | |
| 650 | 4 | |a magnetic field assistance | |
| 650 | 4 | |a L2 cache | |
| 650 | 4 | |a Perpendicular magnetic anisotropy | |
| 700 | 1 | |a Zhang, Chao |4 oth | |
| 700 | 1 | |a Nan, Jiang |4 oth | |
| 700 | 1 | |a Zhang, Zhizhong |4 oth | |
| 700 | 1 | |a Zhang, Xueying |4 oth | |
| 700 | 1 | |a Klein, Jacques-Olivier |4 oth | |
| 700 | 1 | |a Ravelosona, Dafine |4 oth | |
| 700 | 1 | |a Sun, Guangyu |4 oth | |
| 700 | 1 | |a Zhao, Weisheng |4 oth | |
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10.1109/TCSI.2016.2529240 doi PQ20160719 (DE-627)OLC1978330855 (DE-599)GBVOLC1978330855 (PRQ)c719-d63f0eb287a868af5fb2a072e2b0f67e512c421d0cc5b4d60c633a3b851aa3390 (KEY)0213966920160000063000500629perspectivesofracetrackmemoryforlargecapacityonchi DE-627 ger DE-627 rakwb eng 000 620 DNB Zhang, Yue verfasserin aut Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory is an attractive spintronic memory based on this phenomenon, which can store and transfer a series of data along a magnetic nanowire. However, storage capacity issue is always one of the most serious bottlenecks hindering its application for practical systems. This paper focuses on the potential of racetrack memory towards large capacity. The investigations covering from device level to system level have been carried out. Various alternative mechanisms to improve the capacity of racetrack memory have been proposed and elucidated, e.g., magnetic field assistance, chiral DW motion and voltage-controlled flexible DW pinning. All of them can increase nanowire length, allowing enhanced feasibility of large-capacity racetrack memory. By using SPICE-compatible racetrack memory electrical model and commercial CMOS 28 nm design kit, mixed simulations are performed to validate their functionalities and analyze their performance. System-level evaluations demonstrate the impact of capacity improvement on overall system. Compared with traditional SRAM based cache, racetrack memory based cache shows its advantages in terms of execution time and energy consumption. Chiral domain wall motion Magnetic domain walls Magnetic domains racetrack memory Magnetic separation Magnetic heads Thermal stability magnetic field assistance L2 cache Perpendicular magnetic anisotropy Zhang, Chao oth Nan, Jiang oth Zhang, Zhizhong oth Zhang, Xueying oth Klein, Jacques-Olivier oth Ravelosona, Dafine oth Sun, Guangyu oth Zhao, Weisheng oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 5, Seite 629-638 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:63 year:2016 number:5 pages:629-638 http://dx.doi.org/10.1109/TCSI.2016.2529240 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440825 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 63 2016 5 629-638 |
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10.1109/TCSI.2016.2529240 doi PQ20160719 (DE-627)OLC1978330855 (DE-599)GBVOLC1978330855 (PRQ)c719-d63f0eb287a868af5fb2a072e2b0f67e512c421d0cc5b4d60c633a3b851aa3390 (KEY)0213966920160000063000500629perspectivesofracetrackmemoryforlargecapacityonchi DE-627 ger DE-627 rakwb eng 000 620 DNB Zhang, Yue verfasserin aut Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory is an attractive spintronic memory based on this phenomenon, which can store and transfer a series of data along a magnetic nanowire. However, storage capacity issue is always one of the most serious bottlenecks hindering its application for practical systems. This paper focuses on the potential of racetrack memory towards large capacity. The investigations covering from device level to system level have been carried out. Various alternative mechanisms to improve the capacity of racetrack memory have been proposed and elucidated, e.g., magnetic field assistance, chiral DW motion and voltage-controlled flexible DW pinning. All of them can increase nanowire length, allowing enhanced feasibility of large-capacity racetrack memory. By using SPICE-compatible racetrack memory electrical model and commercial CMOS 28 nm design kit, mixed simulations are performed to validate their functionalities and analyze their performance. System-level evaluations demonstrate the impact of capacity improvement on overall system. Compared with traditional SRAM based cache, racetrack memory based cache shows its advantages in terms of execution time and energy consumption. Chiral domain wall motion Magnetic domain walls Magnetic domains racetrack memory Magnetic separation Magnetic heads Thermal stability magnetic field assistance L2 cache Perpendicular magnetic anisotropy Zhang, Chao oth Nan, Jiang oth Zhang, Zhizhong oth Zhang, Xueying oth Klein, Jacques-Olivier oth Ravelosona, Dafine oth Sun, Guangyu oth Zhao, Weisheng oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 5, Seite 629-638 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:63 year:2016 number:5 pages:629-638 http://dx.doi.org/10.1109/TCSI.2016.2529240 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440825 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 63 2016 5 629-638 |
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10.1109/TCSI.2016.2529240 doi PQ20160719 (DE-627)OLC1978330855 (DE-599)GBVOLC1978330855 (PRQ)c719-d63f0eb287a868af5fb2a072e2b0f67e512c421d0cc5b4d60c633a3b851aa3390 (KEY)0213966920160000063000500629perspectivesofracetrackmemoryforlargecapacityonchi DE-627 ger DE-627 rakwb eng 000 620 DNB Zhang, Yue verfasserin aut Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory is an attractive spintronic memory based on this phenomenon, which can store and transfer a series of data along a magnetic nanowire. However, storage capacity issue is always one of the most serious bottlenecks hindering its application for practical systems. This paper focuses on the potential of racetrack memory towards large capacity. The investigations covering from device level to system level have been carried out. Various alternative mechanisms to improve the capacity of racetrack memory have been proposed and elucidated, e.g., magnetic field assistance, chiral DW motion and voltage-controlled flexible DW pinning. All of them can increase nanowire length, allowing enhanced feasibility of large-capacity racetrack memory. By using SPICE-compatible racetrack memory electrical model and commercial CMOS 28 nm design kit, mixed simulations are performed to validate their functionalities and analyze their performance. System-level evaluations demonstrate the impact of capacity improvement on overall system. Compared with traditional SRAM based cache, racetrack memory based cache shows its advantages in terms of execution time and energy consumption. Chiral domain wall motion Magnetic domain walls Magnetic domains racetrack memory Magnetic separation Magnetic heads Thermal stability magnetic field assistance L2 cache Perpendicular magnetic anisotropy Zhang, Chao oth Nan, Jiang oth Zhang, Zhizhong oth Zhang, Xueying oth Klein, Jacques-Olivier oth Ravelosona, Dafine oth Sun, Guangyu oth Zhao, Weisheng oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 5, Seite 629-638 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:63 year:2016 number:5 pages:629-638 http://dx.doi.org/10.1109/TCSI.2016.2529240 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440825 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 63 2016 5 629-638 |
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10.1109/TCSI.2016.2529240 doi PQ20160719 (DE-627)OLC1978330855 (DE-599)GBVOLC1978330855 (PRQ)c719-d63f0eb287a868af5fb2a072e2b0f67e512c421d0cc5b4d60c633a3b851aa3390 (KEY)0213966920160000063000500629perspectivesofracetrackmemoryforlargecapacityonchi DE-627 ger DE-627 rakwb eng 000 620 DNB Zhang, Yue verfasserin aut Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory is an attractive spintronic memory based on this phenomenon, which can store and transfer a series of data along a magnetic nanowire. However, storage capacity issue is always one of the most serious bottlenecks hindering its application for practical systems. This paper focuses on the potential of racetrack memory towards large capacity. The investigations covering from device level to system level have been carried out. Various alternative mechanisms to improve the capacity of racetrack memory have been proposed and elucidated, e.g., magnetic field assistance, chiral DW motion and voltage-controlled flexible DW pinning. All of them can increase nanowire length, allowing enhanced feasibility of large-capacity racetrack memory. By using SPICE-compatible racetrack memory electrical model and commercial CMOS 28 nm design kit, mixed simulations are performed to validate their functionalities and analyze their performance. System-level evaluations demonstrate the impact of capacity improvement on overall system. Compared with traditional SRAM based cache, racetrack memory based cache shows its advantages in terms of execution time and energy consumption. Chiral domain wall motion Magnetic domain walls Magnetic domains racetrack memory Magnetic separation Magnetic heads Thermal stability magnetic field assistance L2 cache Perpendicular magnetic anisotropy Zhang, Chao oth Nan, Jiang oth Zhang, Zhizhong oth Zhang, Xueying oth Klein, Jacques-Olivier oth Ravelosona, Dafine oth Sun, Guangyu oth Zhao, Weisheng oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 5, Seite 629-638 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:63 year:2016 number:5 pages:629-638 http://dx.doi.org/10.1109/TCSI.2016.2529240 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440825 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 63 2016 5 629-638 |
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10.1109/TCSI.2016.2529240 doi PQ20160719 (DE-627)OLC1978330855 (DE-599)GBVOLC1978330855 (PRQ)c719-d63f0eb287a868af5fb2a072e2b0f67e512c421d0cc5b4d60c633a3b851aa3390 (KEY)0213966920160000063000500629perspectivesofracetrackmemoryforlargecapacityonchi DE-627 ger DE-627 rakwb eng 000 620 DNB Zhang, Yue verfasserin aut Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory is an attractive spintronic memory based on this phenomenon, which can store and transfer a series of data along a magnetic nanowire. However, storage capacity issue is always one of the most serious bottlenecks hindering its application for practical systems. This paper focuses on the potential of racetrack memory towards large capacity. The investigations covering from device level to system level have been carried out. Various alternative mechanisms to improve the capacity of racetrack memory have been proposed and elucidated, e.g., magnetic field assistance, chiral DW motion and voltage-controlled flexible DW pinning. All of them can increase nanowire length, allowing enhanced feasibility of large-capacity racetrack memory. By using SPICE-compatible racetrack memory electrical model and commercial CMOS 28 nm design kit, mixed simulations are performed to validate their functionalities and analyze their performance. System-level evaluations demonstrate the impact of capacity improvement on overall system. Compared with traditional SRAM based cache, racetrack memory based cache shows its advantages in terms of execution time and energy consumption. Chiral domain wall motion Magnetic domain walls Magnetic domains racetrack memory Magnetic separation Magnetic heads Thermal stability magnetic field assistance L2 cache Perpendicular magnetic anisotropy Zhang, Chao oth Nan, Jiang oth Zhang, Zhizhong oth Zhang, Xueying oth Klein, Jacques-Olivier oth Ravelosona, Dafine oth Sun, Guangyu oth Zhao, Weisheng oth Enthalten in IEEE transactions on circuits and systems / 1 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 5, Seite 629-638 (DE-627)131043080 (DE-600)1100194-X (DE-576)02804679X 1549-8328 nnns volume:63 year:2016 number:5 pages:629-638 http://dx.doi.org/10.1109/TCSI.2016.2529240 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7440825 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_30 GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 GBV_ILN_2059 AR 63 2016 5 629-638 |
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System-level evaluations demonstrate the impact of capacity improvement on overall system. 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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System |
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Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory is an attractive spintronic memory based on this phenomenon, which can store and transfer a series of data along a magnetic nanowire. However, storage capacity issue is always one of the most serious bottlenecks hindering its application for practical systems. This paper focuses on the potential of racetrack memory towards large capacity. The investigations covering from device level to system level have been carried out. Various alternative mechanisms to improve the capacity of racetrack memory have been proposed and elucidated, e.g., magnetic field assistance, chiral DW motion and voltage-controlled flexible DW pinning. All of them can increase nanowire length, allowing enhanced feasibility of large-capacity racetrack memory. By using SPICE-compatible racetrack memory electrical model and commercial CMOS 28 nm design kit, mixed simulations are performed to validate their functionalities and analyze their performance. System-level evaluations demonstrate the impact of capacity improvement on overall system. Compared with traditional SRAM based cache, racetrack memory based cache shows its advantages in terms of execution time and energy consumption. |
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Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory is an attractive spintronic memory based on this phenomenon, which can store and transfer a series of data along a magnetic nanowire. However, storage capacity issue is always one of the most serious bottlenecks hindering its application for practical systems. This paper focuses on the potential of racetrack memory towards large capacity. The investigations covering from device level to system level have been carried out. Various alternative mechanisms to improve the capacity of racetrack memory have been proposed and elucidated, e.g., magnetic field assistance, chiral DW motion and voltage-controlled flexible DW pinning. All of them can increase nanowire length, allowing enhanced feasibility of large-capacity racetrack memory. By using SPICE-compatible racetrack memory electrical model and commercial CMOS 28 nm design kit, mixed simulations are performed to validate their functionalities and analyze their performance. System-level evaluations demonstrate the impact of capacity improvement on overall system. Compared with traditional SRAM based cache, racetrack memory based cache shows its advantages in terms of execution time and energy consumption. |
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Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory is an attractive spintronic memory based on this phenomenon, which can store and transfer a series of data along a magnetic nanowire. However, storage capacity issue is always one of the most serious bottlenecks hindering its application for practical systems. This paper focuses on the potential of racetrack memory towards large capacity. The investigations covering from device level to system level have been carried out. Various alternative mechanisms to improve the capacity of racetrack memory have been proposed and elucidated, e.g., magnetic field assistance, chiral DW motion and voltage-controlled flexible DW pinning. All of them can increase nanowire length, allowing enhanced feasibility of large-capacity racetrack memory. By using SPICE-compatible racetrack memory electrical model and commercial CMOS 28 nm design kit, mixed simulations are performed to validate their functionalities and analyze their performance. System-level evaluations demonstrate the impact of capacity improvement on overall system. Compared with traditional SRAM based cache, racetrack memory based cache shows its advantages in terms of execution time and energy consumption. |
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