A Digital PLL Using Oversampling Delta-Sigma TDC
A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter <inline-formula> <tex-math notation="LaTeX">(\Delta\Sigma\text{TDC})</tex-math></inline-formula> is presented. This <inline-formula> <tex-math notation="LaTeX">\De...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Wei, Chih-Lu [verfasserIn] |
|---|
| Format: |
Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
2016 |
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| Schlagwörter: |
bang-bang phase-frequency detector |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on circuits and systems / 2 - New York, NY : Institute of Electrical and Electronics Engineers, 1992, 63(2016), 7, Seite 633-637 |
|---|---|
| Übergeordnetes Werk: |
volume:63 ; year:2016 ; number:7 ; pages:633-637 |
| Links: |
|---|
| DOI / URN: |
10.1109/TCSII.2016.2530904 |
|---|
| Katalog-ID: |
OLC1979423385 |
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| 520 | |a A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter <inline-formula> <tex-math notation="LaTeX">(\Delta\Sigma\text{TDC})</tex-math></inline-formula> is presented. This <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm 2 . The measured output frequency is 4 GHz, and the division ratio is 128. The power of the DPLL is 3.51 mW, and its rms jitter is 861 fs. | ||
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| 700 | 1 | |a Liu, Shen-Iuan |4 oth | |
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10.1109/TCSII.2016.2530904 doi PQ20160720 (DE-627)OLC1979423385 (DE-599)GBVOLC1979423385 (PRQ)c726-581b733e13d2bd214bfe4d94e527a9401fc0d91c6605ab3750fed5b7b5acc91f0 (KEY)0213975820160000063000700633digitalpllusingoversamplingdeltasigmatdc DE-627 ger DE-627 rakwb eng 000 620 DNB Wei, Chih-Lu verfasserin aut A Digital PLL Using Oversampling Delta-Sigma TDC 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter <inline-formula> <tex-math notation="LaTeX">(\Delta\Sigma\text{TDC})</tex-math></inline-formula> is presented. This <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm 2 . The measured output frequency is 4 GHz, and the division ratio is 128. The power of the DPLL is 3.51 mW, and its rms jitter is 861 fs. digital phase-locked loop bang-bang phase-frequency detector Varactors time-to-digital converter Finite impulse response filters Clocks Quantization (signal) Phase locked loops delta-sigma Latches Delays Liu, Shen-Iuan oth Enthalten in IEEE transactions on circuits and systems / 2 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 7, Seite 633-637 (DE-627)131044753 (DE-600)1100793-X (DE-576)028047451 1549-7747 nnns volume:63 year:2016 number:7 pages:633-637 http://dx.doi.org/10.1109/TCSII.2016.2530904 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7410012 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 AR 63 2016 7 633-637 |
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10.1109/TCSII.2016.2530904 doi PQ20160720 (DE-627)OLC1979423385 (DE-599)GBVOLC1979423385 (PRQ)c726-581b733e13d2bd214bfe4d94e527a9401fc0d91c6605ab3750fed5b7b5acc91f0 (KEY)0213975820160000063000700633digitalpllusingoversamplingdeltasigmatdc DE-627 ger DE-627 rakwb eng 000 620 DNB Wei, Chih-Lu verfasserin aut A Digital PLL Using Oversampling Delta-Sigma TDC 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter <inline-formula> <tex-math notation="LaTeX">(\Delta\Sigma\text{TDC})</tex-math></inline-formula> is presented. This <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm 2 . The measured output frequency is 4 GHz, and the division ratio is 128. The power of the DPLL is 3.51 mW, and its rms jitter is 861 fs. digital phase-locked loop bang-bang phase-frequency detector Varactors time-to-digital converter Finite impulse response filters Clocks Quantization (signal) Phase locked loops delta-sigma Latches Delays Liu, Shen-Iuan oth Enthalten in IEEE transactions on circuits and systems / 2 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 7, Seite 633-637 (DE-627)131044753 (DE-600)1100793-X (DE-576)028047451 1549-7747 nnns volume:63 year:2016 number:7 pages:633-637 http://dx.doi.org/10.1109/TCSII.2016.2530904 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7410012 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 AR 63 2016 7 633-637 |
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10.1109/TCSII.2016.2530904 doi PQ20160720 (DE-627)OLC1979423385 (DE-599)GBVOLC1979423385 (PRQ)c726-581b733e13d2bd214bfe4d94e527a9401fc0d91c6605ab3750fed5b7b5acc91f0 (KEY)0213975820160000063000700633digitalpllusingoversamplingdeltasigmatdc DE-627 ger DE-627 rakwb eng 000 620 DNB Wei, Chih-Lu verfasserin aut A Digital PLL Using Oversampling Delta-Sigma TDC 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter <inline-formula> <tex-math notation="LaTeX">(\Delta\Sigma\text{TDC})</tex-math></inline-formula> is presented. This <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm 2 . The measured output frequency is 4 GHz, and the division ratio is 128. The power of the DPLL is 3.51 mW, and its rms jitter is 861 fs. digital phase-locked loop bang-bang phase-frequency detector Varactors time-to-digital converter Finite impulse response filters Clocks Quantization (signal) Phase locked loops delta-sigma Latches Delays Liu, Shen-Iuan oth Enthalten in IEEE transactions on circuits and systems / 2 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 7, Seite 633-637 (DE-627)131044753 (DE-600)1100793-X (DE-576)028047451 1549-7747 nnns volume:63 year:2016 number:7 pages:633-637 http://dx.doi.org/10.1109/TCSII.2016.2530904 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7410012 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 AR 63 2016 7 633-637 |
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10.1109/TCSII.2016.2530904 doi PQ20160720 (DE-627)OLC1979423385 (DE-599)GBVOLC1979423385 (PRQ)c726-581b733e13d2bd214bfe4d94e527a9401fc0d91c6605ab3750fed5b7b5acc91f0 (KEY)0213975820160000063000700633digitalpllusingoversamplingdeltasigmatdc DE-627 ger DE-627 rakwb eng 000 620 DNB Wei, Chih-Lu verfasserin aut A Digital PLL Using Oversampling Delta-Sigma TDC 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter <inline-formula> <tex-math notation="LaTeX">(\Delta\Sigma\text{TDC})</tex-math></inline-formula> is presented. This <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm 2 . The measured output frequency is 4 GHz, and the division ratio is 128. The power of the DPLL is 3.51 mW, and its rms jitter is 861 fs. digital phase-locked loop bang-bang phase-frequency detector Varactors time-to-digital converter Finite impulse response filters Clocks Quantization (signal) Phase locked loops delta-sigma Latches Delays Liu, Shen-Iuan oth Enthalten in IEEE transactions on circuits and systems / 2 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 7, Seite 633-637 (DE-627)131044753 (DE-600)1100793-X (DE-576)028047451 1549-7747 nnns volume:63 year:2016 number:7 pages:633-637 http://dx.doi.org/10.1109/TCSII.2016.2530904 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7410012 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 AR 63 2016 7 633-637 |
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10.1109/TCSII.2016.2530904 doi PQ20160720 (DE-627)OLC1979423385 (DE-599)GBVOLC1979423385 (PRQ)c726-581b733e13d2bd214bfe4d94e527a9401fc0d91c6605ab3750fed5b7b5acc91f0 (KEY)0213975820160000063000700633digitalpllusingoversamplingdeltasigmatdc DE-627 ger DE-627 rakwb eng 000 620 DNB Wei, Chih-Lu verfasserin aut A Digital PLL Using Oversampling Delta-Sigma TDC 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter <inline-formula> <tex-math notation="LaTeX">(\Delta\Sigma\text{TDC})</tex-math></inline-formula> is presented. This <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm 2 . The measured output frequency is 4 GHz, and the division ratio is 128. The power of the DPLL is 3.51 mW, and its rms jitter is 861 fs. digital phase-locked loop bang-bang phase-frequency detector Varactors time-to-digital converter Finite impulse response filters Clocks Quantization (signal) Phase locked loops delta-sigma Latches Delays Liu, Shen-Iuan oth Enthalten in IEEE transactions on circuits and systems / 2 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 7, Seite 633-637 (DE-627)131044753 (DE-600)1100793-X (DE-576)028047451 1549-7747 nnns volume:63 year:2016 number:7 pages:633-637 http://dx.doi.org/10.1109/TCSII.2016.2530904 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7410012 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 AR 63 2016 7 633-637 |
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IEEE transactions on circuits and systems / 2 |
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000 - Computer science, knowledge & systems 620 - Engineering |
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IEEE transactions on circuits and systems / 2 |
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A Digital PLL Using Oversampling Delta-Sigma TDC |
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(DE-627)OLC1979423385 (DE-599)GBVOLC1979423385 (PRQ)c726-581b733e13d2bd214bfe4d94e527a9401fc0d91c6605ab3750fed5b7b5acc91f0 (KEY)0213975820160000063000700633digitalpllusingoversamplingdeltasigmatdc |
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A Digital PLL Using Oversampling Delta-Sigma TDC |
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Wei, Chih-Lu |
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IEEE transactions on circuits and systems / 2 |
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IEEE transactions on circuits and systems / 2 |
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eng |
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000 - Computer science, information & general works 600 - Technology |
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2016 |
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Wei, Chih-Lu |
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Wei, Chih-Lu |
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10.1109/TCSII.2016.2530904 |
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000 620 |
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digital pll using oversampling delta-sigma tdc |
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A Digital PLL Using Oversampling Delta-Sigma TDC |
| abstract |
A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter <inline-formula> <tex-math notation="LaTeX">(\Delta\Sigma\text{TDC})</tex-math></inline-formula> is presented. This <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm 2 . The measured output frequency is 4 GHz, and the division ratio is 128. The power of the DPLL is 3.51 mW, and its rms jitter is 861 fs. |
| abstractGer |
A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter <inline-formula> <tex-math notation="LaTeX">(\Delta\Sigma\text{TDC})</tex-math></inline-formula> is presented. This <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm 2 . The measured output frequency is 4 GHz, and the division ratio is 128. The power of the DPLL is 3.51 mW, and its rms jitter is 861 fs. |
| abstract_unstemmed |
A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter <inline-formula> <tex-math notation="LaTeX">(\Delta\Sigma\text{TDC})</tex-math></inline-formula> is presented. This <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed <inline-formula> <tex-math notation="LaTeX">\Delta\Sigma\text{TDC}</tex-math></inline-formula> consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm 2 . The measured output frequency is 4 GHz, and the division ratio is 128. The power of the DPLL is 3.51 mW, and its rms jitter is 861 fs. |
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7 |
| title_short |
A Digital PLL Using Oversampling Delta-Sigma TDC |
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http://dx.doi.org/10.1109/TCSII.2016.2530904 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7410012 |
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Liu, Shen-Iuan |
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