Improving Write Performance for STT-MRAM
Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obsta...
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| Autor*in: |
Bishnoi, Rajendra [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2016 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on magnetics - New York, NY : IEEE, 1965, 52(2016), 8, Seite 1-11 |
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| Übergeordnetes Werk: |
volume:52 ; year:2016 ; number:8 ; pages:1-11 |
| Links: |
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| DOI / URN: |
10.1109/TMAG.2016.2541629 |
|---|
| Katalog-ID: |
OLC1980082081 |
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| 520 | |a Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology. The long write latency of the STT-MRAM is primarily due to two reasons. First, the bit-cell switching is asymmetric, which means that one write direction is significantly slower than the other. Second, the stochastic switching behavior of the bit-cell mandates a significant margin for a target write error rate (WER). In this paper, we propose static and dynamic circuit-level techniques to reduce the overall write latency. The static technique reduces the impact of write asymmetry by increasing the write current only for the slow writes. The dynamic technique additionally targets the write margin by dynamically increasing the write current in a stepwise manner to mitigate the negative impact of the stochastic switching behavior. Experimental results show that our proposed dynamic method can reduce the overall write latency by 71% while maintaining the same WER. Applying this technique to a 512 kB L2-cache of a microprocessor improves its performance by 11% and saves energy by 10% on average. | ||
| 650 | 4 | |a Magnetization | |
| 650 | 4 | |a Transistors | |
| 650 | 4 | |a performance | |
| 650 | 4 | |a Switches | |
| 650 | 4 | |a Computer architecture | |
| 650 | 4 | |a non-volatile memory | |
| 650 | 4 | |a spin-transfer-torque (STT) | |
| 650 | 4 | |a Magnetic memory | |
| 650 | 4 | |a Magnetic tunneling | |
| 650 | 4 | |a Delays | |
| 650 | 4 | |a Microprocessors | |
| 650 | 4 | |a Random access memory | |
| 650 | 4 | |a Computer memory | |
| 700 | 1 | |a Ebrahimi, Mojtaba |4 oth | |
| 700 | 1 | |a Oboril, Fabian |4 oth | |
| 700 | 1 | |a Tahoori, Mehdi B |4 oth | |
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10.1109/TMAG.2016.2541629 doi PQ20160815 (DE-627)OLC1980082081 (DE-599)GBVOLC1980082081 (PRQ)c1243-15c58ccc42e18126c75b82ed8072186d00f0937eeb3e194e8cc0b0086723ad630 (KEY)0061452120160000052000800001improvingwriteperformanceforsttmram DE-627 ger DE-627 rakwb eng 620 DNB 33.75 bkl 33.16 bkl Bishnoi, Rajendra verfasserin aut Improving Write Performance for STT-MRAM 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology. The long write latency of the STT-MRAM is primarily due to two reasons. First, the bit-cell switching is asymmetric, which means that one write direction is significantly slower than the other. Second, the stochastic switching behavior of the bit-cell mandates a significant margin for a target write error rate (WER). In this paper, we propose static and dynamic circuit-level techniques to reduce the overall write latency. The static technique reduces the impact of write asymmetry by increasing the write current only for the slow writes. The dynamic technique additionally targets the write margin by dynamically increasing the write current in a stepwise manner to mitigate the negative impact of the stochastic switching behavior. Experimental results show that our proposed dynamic method can reduce the overall write latency by 71% while maintaining the same WER. Applying this technique to a 512 kB L2-cache of a microprocessor improves its performance by 11% and saves energy by 10% on average. Magnetization Transistors performance Switches Computer architecture non-volatile memory spin-transfer-torque (STT) Magnetic memory Magnetic tunneling Delays Microprocessors Random access memory Computer memory Ebrahimi, Mojtaba oth Oboril, Fabian oth Tahoori, Mehdi B oth Enthalten in IEEE transactions on magnetics New York, NY : IEEE, 1965 52(2016), 8, Seite 1-11 (DE-627)129602078 (DE-600)241508-2 (DE-576)015095789 0018-9464 nnns volume:52 year:2016 number:8 pages:1-11 http://dx.doi.org/10.1109/TMAG.2016.2541629 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7433428 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_170 33.75 AVZ 33.16 AVZ AR 52 2016 8 1-11 |
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10.1109/TMAG.2016.2541629 doi PQ20160815 (DE-627)OLC1980082081 (DE-599)GBVOLC1980082081 (PRQ)c1243-15c58ccc42e18126c75b82ed8072186d00f0937eeb3e194e8cc0b0086723ad630 (KEY)0061452120160000052000800001improvingwriteperformanceforsttmram DE-627 ger DE-627 rakwb eng 620 DNB 33.75 bkl 33.16 bkl Bishnoi, Rajendra verfasserin aut Improving Write Performance for STT-MRAM 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology. The long write latency of the STT-MRAM is primarily due to two reasons. First, the bit-cell switching is asymmetric, which means that one write direction is significantly slower than the other. Second, the stochastic switching behavior of the bit-cell mandates a significant margin for a target write error rate (WER). In this paper, we propose static and dynamic circuit-level techniques to reduce the overall write latency. The static technique reduces the impact of write asymmetry by increasing the write current only for the slow writes. The dynamic technique additionally targets the write margin by dynamically increasing the write current in a stepwise manner to mitigate the negative impact of the stochastic switching behavior. Experimental results show that our proposed dynamic method can reduce the overall write latency by 71% while maintaining the same WER. Applying this technique to a 512 kB L2-cache of a microprocessor improves its performance by 11% and saves energy by 10% on average. Magnetization Transistors performance Switches Computer architecture non-volatile memory spin-transfer-torque (STT) Magnetic memory Magnetic tunneling Delays Microprocessors Random access memory Computer memory Ebrahimi, Mojtaba oth Oboril, Fabian oth Tahoori, Mehdi B oth Enthalten in IEEE transactions on magnetics New York, NY : IEEE, 1965 52(2016), 8, Seite 1-11 (DE-627)129602078 (DE-600)241508-2 (DE-576)015095789 0018-9464 nnns volume:52 year:2016 number:8 pages:1-11 http://dx.doi.org/10.1109/TMAG.2016.2541629 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7433428 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_170 33.75 AVZ 33.16 AVZ AR 52 2016 8 1-11 |
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10.1109/TMAG.2016.2541629 doi PQ20160815 (DE-627)OLC1980082081 (DE-599)GBVOLC1980082081 (PRQ)c1243-15c58ccc42e18126c75b82ed8072186d00f0937eeb3e194e8cc0b0086723ad630 (KEY)0061452120160000052000800001improvingwriteperformanceforsttmram DE-627 ger DE-627 rakwb eng 620 DNB 33.75 bkl 33.16 bkl Bishnoi, Rajendra verfasserin aut Improving Write Performance for STT-MRAM 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology. The long write latency of the STT-MRAM is primarily due to two reasons. First, the bit-cell switching is asymmetric, which means that one write direction is significantly slower than the other. Second, the stochastic switching behavior of the bit-cell mandates a significant margin for a target write error rate (WER). In this paper, we propose static and dynamic circuit-level techniques to reduce the overall write latency. The static technique reduces the impact of write asymmetry by increasing the write current only for the slow writes. The dynamic technique additionally targets the write margin by dynamically increasing the write current in a stepwise manner to mitigate the negative impact of the stochastic switching behavior. Experimental results show that our proposed dynamic method can reduce the overall write latency by 71% while maintaining the same WER. Applying this technique to a 512 kB L2-cache of a microprocessor improves its performance by 11% and saves energy by 10% on average. Magnetization Transistors performance Switches Computer architecture non-volatile memory spin-transfer-torque (STT) Magnetic memory Magnetic tunneling Delays Microprocessors Random access memory Computer memory Ebrahimi, Mojtaba oth Oboril, Fabian oth Tahoori, Mehdi B oth Enthalten in IEEE transactions on magnetics New York, NY : IEEE, 1965 52(2016), 8, Seite 1-11 (DE-627)129602078 (DE-600)241508-2 (DE-576)015095789 0018-9464 nnns volume:52 year:2016 number:8 pages:1-11 http://dx.doi.org/10.1109/TMAG.2016.2541629 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7433428 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_170 33.75 AVZ 33.16 AVZ AR 52 2016 8 1-11 |
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10.1109/TMAG.2016.2541629 doi PQ20160815 (DE-627)OLC1980082081 (DE-599)GBVOLC1980082081 (PRQ)c1243-15c58ccc42e18126c75b82ed8072186d00f0937eeb3e194e8cc0b0086723ad630 (KEY)0061452120160000052000800001improvingwriteperformanceforsttmram DE-627 ger DE-627 rakwb eng 620 DNB 33.75 bkl 33.16 bkl Bishnoi, Rajendra verfasserin aut Improving Write Performance for STT-MRAM 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology. The long write latency of the STT-MRAM is primarily due to two reasons. First, the bit-cell switching is asymmetric, which means that one write direction is significantly slower than the other. Second, the stochastic switching behavior of the bit-cell mandates a significant margin for a target write error rate (WER). In this paper, we propose static and dynamic circuit-level techniques to reduce the overall write latency. The static technique reduces the impact of write asymmetry by increasing the write current only for the slow writes. The dynamic technique additionally targets the write margin by dynamically increasing the write current in a stepwise manner to mitigate the negative impact of the stochastic switching behavior. Experimental results show that our proposed dynamic method can reduce the overall write latency by 71% while maintaining the same WER. Applying this technique to a 512 kB L2-cache of a microprocessor improves its performance by 11% and saves energy by 10% on average. Magnetization Transistors performance Switches Computer architecture non-volatile memory spin-transfer-torque (STT) Magnetic memory Magnetic tunneling Delays Microprocessors Random access memory Computer memory Ebrahimi, Mojtaba oth Oboril, Fabian oth Tahoori, Mehdi B oth Enthalten in IEEE transactions on magnetics New York, NY : IEEE, 1965 52(2016), 8, Seite 1-11 (DE-627)129602078 (DE-600)241508-2 (DE-576)015095789 0018-9464 nnns volume:52 year:2016 number:8 pages:1-11 http://dx.doi.org/10.1109/TMAG.2016.2541629 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7433428 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_170 33.75 AVZ 33.16 AVZ AR 52 2016 8 1-11 |
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10.1109/TMAG.2016.2541629 doi PQ20160815 (DE-627)OLC1980082081 (DE-599)GBVOLC1980082081 (PRQ)c1243-15c58ccc42e18126c75b82ed8072186d00f0937eeb3e194e8cc0b0086723ad630 (KEY)0061452120160000052000800001improvingwriteperformanceforsttmram DE-627 ger DE-627 rakwb eng 620 DNB 33.75 bkl 33.16 bkl Bishnoi, Rajendra verfasserin aut Improving Write Performance for STT-MRAM 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology. The long write latency of the STT-MRAM is primarily due to two reasons. First, the bit-cell switching is asymmetric, which means that one write direction is significantly slower than the other. Second, the stochastic switching behavior of the bit-cell mandates a significant margin for a target write error rate (WER). In this paper, we propose static and dynamic circuit-level techniques to reduce the overall write latency. The static technique reduces the impact of write asymmetry by increasing the write current only for the slow writes. The dynamic technique additionally targets the write margin by dynamically increasing the write current in a stepwise manner to mitigate the negative impact of the stochastic switching behavior. Experimental results show that our proposed dynamic method can reduce the overall write latency by 71% while maintaining the same WER. Applying this technique to a 512 kB L2-cache of a microprocessor improves its performance by 11% and saves energy by 10% on average. Magnetization Transistors performance Switches Computer architecture non-volatile memory spin-transfer-torque (STT) Magnetic memory Magnetic tunneling Delays Microprocessors Random access memory Computer memory Ebrahimi, Mojtaba oth Oboril, Fabian oth Tahoori, Mehdi B oth Enthalten in IEEE transactions on magnetics New York, NY : IEEE, 1965 52(2016), 8, Seite 1-11 (DE-627)129602078 (DE-600)241508-2 (DE-576)015095789 0018-9464 nnns volume:52 year:2016 number:8 pages:1-11 http://dx.doi.org/10.1109/TMAG.2016.2541629 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7433428 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_170 33.75 AVZ 33.16 AVZ AR 52 2016 8 1-11 |
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Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology. The long write latency of the STT-MRAM is primarily due to two reasons. First, the bit-cell switching is asymmetric, which means that one write direction is significantly slower than the other. Second, the stochastic switching behavior of the bit-cell mandates a significant margin for a target write error rate (WER). In this paper, we propose static and dynamic circuit-level techniques to reduce the overall write latency. The static technique reduces the impact of write asymmetry by increasing the write current only for the slow writes. The dynamic technique additionally targets the write margin by dynamically increasing the write current in a stepwise manner to mitigate the negative impact of the stochastic switching behavior. Experimental results show that our proposed dynamic method can reduce the overall write latency by 71% while maintaining the same WER. Applying this technique to a 512 kB L2-cache of a microprocessor improves its performance by 11% and saves energy by 10% on average. |
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Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology. The long write latency of the STT-MRAM is primarily due to two reasons. First, the bit-cell switching is asymmetric, which means that one write direction is significantly slower than the other. Second, the stochastic switching behavior of the bit-cell mandates a significant margin for a target write error rate (WER). In this paper, we propose static and dynamic circuit-level techniques to reduce the overall write latency. The static technique reduces the impact of write asymmetry by increasing the write current only for the slow writes. The dynamic technique additionally targets the write margin by dynamically increasing the write current in a stepwise manner to mitigate the negative impact of the stochastic switching behavior. Experimental results show that our proposed dynamic method can reduce the overall write latency by 71% while maintaining the same WER. Applying this technique to a 512 kB L2-cache of a microprocessor improves its performance by 11% and saves energy by 10% on average. |
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Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology. The long write latency of the STT-MRAM is primarily due to two reasons. First, the bit-cell switching is asymmetric, which means that one write direction is significantly slower than the other. Second, the stochastic switching behavior of the bit-cell mandates a significant margin for a target write error rate (WER). In this paper, we propose static and dynamic circuit-level techniques to reduce the overall write latency. The static technique reduces the impact of write asymmetry by increasing the write current only for the slow writes. The dynamic technique additionally targets the write margin by dynamically increasing the write current in a stepwise manner to mitigate the negative impact of the stochastic switching behavior. Experimental results show that our proposed dynamic method can reduce the overall write latency by 71% while maintaining the same WER. Applying this technique to a 512 kB L2-cache of a microprocessor improves its performance by 11% and saves energy by 10% on average. |
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