A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector
This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and t...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Lee, Dongil [verfasserIn] |
|---|
| Format: |
Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
2016 |
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| Schlagwörter: |
Voltage-controlled oscillators Dividerless injection-locked phase-locked loop (PLL) (ILPLL) voltage-controlled oscillator (VCO) control voltage ripple compensation |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on circuits and systems / 2 - New York, NY : Institute of Electrical and Electronics Engineers, 1992, 63(2016), 8, Seite 733-737 |
|---|---|
| Übergeordnetes Werk: |
volume:63 ; year:2016 ; number:8 ; pages:733-737 |
| Links: |
|---|
| DOI / URN: |
10.1109/TCSII.2016.2530098 |
|---|
| Katalog-ID: |
OLC1980589372 |
|---|
| LEADER | 01000caa a2200265 4500 | ||
|---|---|---|---|
| 001 | OLC1980589372 | ||
| 003 | DE-627 | ||
| 005 | 20210716122302.0 | ||
| 007 | tu | ||
| 008 | 160816s2016 xx ||||| 00| ||eng c | ||
| 024 | 7 | |a 10.1109/TCSII.2016.2530098 |2 doi | |
| 028 | 5 | 2 | |a PQ20160815 |
| 035 | |a (DE-627)OLC1980589372 | ||
| 035 | |a (DE-599)GBVOLC1980589372 | ||
| 035 | |a (PRQ)i587-5a0a93ae9468a8abae5b4bf88a94c96ca70d2618b1bce3848a394f2d15012a40 | ||
| 035 | |a (KEY)021397582016000006300080073321jitterimprovedselfaligneddividerlessinjectionloc | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 082 | 0 | 4 | |a 000 |a 620 |q DNB |
| 100 | 1 | |a Lee, Dongil |e verfasserin |4 aut | |
| 245 | 1 | 2 | |a A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector |
| 264 | 1 | |c 2016 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a ohne Hilfsmittel zu benutzen |b n |2 rdamedia | ||
| 338 | |a Band |b nc |2 rdacarrier | ||
| 520 | |a This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW. | ||
| 650 | 4 | |a Voltage-controlled oscillators | |
| 650 | 4 | |a Phase frequency detector | |
| 650 | 4 | |a Dividerless injection-locked phase-locked loop (PLL) (ILPLL) | |
| 650 | 4 | |a Jitter | |
| 650 | 4 | |a Detectors | |
| 650 | 4 | |a Clocks | |
| 650 | 4 | |a lock detector (LD) | |
| 650 | 4 | |a Phase locked loops | |
| 650 | 4 | |a voltage-controlled oscillator (VCO) control voltage ripple compensation | |
| 650 | 4 | |a Phase noise | |
| 700 | 1 | |a Lee, Taeho |4 oth | |
| 700 | 1 | |a Kim, Young-Ju |4 oth | |
| 700 | 1 | |a Kim, Lee-Sup |4 oth | |
| 773 | 0 | 8 | |i Enthalten in |t IEEE transactions on circuits and systems / 2 |d New York, NY : Institute of Electrical and Electronics Engineers, 1992 |g 63(2016), 8, Seite 733-737 |w (DE-627)131044753 |w (DE-600)1100793-X |w (DE-576)028047451 |x 1549-7747 |7 nnns |
| 773 | 1 | 8 | |g volume:63 |g year:2016 |g number:8 |g pages:733-737 |
| 856 | 4 | 1 | |u http://dx.doi.org/10.1109/TCSII.2016.2530098 |3 Volltext |
| 856 | 4 | 2 | |u http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407361 |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_OLC | ||
| 912 | |a SSG-OLC-TEC | ||
| 912 | |a SSG-OLC-MAT | ||
| 912 | |a GBV_ILN_70 | ||
| 912 | |a GBV_ILN_2002 | ||
| 912 | |a GBV_ILN_2005 | ||
| 951 | |a AR | ||
| 952 | |d 63 |j 2016 |e 8 |h 733-737 | ||
| author_variant |
d l dl |
|---|---|
| matchkey_str |
article:15497747:2016----::2jteipoeslaindiielsijcinokdlwtaccnrlotgr |
| hierarchy_sort_str |
2016 |
| publishDate |
2016 |
| allfields |
10.1109/TCSII.2016.2530098 doi PQ20160815 (DE-627)OLC1980589372 (DE-599)GBVOLC1980589372 (PRQ)i587-5a0a93ae9468a8abae5b4bf88a94c96ca70d2618b1bce3848a394f2d15012a40 (KEY)021397582016000006300080073321jitterimprovedselfaligneddividerlessinjectionloc DE-627 ger DE-627 rakwb eng 000 620 DNB Lee, Dongil verfasserin aut A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW. Voltage-controlled oscillators Phase frequency detector Dividerless injection-locked phase-locked loop (PLL) (ILPLL) Jitter Detectors Clocks lock detector (LD) Phase locked loops voltage-controlled oscillator (VCO) control voltage ripple compensation Phase noise Lee, Taeho oth Kim, Young-Ju oth Kim, Lee-Sup oth Enthalten in IEEE transactions on circuits and systems / 2 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 8, Seite 733-737 (DE-627)131044753 (DE-600)1100793-X (DE-576)028047451 1549-7747 nnns volume:63 year:2016 number:8 pages:733-737 http://dx.doi.org/10.1109/TCSII.2016.2530098 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407361 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 AR 63 2016 8 733-737 |
| spelling |
10.1109/TCSII.2016.2530098 doi PQ20160815 (DE-627)OLC1980589372 (DE-599)GBVOLC1980589372 (PRQ)i587-5a0a93ae9468a8abae5b4bf88a94c96ca70d2618b1bce3848a394f2d15012a40 (KEY)021397582016000006300080073321jitterimprovedselfaligneddividerlessinjectionloc DE-627 ger DE-627 rakwb eng 000 620 DNB Lee, Dongil verfasserin aut A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW. Voltage-controlled oscillators Phase frequency detector Dividerless injection-locked phase-locked loop (PLL) (ILPLL) Jitter Detectors Clocks lock detector (LD) Phase locked loops voltage-controlled oscillator (VCO) control voltage ripple compensation Phase noise Lee, Taeho oth Kim, Young-Ju oth Kim, Lee-Sup oth Enthalten in IEEE transactions on circuits and systems / 2 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 8, Seite 733-737 (DE-627)131044753 (DE-600)1100793-X (DE-576)028047451 1549-7747 nnns volume:63 year:2016 number:8 pages:733-737 http://dx.doi.org/10.1109/TCSII.2016.2530098 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407361 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 AR 63 2016 8 733-737 |
| allfields_unstemmed |
10.1109/TCSII.2016.2530098 doi PQ20160815 (DE-627)OLC1980589372 (DE-599)GBVOLC1980589372 (PRQ)i587-5a0a93ae9468a8abae5b4bf88a94c96ca70d2618b1bce3848a394f2d15012a40 (KEY)021397582016000006300080073321jitterimprovedselfaligneddividerlessinjectionloc DE-627 ger DE-627 rakwb eng 000 620 DNB Lee, Dongil verfasserin aut A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW. Voltage-controlled oscillators Phase frequency detector Dividerless injection-locked phase-locked loop (PLL) (ILPLL) Jitter Detectors Clocks lock detector (LD) Phase locked loops voltage-controlled oscillator (VCO) control voltage ripple compensation Phase noise Lee, Taeho oth Kim, Young-Ju oth Kim, Lee-Sup oth Enthalten in IEEE transactions on circuits and systems / 2 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 8, Seite 733-737 (DE-627)131044753 (DE-600)1100793-X (DE-576)028047451 1549-7747 nnns volume:63 year:2016 number:8 pages:733-737 http://dx.doi.org/10.1109/TCSII.2016.2530098 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407361 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 AR 63 2016 8 733-737 |
| allfieldsGer |
10.1109/TCSII.2016.2530098 doi PQ20160815 (DE-627)OLC1980589372 (DE-599)GBVOLC1980589372 (PRQ)i587-5a0a93ae9468a8abae5b4bf88a94c96ca70d2618b1bce3848a394f2d15012a40 (KEY)021397582016000006300080073321jitterimprovedselfaligneddividerlessinjectionloc DE-627 ger DE-627 rakwb eng 000 620 DNB Lee, Dongil verfasserin aut A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW. Voltage-controlled oscillators Phase frequency detector Dividerless injection-locked phase-locked loop (PLL) (ILPLL) Jitter Detectors Clocks lock detector (LD) Phase locked loops voltage-controlled oscillator (VCO) control voltage ripple compensation Phase noise Lee, Taeho oth Kim, Young-Ju oth Kim, Lee-Sup oth Enthalten in IEEE transactions on circuits and systems / 2 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 8, Seite 733-737 (DE-627)131044753 (DE-600)1100793-X (DE-576)028047451 1549-7747 nnns volume:63 year:2016 number:8 pages:733-737 http://dx.doi.org/10.1109/TCSII.2016.2530098 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407361 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 AR 63 2016 8 733-737 |
| allfieldsSound |
10.1109/TCSII.2016.2530098 doi PQ20160815 (DE-627)OLC1980589372 (DE-599)GBVOLC1980589372 (PRQ)i587-5a0a93ae9468a8abae5b4bf88a94c96ca70d2618b1bce3848a394f2d15012a40 (KEY)021397582016000006300080073321jitterimprovedselfaligneddividerlessinjectionloc DE-627 ger DE-627 rakwb eng 000 620 DNB Lee, Dongil verfasserin aut A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW. Voltage-controlled oscillators Phase frequency detector Dividerless injection-locked phase-locked loop (PLL) (ILPLL) Jitter Detectors Clocks lock detector (LD) Phase locked loops voltage-controlled oscillator (VCO) control voltage ripple compensation Phase noise Lee, Taeho oth Kim, Young-Ju oth Kim, Lee-Sup oth Enthalten in IEEE transactions on circuits and systems / 2 New York, NY : Institute of Electrical and Electronics Engineers, 1992 63(2016), 8, Seite 733-737 (DE-627)131044753 (DE-600)1100793-X (DE-576)028047451 1549-7747 nnns volume:63 year:2016 number:8 pages:733-737 http://dx.doi.org/10.1109/TCSII.2016.2530098 Volltext http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407361 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 AR 63 2016 8 733-737 |
| language |
English |
| source |
Enthalten in IEEE transactions on circuits and systems / 2 63(2016), 8, Seite 733-737 volume:63 year:2016 number:8 pages:733-737 |
| sourceStr |
Enthalten in IEEE transactions on circuits and systems / 2 63(2016), 8, Seite 733-737 volume:63 year:2016 number:8 pages:733-737 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Voltage-controlled oscillators Phase frequency detector Dividerless injection-locked phase-locked loop (PLL) (ILPLL) Jitter Detectors Clocks lock detector (LD) Phase locked loops voltage-controlled oscillator (VCO) control voltage ripple compensation Phase noise |
| dewey-raw |
000 |
| isfreeaccess_bool |
false |
| container_title |
IEEE transactions on circuits and systems / 2 |
| authorswithroles_txt_mv |
Lee, Dongil @@aut@@ Lee, Taeho @@oth@@ Kim, Young-Ju @@oth@@ Kim, Lee-Sup @@oth@@ |
| publishDateDaySort_date |
2016-01-01T00:00:00Z |
| hierarchy_top_id |
131044753 |
| dewey-sort |
0 |
| id |
OLC1980589372 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1980589372</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210716122302.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">160816s2016 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/TCSII.2016.2530098</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20160815</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1980589372</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1980589372</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)i587-5a0a93ae9468a8abae5b4bf88a94c96ca70d2618b1bce3848a394f2d15012a40</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)021397582016000006300080073321jitterimprovedselfaligneddividerlessinjectionloc</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">000</subfield><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Lee, Dongil</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2016</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Voltage-controlled oscillators</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase frequency detector</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Dividerless injection-locked phase-locked loop (PLL) (ILPLL)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Jitter</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Detectors</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Clocks</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">lock detector (LD)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase locked loops</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">voltage-controlled oscillator (VCO) control voltage ripple compensation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase noise</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Lee, Taeho</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kim, Young-Ju</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kim, Lee-Sup</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE transactions on circuits and systems / 2</subfield><subfield code="d">New York, NY : Institute of Electrical and Electronics Engineers, 1992</subfield><subfield code="g">63(2016), 8, Seite 733-737</subfield><subfield code="w">(DE-627)131044753</subfield><subfield code="w">(DE-600)1100793-X</subfield><subfield code="w">(DE-576)028047451</subfield><subfield code="x">1549-7747</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:63</subfield><subfield code="g">year:2016</subfield><subfield code="g">number:8</subfield><subfield code="g">pages:733-737</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/TCSII.2016.2530098</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407361</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-MAT</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2002</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">63</subfield><subfield code="j">2016</subfield><subfield code="e">8</subfield><subfield code="h">733-737</subfield></datafield></record></collection>
|
| author |
Lee, Dongil |
| spellingShingle |
Lee, Dongil ddc 000 misc Voltage-controlled oscillators misc Phase frequency detector misc Dividerless injection-locked phase-locked loop (PLL) (ILPLL) misc Jitter misc Detectors misc Clocks misc lock detector (LD) misc Phase locked loops misc voltage-controlled oscillator (VCO) control voltage ripple compensation misc Phase noise A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector |
| authorStr |
Lee, Dongil |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)131044753 |
| format |
Article |
| dewey-ones |
000 - Computer science, information & general works 620 - Engineering & allied operations |
| delete_txt_mv |
keep |
| author_role |
aut |
| collection |
OLC |
| remote_str |
false |
| illustrated |
Not Illustrated |
| issn |
1549-7747 |
| topic_title |
000 620 DNB A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector Voltage-controlled oscillators Phase frequency detector Dividerless injection-locked phase-locked loop (PLL) (ILPLL) Jitter Detectors Clocks lock detector (LD) Phase locked loops voltage-controlled oscillator (VCO) control voltage ripple compensation Phase noise |
| topic |
ddc 000 misc Voltage-controlled oscillators misc Phase frequency detector misc Dividerless injection-locked phase-locked loop (PLL) (ILPLL) misc Jitter misc Detectors misc Clocks misc lock detector (LD) misc Phase locked loops misc voltage-controlled oscillator (VCO) control voltage ripple compensation misc Phase noise |
| topic_unstemmed |
ddc 000 misc Voltage-controlled oscillators misc Phase frequency detector misc Dividerless injection-locked phase-locked loop (PLL) (ILPLL) misc Jitter misc Detectors misc Clocks misc lock detector (LD) misc Phase locked loops misc voltage-controlled oscillator (VCO) control voltage ripple compensation misc Phase noise |
| topic_browse |
ddc 000 misc Voltage-controlled oscillators misc Phase frequency detector misc Dividerless injection-locked phase-locked loop (PLL) (ILPLL) misc Jitter misc Detectors misc Clocks misc lock detector (LD) misc Phase locked loops misc voltage-controlled oscillator (VCO) control voltage ripple compensation misc Phase noise |
| format_facet |
Aufsätze Gedruckte Aufsätze |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
nc |
| author2_variant |
t l tl y j k yjk l s k lsk |
| hierarchy_parent_title |
IEEE transactions on circuits and systems / 2 |
| hierarchy_parent_id |
131044753 |
| dewey-tens |
000 - Computer science, knowledge & systems 620 - Engineering |
| hierarchy_top_title |
IEEE transactions on circuits and systems / 2 |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)131044753 (DE-600)1100793-X (DE-576)028047451 |
| title |
A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector |
| ctrlnum |
(DE-627)OLC1980589372 (DE-599)GBVOLC1980589372 (PRQ)i587-5a0a93ae9468a8abae5b4bf88a94c96ca70d2618b1bce3848a394f2d15012a40 (KEY)021397582016000006300080073321jitterimprovedselfaligneddividerlessinjectionloc |
| title_full |
A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector |
| author_sort |
Lee, Dongil |
| journal |
IEEE transactions on circuits and systems / 2 |
| journalStr |
IEEE transactions on circuits and systems / 2 |
| lang_code |
eng |
| isOA_bool |
false |
| dewey-hundreds |
000 - Computer science, information & general works 600 - Technology |
| recordtype |
marc |
| publishDateSort |
2016 |
| contenttype_str_mv |
txt |
| container_start_page |
733 |
| author_browse |
Lee, Dongil |
| container_volume |
63 |
| class |
000 620 DNB |
| format_se |
Aufsätze |
| author-letter |
Lee, Dongil |
| doi_str_mv |
10.1109/TCSII.2016.2530098 |
| dewey-full |
000 620 |
| title_sort |
21%-jitter-improved self-aligned dividerless injection-locked pll with a vco control voltage ripple-compensated phase detector |
| title_auth |
A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector |
| abstract |
This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW. |
| abstractGer |
This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW. |
| abstract_unstemmed |
This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW. |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2005 |
| container_issue |
8 |
| title_short |
A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector |
| url |
http://dx.doi.org/10.1109/TCSII.2016.2530098 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407361 |
| remote_bool |
false |
| author2 |
Lee, Taeho Kim, Young-Ju Kim, Lee-Sup |
| author2Str |
Lee, Taeho Kim, Young-Ju Kim, Lee-Sup |
| ppnlink |
131044753 |
| mediatype_str_mv |
n |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| author2_role |
oth oth oth |
| doi_str |
10.1109/TCSII.2016.2530098 |
| up_date |
2024-07-04T03:23:32.046Z |
| _version_ |
1803617212367372288 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1980589372</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210716122302.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">160816s2016 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/TCSII.2016.2530098</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20160815</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1980589372</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1980589372</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)i587-5a0a93ae9468a8abae5b4bf88a94c96ca70d2618b1bce3848a394f2d15012a40</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)021397582016000006300080073321jitterimprovedselfaligneddividerlessinjectionloc</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">000</subfield><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Lee, Dongil</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2016</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Voltage-controlled oscillators</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase frequency detector</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Dividerless injection-locked phase-locked loop (PLL) (ILPLL)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Jitter</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Detectors</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Clocks</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">lock detector (LD)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase locked loops</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">voltage-controlled oscillator (VCO) control voltage ripple compensation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase noise</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Lee, Taeho</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kim, Young-Ju</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kim, Lee-Sup</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE transactions on circuits and systems / 2</subfield><subfield code="d">New York, NY : Institute of Electrical and Electronics Engineers, 1992</subfield><subfield code="g">63(2016), 8, Seite 733-737</subfield><subfield code="w">(DE-627)131044753</subfield><subfield code="w">(DE-600)1100793-X</subfield><subfield code="w">(DE-576)028047451</subfield><subfield code="x">1549-7747</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:63</subfield><subfield code="g">year:2016</subfield><subfield code="g">number:8</subfield><subfield code="g">pages:733-737</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/TCSII.2016.2530098</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7407361</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-MAT</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2002</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">63</subfield><subfield code="j">2016</subfield><subfield code="e">8</subfield><subfield code="h">733-737</subfield></datafield></record></collection>
|
| score |
7.399165 |