A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers
This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppr...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Yu, Lilan [verfasserIn] |
|---|
| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2016 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: IEEE journal of solid state circuits - New York, NY : IEEE, 1966, 51(2016), 10, Seite 2210-2221 |
|---|---|
| Übergeordnetes Werk: |
volume:51 ; year:2016 ; number:10 ; pages:2210-2221 |
| Links: |
|---|
| DOI / URN: |
10.1109/JSSC.2016.2582852 |
|---|
| Katalog-ID: |
OLC1984620606 |
|---|
| LEADER | 01000caa a2200265 4500 | ||
|---|---|---|---|
| 001 | OLC1984620606 | ||
| 003 | DE-627 | ||
| 005 | 20210716143828.0 | ||
| 007 | tu | ||
| 008 | 161202s2016 xx ||||| 00| ||eng c | ||
| 024 | 7 | |a 10.1109/JSSC.2016.2582852 |2 doi | |
| 028 | 5 | 2 | |a PQ20170206 |
| 035 | |a (DE-627)OLC1984620606 | ||
| 035 | |a (DE-599)GBVOLC1984620606 | ||
| 035 | |a (PRQ)c1316-2d939ff4cfaf0a0b6b5eb28f7782d1b5b7a537e2f71fe391cbb6e3aee3e1e7110 | ||
| 035 | |a (KEY)00506842201600000510010022109bit18gss44mwpipelinedadcusinglinearizedopenloopam | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 082 | 0 | 4 | |a 620 |q DNB |
| 100 | 1 | |a Yu, Lilan |e verfasserin |4 aut | |
| 245 | 1 | 2 | |a A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers |
| 264 | 1 | |c 2016 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a ohne Hilfsmittel zu benutzen |b n |2 rdamedia | ||
| 338 | |a Band |b nc |2 rdacarrier | ||
| 520 | |a This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply. | ||
| 650 | 4 | |a Linearization techniques | |
| 650 | 4 | |a double sampling | |
| 650 | 4 | |a Gain | |
| 650 | 4 | |a Power demand | |
| 650 | 4 | |a Linearity | |
| 650 | 4 | |a Calibration | |
| 650 | 4 | |a linearity enhancement | |
| 650 | 4 | |a open-loop amplifier | |
| 650 | 4 | |a Analog-to-digital converter | |
| 650 | 4 | |a pipelined ADC | |
| 650 | 4 | |a Signal resolution | |
| 650 | 4 | |a Bandwidth | |
| 700 | 1 | |a Miyahara, Masaya |4 oth | |
| 700 | 1 | |a Matsuzawa, Akira |4 oth | |
| 773 | 0 | 8 | |i Enthalten in |t IEEE journal of solid state circuits |d New York, NY : IEEE, 1966 |g 51(2016), 10, Seite 2210-2221 |w (DE-627)129594865 |w (DE-600)240580-5 |w (DE-576)01508776X |x 0018-9200 |7 nnns |
| 773 | 1 | 8 | |g volume:51 |g year:2016 |g number:10 |g pages:2210-2221 |
| 856 | 4 | 1 | |u http://dx.doi.org/10.1109/JSSC.2016.2582852 |3 Volltext |
| 856 | 4 | 2 | |u http://ieeexplore.ieee.org/document/7526295 |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_OLC | ||
| 912 | |a SSG-OLC-TEC | ||
| 912 | |a SSG-OLC-PHY | ||
| 912 | |a GBV_ILN_70 | ||
| 912 | |a GBV_ILN_2004 | ||
| 912 | |a GBV_ILN_4313 | ||
| 951 | |a AR | ||
| 952 | |d 51 |j 2016 |e 10 |h 2210-2221 | ||
| author_variant |
l y ly |
|---|---|
| matchkey_str |
article:00189200:2016----::9i1gs4wieieacsnlnaieo |
| hierarchy_sort_str |
2016 |
| publishDate |
2016 |
| allfields |
10.1109/JSSC.2016.2582852 doi PQ20170206 (DE-627)OLC1984620606 (DE-599)GBVOLC1984620606 (PRQ)c1316-2d939ff4cfaf0a0b6b5eb28f7782d1b5b7a537e2f71fe391cbb6e3aee3e1e7110 (KEY)00506842201600000510010022109bit18gss44mwpipelinedadcusinglinearizedopenloopam DE-627 ger DE-627 rakwb eng 620 DNB Yu, Lilan verfasserin aut A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply. Linearization techniques double sampling Gain Power demand Linearity Calibration linearity enhancement open-loop amplifier Analog-to-digital converter pipelined ADC Signal resolution Bandwidth Miyahara, Masaya oth Matsuzawa, Akira oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 10, Seite 2210-2221 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:10 pages:2210-2221 http://dx.doi.org/10.1109/JSSC.2016.2582852 Volltext http://ieeexplore.ieee.org/document/7526295 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 10 2210-2221 |
| spelling |
10.1109/JSSC.2016.2582852 doi PQ20170206 (DE-627)OLC1984620606 (DE-599)GBVOLC1984620606 (PRQ)c1316-2d939ff4cfaf0a0b6b5eb28f7782d1b5b7a537e2f71fe391cbb6e3aee3e1e7110 (KEY)00506842201600000510010022109bit18gss44mwpipelinedadcusinglinearizedopenloopam DE-627 ger DE-627 rakwb eng 620 DNB Yu, Lilan verfasserin aut A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply. Linearization techniques double sampling Gain Power demand Linearity Calibration linearity enhancement open-loop amplifier Analog-to-digital converter pipelined ADC Signal resolution Bandwidth Miyahara, Masaya oth Matsuzawa, Akira oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 10, Seite 2210-2221 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:10 pages:2210-2221 http://dx.doi.org/10.1109/JSSC.2016.2582852 Volltext http://ieeexplore.ieee.org/document/7526295 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 10 2210-2221 |
| allfields_unstemmed |
10.1109/JSSC.2016.2582852 doi PQ20170206 (DE-627)OLC1984620606 (DE-599)GBVOLC1984620606 (PRQ)c1316-2d939ff4cfaf0a0b6b5eb28f7782d1b5b7a537e2f71fe391cbb6e3aee3e1e7110 (KEY)00506842201600000510010022109bit18gss44mwpipelinedadcusinglinearizedopenloopam DE-627 ger DE-627 rakwb eng 620 DNB Yu, Lilan verfasserin aut A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply. Linearization techniques double sampling Gain Power demand Linearity Calibration linearity enhancement open-loop amplifier Analog-to-digital converter pipelined ADC Signal resolution Bandwidth Miyahara, Masaya oth Matsuzawa, Akira oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 10, Seite 2210-2221 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:10 pages:2210-2221 http://dx.doi.org/10.1109/JSSC.2016.2582852 Volltext http://ieeexplore.ieee.org/document/7526295 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 10 2210-2221 |
| allfieldsGer |
10.1109/JSSC.2016.2582852 doi PQ20170206 (DE-627)OLC1984620606 (DE-599)GBVOLC1984620606 (PRQ)c1316-2d939ff4cfaf0a0b6b5eb28f7782d1b5b7a537e2f71fe391cbb6e3aee3e1e7110 (KEY)00506842201600000510010022109bit18gss44mwpipelinedadcusinglinearizedopenloopam DE-627 ger DE-627 rakwb eng 620 DNB Yu, Lilan verfasserin aut A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply. Linearization techniques double sampling Gain Power demand Linearity Calibration linearity enhancement open-loop amplifier Analog-to-digital converter pipelined ADC Signal resolution Bandwidth Miyahara, Masaya oth Matsuzawa, Akira oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 10, Seite 2210-2221 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:10 pages:2210-2221 http://dx.doi.org/10.1109/JSSC.2016.2582852 Volltext http://ieeexplore.ieee.org/document/7526295 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 10 2210-2221 |
| allfieldsSound |
10.1109/JSSC.2016.2582852 doi PQ20170206 (DE-627)OLC1984620606 (DE-599)GBVOLC1984620606 (PRQ)c1316-2d939ff4cfaf0a0b6b5eb28f7782d1b5b7a537e2f71fe391cbb6e3aee3e1e7110 (KEY)00506842201600000510010022109bit18gss44mwpipelinedadcusinglinearizedopenloopam DE-627 ger DE-627 rakwb eng 620 DNB Yu, Lilan verfasserin aut A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers 2016 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply. Linearization techniques double sampling Gain Power demand Linearity Calibration linearity enhancement open-loop amplifier Analog-to-digital converter pipelined ADC Signal resolution Bandwidth Miyahara, Masaya oth Matsuzawa, Akira oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 51(2016), 10, Seite 2210-2221 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:51 year:2016 number:10 pages:2210-2221 http://dx.doi.org/10.1109/JSSC.2016.2582852 Volltext http://ieeexplore.ieee.org/document/7526295 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 51 2016 10 2210-2221 |
| language |
English |
| source |
Enthalten in IEEE journal of solid state circuits 51(2016), 10, Seite 2210-2221 volume:51 year:2016 number:10 pages:2210-2221 |
| sourceStr |
Enthalten in IEEE journal of solid state circuits 51(2016), 10, Seite 2210-2221 volume:51 year:2016 number:10 pages:2210-2221 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Linearization techniques double sampling Gain Power demand Linearity Calibration linearity enhancement open-loop amplifier Analog-to-digital converter pipelined ADC Signal resolution Bandwidth |
| dewey-raw |
620 |
| isfreeaccess_bool |
false |
| container_title |
IEEE journal of solid state circuits |
| authorswithroles_txt_mv |
Yu, Lilan @@aut@@ Miyahara, Masaya @@oth@@ Matsuzawa, Akira @@oth@@ |
| publishDateDaySort_date |
2016-01-01T00:00:00Z |
| hierarchy_top_id |
129594865 |
| dewey-sort |
3620 |
| id |
OLC1984620606 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1984620606</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210716143828.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">161202s2016 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/JSSC.2016.2582852</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20170206</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1984620606</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1984620606</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)c1316-2d939ff4cfaf0a0b6b5eb28f7782d1b5b7a537e2f71fe391cbb6e3aee3e1e7110</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)00506842201600000510010022109bit18gss44mwpipelinedadcusinglinearizedopenloopam</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Yu, Lilan</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2016</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Linearization techniques</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">double sampling</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Gain</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Power demand</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Linearity</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Calibration</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">linearity enhancement</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">open-loop amplifier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Analog-to-digital converter</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">pipelined ADC</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Signal resolution</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Bandwidth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Miyahara, Masaya</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Matsuzawa, Akira</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE journal of solid state circuits</subfield><subfield code="d">New York, NY : IEEE, 1966</subfield><subfield code="g">51(2016), 10, Seite 2210-2221</subfield><subfield code="w">(DE-627)129594865</subfield><subfield code="w">(DE-600)240580-5</subfield><subfield code="w">(DE-576)01508776X</subfield><subfield code="x">0018-9200</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:51</subfield><subfield code="g">year:2016</subfield><subfield code="g">number:10</subfield><subfield code="g">pages:2210-2221</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/JSSC.2016.2582852</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/document/7526295</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-PHY</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">51</subfield><subfield code="j">2016</subfield><subfield code="e">10</subfield><subfield code="h">2210-2221</subfield></datafield></record></collection>
|
| author |
Yu, Lilan |
| spellingShingle |
Yu, Lilan ddc 620 misc Linearization techniques misc double sampling misc Gain misc Power demand misc Linearity misc Calibration misc linearity enhancement misc open-loop amplifier misc Analog-to-digital converter misc pipelined ADC misc Signal resolution misc Bandwidth A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers |
| authorStr |
Yu, Lilan |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)129594865 |
| format |
Article |
| dewey-ones |
620 - Engineering & allied operations |
| delete_txt_mv |
keep |
| author_role |
aut |
| collection |
OLC |
| remote_str |
false |
| illustrated |
Not Illustrated |
| issn |
0018-9200 |
| topic_title |
620 DNB A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers Linearization techniques double sampling Gain Power demand Linearity Calibration linearity enhancement open-loop amplifier Analog-to-digital converter pipelined ADC Signal resolution Bandwidth |
| topic |
ddc 620 misc Linearization techniques misc double sampling misc Gain misc Power demand misc Linearity misc Calibration misc linearity enhancement misc open-loop amplifier misc Analog-to-digital converter misc pipelined ADC misc Signal resolution misc Bandwidth |
| topic_unstemmed |
ddc 620 misc Linearization techniques misc double sampling misc Gain misc Power demand misc Linearity misc Calibration misc linearity enhancement misc open-loop amplifier misc Analog-to-digital converter misc pipelined ADC misc Signal resolution misc Bandwidth |
| topic_browse |
ddc 620 misc Linearization techniques misc double sampling misc Gain misc Power demand misc Linearity misc Calibration misc linearity enhancement misc open-loop amplifier misc Analog-to-digital converter misc pipelined ADC misc Signal resolution misc Bandwidth |
| format_facet |
Aufsätze Gedruckte Aufsätze |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
nc |
| author2_variant |
m m mm a m am |
| hierarchy_parent_title |
IEEE journal of solid state circuits |
| hierarchy_parent_id |
129594865 |
| dewey-tens |
620 - Engineering |
| hierarchy_top_title |
IEEE journal of solid state circuits |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X |
| title |
A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers |
| ctrlnum |
(DE-627)OLC1984620606 (DE-599)GBVOLC1984620606 (PRQ)c1316-2d939ff4cfaf0a0b6b5eb28f7782d1b5b7a537e2f71fe391cbb6e3aee3e1e7110 (KEY)00506842201600000510010022109bit18gss44mwpipelinedadcusinglinearizedopenloopam |
| title_full |
A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers |
| author_sort |
Yu, Lilan |
| journal |
IEEE journal of solid state circuits |
| journalStr |
IEEE journal of solid state circuits |
| lang_code |
eng |
| isOA_bool |
false |
| dewey-hundreds |
600 - Technology |
| recordtype |
marc |
| publishDateSort |
2016 |
| contenttype_str_mv |
txt |
| container_start_page |
2210 |
| author_browse |
Yu, Lilan |
| container_volume |
51 |
| class |
620 DNB |
| format_se |
Aufsätze |
| author-letter |
Yu, Lilan |
| doi_str_mv |
10.1109/JSSC.2016.2582852 |
| dewey-full |
620 |
| title_sort |
9-bit 1.8 gs/s 44 mw pipelined adc using linearized open-loop amplifiers |
| title_auth |
A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers |
| abstract |
This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply. |
| abstractGer |
This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply. |
| abstract_unstemmed |
This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply. |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 |
| container_issue |
10 |
| title_short |
A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers |
| url |
http://dx.doi.org/10.1109/JSSC.2016.2582852 http://ieeexplore.ieee.org/document/7526295 |
| remote_bool |
false |
| author2 |
Miyahara, Masaya Matsuzawa, Akira |
| author2Str |
Miyahara, Masaya Matsuzawa, Akira |
| ppnlink |
129594865 |
| mediatype_str_mv |
n |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| author2_role |
oth oth |
| doi_str |
10.1109/JSSC.2016.2582852 |
| up_date |
2024-07-04T01:02:10.777Z |
| _version_ |
1803608319096520704 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1984620606</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210716143828.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">161202s2016 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/JSSC.2016.2582852</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20170206</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1984620606</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1984620606</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)c1316-2d939ff4cfaf0a0b6b5eb28f7782d1b5b7a537e2f71fe391cbb6e3aee3e1e7110</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)00506842201600000510010022109bit18gss44mwpipelinedadcusinglinearizedopenloopam</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Yu, Lilan</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2016</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This paper presents a 9-bit 1.8 GS/s pipelined analog-to-digital converter (ADC) using open-loop amplifiers. In this ADC, open-loop amplifiers are used as residue amplifiers to increase the sampling rate of the ADC with relatively low power consumption. A linearization technique is proposed to suppress the SNDR decrease caused by the nonlinearity of open-loop amplifiers. The attenuation in the capacitor digital-to-analog converter (CDAC) is utilized to calibrate the gain error of the pipelined stages. In addition, top-plate sampling is proposed to further enhance the power efficiency of the residue amplifiers. With these techniques, the ADC achieves a high sampling rate and high power efficiency. A prototype of the ADC is fabricated in 65 nm CMOS technology. An SNDR of 47 dB and a FoM of 134 fJ/conversion-step is achieved at a sampling rate of 1.8 GS/s with 900 MHz input, while consuming 44 mW from a 1.2 V supply.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Linearization techniques</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">double sampling</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Gain</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Power demand</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Linearity</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Calibration</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">linearity enhancement</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">open-loop amplifier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Analog-to-digital converter</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">pipelined ADC</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Signal resolution</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Bandwidth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Miyahara, Masaya</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Matsuzawa, Akira</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE journal of solid state circuits</subfield><subfield code="d">New York, NY : IEEE, 1966</subfield><subfield code="g">51(2016), 10, Seite 2210-2221</subfield><subfield code="w">(DE-627)129594865</subfield><subfield code="w">(DE-600)240580-5</subfield><subfield code="w">(DE-576)01508776X</subfield><subfield code="x">0018-9200</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:51</subfield><subfield code="g">year:2016</subfield><subfield code="g">number:10</subfield><subfield code="g">pages:2210-2221</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/JSSC.2016.2582852</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/document/7526295</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-PHY</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">51</subfield><subfield code="j">2016</subfield><subfield code="e">10</subfield><subfield code="h">2210-2221</subfield></datafield></record></collection>
|
| score |
7.40189 |