Modeling and Pareto Optimization of On-Chip Switched Capacitor
The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter o...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Toke M Andersen [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2017 |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on power electronics - New York, NY : IEEE, 1986, 32(2017), 1, Seite 363 |
|---|---|
| Übergeordnetes Werk: |
volume:32 ; year:2017 ; number:1 ; pages:363 |
| Katalog-ID: |
OLC198886528X |
|---|
| LEADER | 01000caa a2200265 4500 | ||
|---|---|---|---|
| 001 | OLC198886528X | ||
| 003 | DE-627 | ||
| 005 | 20220220214917.0 | ||
| 007 | tu | ||
| 008 | 170207s2017 xx ||||| 00| ||eng c | ||
| 028 | 5 | 2 | |a PQ20170501 |
| 035 | |a (DE-627)OLC198886528X | ||
| 035 | |a (DE-599)GBVOLC198886528X | ||
| 035 | |a (PRQ)proquest_abstracts_18245324310 | ||
| 035 | |a (KEY)0151676020170000032000100363modelingandparetooptimizationofonchipswitchedcapac | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 082 | 0 | 4 | |a 620 |q DNB |
| 084 | |a ZG 1100: |q AVZ |2 rvk | ||
| 084 | |a 53.35 |2 bkl | ||
| 100 | 0 | |a Toke M Andersen |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a Modeling and Pareto Optimization of On-Chip Switched Capacitor |
| 264 | 1 | |c 2017 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a ohne Hilfsmittel zu benutzen |b n |2 rdamedia | ||
| 338 | |a Band |b nc |2 rdacarrier | ||
| 520 | |a The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage. | ||
| 650 | 4 | |a Pareto optimum | |
| 650 | 4 | |a Mathematical models | |
| 650 | 4 | |a Electrical equipment | |
| 650 | 4 | |a Electrical currents | |
| 650 | 4 | |a CMOS | |
| 700 | 0 | |a Florian Krismer |4 oth | |
| 700 | 0 | |a Johann W Kolar |4 oth | |
| 700 | 0 | |a Thomas Toifl |4 oth | |
| 700 | 0 | |a Christian Menolfi |4 oth | |
| 700 | 0 | |a Lukas Kull |4 oth | |
| 700 | 0 | |a Thomas Morf |4 oth | |
| 700 | 0 | |a Marcel Kossel |4 oth | |
| 700 | 0 | |a Matthias Brändli |4 oth | |
| 700 | 0 | |a Pier Andrea Francese |4 oth | |
| 773 | 0 | 8 | |i Enthalten in |t IEEE transactions on power electronics |d New York, NY : IEEE, 1986 |g 32(2017), 1, Seite 363 |w (DE-627)129383333 |w (DE-600)165902-9 |w (DE-576)014769980 |x 0885-8993 |7 nnns |
| 773 | 1 | 8 | |g volume:32 |g year:2017 |g number:1 |g pages:363 |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_OLC | ||
| 912 | |a SSG-OLC-TEC | ||
| 912 | |a GBV_ILN_70 | ||
| 912 | |a GBV_ILN_2061 | ||
| 936 | r | v | |a ZG 1100: |
| 936 | b | k | |a 53.35 |q AVZ |
| 951 | |a AR | ||
| 952 | |d 32 |j 2017 |e 1 |h 363 | ||
| author_variant |
t m a tma |
|---|---|
| matchkey_str |
article:08858993:2017----::oeignprtotmztooocis |
| hierarchy_sort_str |
2017 |
| bklnumber |
53.35 |
| publishDate |
2017 |
| allfields |
PQ20170501 (DE-627)OLC198886528X (DE-599)GBVOLC198886528X (PRQ)proquest_abstracts_18245324310 (KEY)0151676020170000032000100363modelingandparetooptimizationofonchipswitchedcapac DE-627 ger DE-627 rakwb eng 620 DNB ZG 1100: AVZ rvk 53.35 bkl Toke M Andersen verfasserin aut Modeling and Pareto Optimization of On-Chip Switched Capacitor 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage. Pareto optimum Mathematical models Electrical equipment Electrical currents CMOS Florian Krismer oth Johann W Kolar oth Thomas Toifl oth Christian Menolfi oth Lukas Kull oth Thomas Morf oth Marcel Kossel oth Matthias Brändli oth Pier Andrea Francese oth Enthalten in IEEE transactions on power electronics New York, NY : IEEE, 1986 32(2017), 1, Seite 363 (DE-627)129383333 (DE-600)165902-9 (DE-576)014769980 0885-8993 nnns volume:32 year:2017 number:1 pages:363 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2061 ZG 1100: 53.35 AVZ AR 32 2017 1 363 |
| spelling |
PQ20170501 (DE-627)OLC198886528X (DE-599)GBVOLC198886528X (PRQ)proquest_abstracts_18245324310 (KEY)0151676020170000032000100363modelingandparetooptimizationofonchipswitchedcapac DE-627 ger DE-627 rakwb eng 620 DNB ZG 1100: AVZ rvk 53.35 bkl Toke M Andersen verfasserin aut Modeling and Pareto Optimization of On-Chip Switched Capacitor 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage. Pareto optimum Mathematical models Electrical equipment Electrical currents CMOS Florian Krismer oth Johann W Kolar oth Thomas Toifl oth Christian Menolfi oth Lukas Kull oth Thomas Morf oth Marcel Kossel oth Matthias Brändli oth Pier Andrea Francese oth Enthalten in IEEE transactions on power electronics New York, NY : IEEE, 1986 32(2017), 1, Seite 363 (DE-627)129383333 (DE-600)165902-9 (DE-576)014769980 0885-8993 nnns volume:32 year:2017 number:1 pages:363 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2061 ZG 1100: 53.35 AVZ AR 32 2017 1 363 |
| allfields_unstemmed |
PQ20170501 (DE-627)OLC198886528X (DE-599)GBVOLC198886528X (PRQ)proquest_abstracts_18245324310 (KEY)0151676020170000032000100363modelingandparetooptimizationofonchipswitchedcapac DE-627 ger DE-627 rakwb eng 620 DNB ZG 1100: AVZ rvk 53.35 bkl Toke M Andersen verfasserin aut Modeling and Pareto Optimization of On-Chip Switched Capacitor 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage. Pareto optimum Mathematical models Electrical equipment Electrical currents CMOS Florian Krismer oth Johann W Kolar oth Thomas Toifl oth Christian Menolfi oth Lukas Kull oth Thomas Morf oth Marcel Kossel oth Matthias Brändli oth Pier Andrea Francese oth Enthalten in IEEE transactions on power electronics New York, NY : IEEE, 1986 32(2017), 1, Seite 363 (DE-627)129383333 (DE-600)165902-9 (DE-576)014769980 0885-8993 nnns volume:32 year:2017 number:1 pages:363 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2061 ZG 1100: 53.35 AVZ AR 32 2017 1 363 |
| allfieldsGer |
PQ20170501 (DE-627)OLC198886528X (DE-599)GBVOLC198886528X (PRQ)proquest_abstracts_18245324310 (KEY)0151676020170000032000100363modelingandparetooptimizationofonchipswitchedcapac DE-627 ger DE-627 rakwb eng 620 DNB ZG 1100: AVZ rvk 53.35 bkl Toke M Andersen verfasserin aut Modeling and Pareto Optimization of On-Chip Switched Capacitor 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage. Pareto optimum Mathematical models Electrical equipment Electrical currents CMOS Florian Krismer oth Johann W Kolar oth Thomas Toifl oth Christian Menolfi oth Lukas Kull oth Thomas Morf oth Marcel Kossel oth Matthias Brändli oth Pier Andrea Francese oth Enthalten in IEEE transactions on power electronics New York, NY : IEEE, 1986 32(2017), 1, Seite 363 (DE-627)129383333 (DE-600)165902-9 (DE-576)014769980 0885-8993 nnns volume:32 year:2017 number:1 pages:363 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2061 ZG 1100: 53.35 AVZ AR 32 2017 1 363 |
| allfieldsSound |
PQ20170501 (DE-627)OLC198886528X (DE-599)GBVOLC198886528X (PRQ)proquest_abstracts_18245324310 (KEY)0151676020170000032000100363modelingandparetooptimizationofonchipswitchedcapac DE-627 ger DE-627 rakwb eng 620 DNB ZG 1100: AVZ rvk 53.35 bkl Toke M Andersen verfasserin aut Modeling and Pareto Optimization of On-Chip Switched Capacitor 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage. Pareto optimum Mathematical models Electrical equipment Electrical currents CMOS Florian Krismer oth Johann W Kolar oth Thomas Toifl oth Christian Menolfi oth Lukas Kull oth Thomas Morf oth Marcel Kossel oth Matthias Brändli oth Pier Andrea Francese oth Enthalten in IEEE transactions on power electronics New York, NY : IEEE, 1986 32(2017), 1, Seite 363 (DE-627)129383333 (DE-600)165902-9 (DE-576)014769980 0885-8993 nnns volume:32 year:2017 number:1 pages:363 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2061 ZG 1100: 53.35 AVZ AR 32 2017 1 363 |
| language |
English |
| source |
Enthalten in IEEE transactions on power electronics 32(2017), 1, Seite 363 volume:32 year:2017 number:1 pages:363 |
| sourceStr |
Enthalten in IEEE transactions on power electronics 32(2017), 1, Seite 363 volume:32 year:2017 number:1 pages:363 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Pareto optimum Mathematical models Electrical equipment Electrical currents CMOS |
| dewey-raw |
620 |
| isfreeaccess_bool |
false |
| container_title |
IEEE transactions on power electronics |
| authorswithroles_txt_mv |
Toke M Andersen @@aut@@ Florian Krismer @@oth@@ Johann W Kolar @@oth@@ Thomas Toifl @@oth@@ Christian Menolfi @@oth@@ Lukas Kull @@oth@@ Thomas Morf @@oth@@ Marcel Kossel @@oth@@ Matthias Brändli @@oth@@ Pier Andrea Francese @@oth@@ |
| publishDateDaySort_date |
2017-01-01T00:00:00Z |
| hierarchy_top_id |
129383333 |
| dewey-sort |
3620 |
| id |
OLC198886528X |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC198886528X</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20220220214917.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">170207s2017 xx ||||| 00| ||eng c</controlfield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20170501</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC198886528X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC198886528X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)proquest_abstracts_18245324310</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)0151676020170000032000100363modelingandparetooptimizationofonchipswitchedcapac</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZG 1100:</subfield><subfield code="q">AVZ</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.35</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="0" ind2=" "><subfield code="a">Toke M Andersen</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Modeling and Pareto Optimization of On-Chip Switched Capacitor</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2017</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Pareto optimum</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Mathematical models</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical equipment</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical currents</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">CMOS</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Florian Krismer</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Johann W Kolar</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Thomas Toifl</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Christian Menolfi</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Lukas Kull</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Thomas Morf</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Marcel Kossel</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Matthias Brändli</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Pier Andrea Francese</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE transactions on power electronics</subfield><subfield code="d">New York, NY : IEEE, 1986</subfield><subfield code="g">32(2017), 1, Seite 363</subfield><subfield code="w">(DE-627)129383333</subfield><subfield code="w">(DE-600)165902-9</subfield><subfield code="w">(DE-576)014769980</subfield><subfield code="x">0885-8993</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:32</subfield><subfield code="g">year:2017</subfield><subfield code="g">number:1</subfield><subfield code="g">pages:363</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2061</subfield></datafield><datafield tag="936" ind1="r" ind2="v"><subfield code="a">ZG 1100:</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">53.35</subfield><subfield code="q">AVZ</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">32</subfield><subfield code="j">2017</subfield><subfield code="e">1</subfield><subfield code="h">363</subfield></datafield></record></collection>
|
| author |
Toke M Andersen |
| spellingShingle |
Toke M Andersen ddc 620 rvk ZG 1100: bkl 53.35 misc Pareto optimum misc Mathematical models misc Electrical equipment misc Electrical currents misc CMOS Modeling and Pareto Optimization of On-Chip Switched Capacitor |
| authorStr |
Toke M Andersen |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)129383333 |
| format |
Article |
| dewey-ones |
620 - Engineering & allied operations |
| delete_txt_mv |
keep |
| author_role |
aut |
| collection |
OLC |
| remote_str |
false |
| illustrated |
Not Illustrated |
| issn |
0885-8993 |
| topic_title |
620 DNB ZG 1100: AVZ rvk 53.35 bkl Modeling and Pareto Optimization of On-Chip Switched Capacitor Pareto optimum Mathematical models Electrical equipment Electrical currents CMOS |
| topic |
ddc 620 rvk ZG 1100: bkl 53.35 misc Pareto optimum misc Mathematical models misc Electrical equipment misc Electrical currents misc CMOS |
| topic_unstemmed |
ddc 620 rvk ZG 1100: bkl 53.35 misc Pareto optimum misc Mathematical models misc Electrical equipment misc Electrical currents misc CMOS |
| topic_browse |
ddc 620 rvk ZG 1100: bkl 53.35 misc Pareto optimum misc Mathematical models misc Electrical equipment misc Electrical currents misc CMOS |
| format_facet |
Aufsätze Gedruckte Aufsätze |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
nc |
| author2_variant |
f k fk j w k jwk t t tt c m cm l k lk t m tm m k mk m b mb p a f paf |
| hierarchy_parent_title |
IEEE transactions on power electronics |
| hierarchy_parent_id |
129383333 |
| dewey-tens |
620 - Engineering |
| hierarchy_top_title |
IEEE transactions on power electronics |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)129383333 (DE-600)165902-9 (DE-576)014769980 |
| title |
Modeling and Pareto Optimization of On-Chip Switched Capacitor |
| ctrlnum |
(DE-627)OLC198886528X (DE-599)GBVOLC198886528X (PRQ)proquest_abstracts_18245324310 (KEY)0151676020170000032000100363modelingandparetooptimizationofonchipswitchedcapac |
| title_full |
Modeling and Pareto Optimization of On-Chip Switched Capacitor |
| author_sort |
Toke M Andersen |
| journal |
IEEE transactions on power electronics |
| journalStr |
IEEE transactions on power electronics |
| lang_code |
eng |
| isOA_bool |
false |
| dewey-hundreds |
600 - Technology |
| recordtype |
marc |
| publishDateSort |
2017 |
| contenttype_str_mv |
txt |
| container_start_page |
363 |
| author_browse |
Toke M Andersen |
| container_volume |
32 |
| class |
620 DNB ZG 1100: AVZ rvk 53.35 bkl |
| format_se |
Aufsätze |
| author-letter |
Toke M Andersen |
| dewey-full |
620 |
| title_sort |
modeling and pareto optimization of on-chip switched capacitor |
| title_auth |
Modeling and Pareto Optimization of On-Chip Switched Capacitor |
| abstract |
The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage. |
| abstractGer |
The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage. |
| abstract_unstemmed |
The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage. |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2061 |
| container_issue |
1 |
| title_short |
Modeling and Pareto Optimization of On-Chip Switched Capacitor |
| remote_bool |
false |
| author2 |
Florian Krismer Johann W Kolar Thomas Toifl Christian Menolfi Lukas Kull Thomas Morf Marcel Kossel Matthias Brändli Pier Andrea Francese |
| author2Str |
Florian Krismer Johann W Kolar Thomas Toifl Christian Menolfi Lukas Kull Thomas Morf Marcel Kossel Matthias Brändli Pier Andrea Francese |
| ppnlink |
129383333 |
| mediatype_str_mv |
n |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| author2_role |
oth oth oth oth oth oth oth oth oth |
| up_date |
2024-07-03T19:30:07.422Z |
| _version_ |
1803587427943579648 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC198886528X</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20220220214917.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">170207s2017 xx ||||| 00| ||eng c</controlfield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20170501</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC198886528X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC198886528X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)proquest_abstracts_18245324310</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)0151676020170000032000100363modelingandparetooptimizationofonchipswitchedcapac</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZG 1100:</subfield><subfield code="q">AVZ</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.35</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="0" ind2=" "><subfield code="a">Toke M Andersen</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Modeling and Pareto Optimization of On-Chip Switched Capacitor</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2017</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Pareto optimum</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Mathematical models</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical equipment</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical currents</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">CMOS</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Florian Krismer</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Johann W Kolar</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Thomas Toifl</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Christian Menolfi</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Lukas Kull</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Thomas Morf</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Marcel Kossel</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Matthias Brändli</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="0" ind2=" "><subfield code="a">Pier Andrea Francese</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE transactions on power electronics</subfield><subfield code="d">New York, NY : IEEE, 1986</subfield><subfield code="g">32(2017), 1, Seite 363</subfield><subfield code="w">(DE-627)129383333</subfield><subfield code="w">(DE-600)165902-9</subfield><subfield code="w">(DE-576)014769980</subfield><subfield code="x">0885-8993</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:32</subfield><subfield code="g">year:2017</subfield><subfield code="g">number:1</subfield><subfield code="g">pages:363</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2061</subfield></datafield><datafield tag="936" ind1="r" ind2="v"><subfield code="a">ZG 1100:</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">53.35</subfield><subfield code="q">AVZ</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">32</subfield><subfield code="j">2017</subfield><subfield code="e">1</subfield><subfield code="h">363</subfield></datafield></record></collection>
|
| score |
7.4022045 |