High-Breakdown, High- f} Multiport Stacked-Transistor Topologies for the -Band Power Amplifiers
Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the <inline-formula> <tex-math notation="LaTeX">{W} </tex-mat...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Datta, Kunal [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2017 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: IEEE journal of solid state circuits - New York, NY : IEEE, 1966, 52(2017), 5, Seite 1305-1319 |
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| Übergeordnetes Werk: |
volume:52 ; year:2017 ; number:5 ; pages:1305-1319 |
| Links: |
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| DOI / URN: |
10.1109/JSSC.2016.2641464 |
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| Katalog-ID: |
OLC1992323879 |
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| 520 | |a Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band frequencies (75-110 GHz), is presented in this paper. To mitigate the performance degradation in output power and PAE arising from such causes, high-breakdown voltage, high-<inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> multiport stacked-transistor topologies are proposed for realizing power amplifiers with high output power and high efficiency at 75-110 GHz. A 90-nm silicon germanium (SiGe) BiCMOS process is used to propose active structures comprising of two and three stacked transistors with integrated layout parasitics that achieve <inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> and breakdown voltage of 295 GHz and 8 V and 260 GHz and 11 V, respectively. Functionality of such multiport transistor topologies is demonstrated in proof-of-concept implementations, including a five-stage two-stacked switching power amplifier (PA) that achieves peak output power and PAE of 22 dBm and 19% at 85 GHz, and a six-stage three-stacked PA that achieves peak output power and PAE of 23.3 dBm and 17% at 83 GHz, respectively. For comparison with conventional switching PA designs using native transistor footprints, a five-stage <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band nonstacked Class-E amplifiers is also fabricated in the same 90-nm SiGe BiCMOS process with output power and PAE of 19.5 dBm and 16% at 88 GHz. The superior performance of output power and PAE in designs using the multiport transistor topologies highlights the benefit of the proposed approach. | ||
| 650 | 4 | |a Heterojunction bipolar transistors | |
| 650 | 4 | |a Class-E | |
| 650 | 4 | |a transmitter | |
| 650 | 4 | |a Silicon | |
| 650 | 4 | |a power amplifier (PA) | |
| 650 | 4 | |a Gain | |
| 650 | 4 | |a Silicon germanium | |
| 650 | 4 | |a Topology | |
| 650 | 4 | |a millimeter wave (mm-wave) | |
| 650 | 4 | |a silicon germanium (SiGe) | |
| 650 | 4 | |a Power generation | |
| 650 | 4 | |a HBT | |
| 700 | 1 | |a Hashemi, Hossein |4 oth | |
| 773 | 0 | 8 | |i Enthalten in |t IEEE journal of solid state circuits |d New York, NY : IEEE, 1966 |g 52(2017), 5, Seite 1305-1319 |w (DE-627)129594865 |w (DE-600)240580-5 |w (DE-576)01508776X |x 0018-9200 |7 nnns |
| 773 | 1 | 8 | |g volume:52 |g year:2017 |g number:5 |g pages:1305-1319 |
| 856 | 4 | 1 | |u http://dx.doi.org/10.1109/JSSC.2016.2641464 |3 Volltext |
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10.1109/JSSC.2016.2641464 doi PQ20170501 (DE-627)OLC1992323879 (DE-599)GBVOLC1992323879 (PRQ)ieee_primary_0b00006485b568d00 (KEY)0050684220170000052000501305highbreakdownhighfmultiportstackedtransistortopolo DE-627 ger DE-627 rakwb eng 620 DE-600 Datta, Kunal verfasserin aut High-Breakdown, High- f} Multiport Stacked-Transistor Topologies for the -Band Power Amplifiers 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band frequencies (75-110 GHz), is presented in this paper. To mitigate the performance degradation in output power and PAE arising from such causes, high-breakdown voltage, high-<inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> multiport stacked-transistor topologies are proposed for realizing power amplifiers with high output power and high efficiency at 75-110 GHz. A 90-nm silicon germanium (SiGe) BiCMOS process is used to propose active structures comprising of two and three stacked transistors with integrated layout parasitics that achieve <inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> and breakdown voltage of 295 GHz and 8 V and 260 GHz and 11 V, respectively. Functionality of such multiport transistor topologies is demonstrated in proof-of-concept implementations, including a five-stage two-stacked switching power amplifier (PA) that achieves peak output power and PAE of 22 dBm and 19% at 85 GHz, and a six-stage three-stacked PA that achieves peak output power and PAE of 23.3 dBm and 17% at 83 GHz, respectively. For comparison with conventional switching PA designs using native transistor footprints, a five-stage <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band nonstacked Class-E amplifiers is also fabricated in the same 90-nm SiGe BiCMOS process with output power and PAE of 19.5 dBm and 16% at 88 GHz. The superior performance of output power and PAE in designs using the multiport transistor topologies highlights the benefit of the proposed approach. Heterojunction bipolar transistors Class-E transmitter Silicon power amplifier (PA) Gain Silicon germanium Topology millimeter wave (mm-wave) silicon germanium (SiGe) Power generation HBT Hashemi, Hossein oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 52(2017), 5, Seite 1305-1319 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:52 year:2017 number:5 pages:1305-1319 http://dx.doi.org/10.1109/JSSC.2016.2641464 Volltext http://ieeexplore.ieee.org/document/7815257 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 52 2017 5 1305-1319 |
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10.1109/JSSC.2016.2641464 doi PQ20170501 (DE-627)OLC1992323879 (DE-599)GBVOLC1992323879 (PRQ)ieee_primary_0b00006485b568d00 (KEY)0050684220170000052000501305highbreakdownhighfmultiportstackedtransistortopolo DE-627 ger DE-627 rakwb eng 620 DE-600 Datta, Kunal verfasserin aut High-Breakdown, High- f} Multiport Stacked-Transistor Topologies for the -Band Power Amplifiers 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band frequencies (75-110 GHz), is presented in this paper. To mitigate the performance degradation in output power and PAE arising from such causes, high-breakdown voltage, high-<inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> multiport stacked-transistor topologies are proposed for realizing power amplifiers with high output power and high efficiency at 75-110 GHz. A 90-nm silicon germanium (SiGe) BiCMOS process is used to propose active structures comprising of two and three stacked transistors with integrated layout parasitics that achieve <inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> and breakdown voltage of 295 GHz and 8 V and 260 GHz and 11 V, respectively. Functionality of such multiport transistor topologies is demonstrated in proof-of-concept implementations, including a five-stage two-stacked switching power amplifier (PA) that achieves peak output power and PAE of 22 dBm and 19% at 85 GHz, and a six-stage three-stacked PA that achieves peak output power and PAE of 23.3 dBm and 17% at 83 GHz, respectively. For comparison with conventional switching PA designs using native transistor footprints, a five-stage <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band nonstacked Class-E amplifiers is also fabricated in the same 90-nm SiGe BiCMOS process with output power and PAE of 19.5 dBm and 16% at 88 GHz. The superior performance of output power and PAE in designs using the multiport transistor topologies highlights the benefit of the proposed approach. Heterojunction bipolar transistors Class-E transmitter Silicon power amplifier (PA) Gain Silicon germanium Topology millimeter wave (mm-wave) silicon germanium (SiGe) Power generation HBT Hashemi, Hossein oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 52(2017), 5, Seite 1305-1319 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:52 year:2017 number:5 pages:1305-1319 http://dx.doi.org/10.1109/JSSC.2016.2641464 Volltext http://ieeexplore.ieee.org/document/7815257 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 52 2017 5 1305-1319 |
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10.1109/JSSC.2016.2641464 doi PQ20170501 (DE-627)OLC1992323879 (DE-599)GBVOLC1992323879 (PRQ)ieee_primary_0b00006485b568d00 (KEY)0050684220170000052000501305highbreakdownhighfmultiportstackedtransistortopolo DE-627 ger DE-627 rakwb eng 620 DE-600 Datta, Kunal verfasserin aut High-Breakdown, High- f} Multiport Stacked-Transistor Topologies for the -Band Power Amplifiers 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band frequencies (75-110 GHz), is presented in this paper. To mitigate the performance degradation in output power and PAE arising from such causes, high-breakdown voltage, high-<inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> multiport stacked-transistor topologies are proposed for realizing power amplifiers with high output power and high efficiency at 75-110 GHz. A 90-nm silicon germanium (SiGe) BiCMOS process is used to propose active structures comprising of two and three stacked transistors with integrated layout parasitics that achieve <inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> and breakdown voltage of 295 GHz and 8 V and 260 GHz and 11 V, respectively. Functionality of such multiport transistor topologies is demonstrated in proof-of-concept implementations, including a five-stage two-stacked switching power amplifier (PA) that achieves peak output power and PAE of 22 dBm and 19% at 85 GHz, and a six-stage three-stacked PA that achieves peak output power and PAE of 23.3 dBm and 17% at 83 GHz, respectively. For comparison with conventional switching PA designs using native transistor footprints, a five-stage <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band nonstacked Class-E amplifiers is also fabricated in the same 90-nm SiGe BiCMOS process with output power and PAE of 19.5 dBm and 16% at 88 GHz. The superior performance of output power and PAE in designs using the multiport transistor topologies highlights the benefit of the proposed approach. Heterojunction bipolar transistors Class-E transmitter Silicon power amplifier (PA) Gain Silicon germanium Topology millimeter wave (mm-wave) silicon germanium (SiGe) Power generation HBT Hashemi, Hossein oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 52(2017), 5, Seite 1305-1319 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:52 year:2017 number:5 pages:1305-1319 http://dx.doi.org/10.1109/JSSC.2016.2641464 Volltext http://ieeexplore.ieee.org/document/7815257 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 52 2017 5 1305-1319 |
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10.1109/JSSC.2016.2641464 doi PQ20170501 (DE-627)OLC1992323879 (DE-599)GBVOLC1992323879 (PRQ)ieee_primary_0b00006485b568d00 (KEY)0050684220170000052000501305highbreakdownhighfmultiportstackedtransistortopolo DE-627 ger DE-627 rakwb eng 620 DE-600 Datta, Kunal verfasserin aut High-Breakdown, High- f} Multiport Stacked-Transistor Topologies for the -Band Power Amplifiers 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band frequencies (75-110 GHz), is presented in this paper. To mitigate the performance degradation in output power and PAE arising from such causes, high-breakdown voltage, high-<inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> multiport stacked-transistor topologies are proposed for realizing power amplifiers with high output power and high efficiency at 75-110 GHz. A 90-nm silicon germanium (SiGe) BiCMOS process is used to propose active structures comprising of two and three stacked transistors with integrated layout parasitics that achieve <inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> and breakdown voltage of 295 GHz and 8 V and 260 GHz and 11 V, respectively. Functionality of such multiport transistor topologies is demonstrated in proof-of-concept implementations, including a five-stage two-stacked switching power amplifier (PA) that achieves peak output power and PAE of 22 dBm and 19% at 85 GHz, and a six-stage three-stacked PA that achieves peak output power and PAE of 23.3 dBm and 17% at 83 GHz, respectively. For comparison with conventional switching PA designs using native transistor footprints, a five-stage <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band nonstacked Class-E amplifiers is also fabricated in the same 90-nm SiGe BiCMOS process with output power and PAE of 19.5 dBm and 16% at 88 GHz. The superior performance of output power and PAE in designs using the multiport transistor topologies highlights the benefit of the proposed approach. Heterojunction bipolar transistors Class-E transmitter Silicon power amplifier (PA) Gain Silicon germanium Topology millimeter wave (mm-wave) silicon germanium (SiGe) Power generation HBT Hashemi, Hossein oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 52(2017), 5, Seite 1305-1319 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:52 year:2017 number:5 pages:1305-1319 http://dx.doi.org/10.1109/JSSC.2016.2641464 Volltext http://ieeexplore.ieee.org/document/7815257 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 52 2017 5 1305-1319 |
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10.1109/JSSC.2016.2641464 doi PQ20170501 (DE-627)OLC1992323879 (DE-599)GBVOLC1992323879 (PRQ)ieee_primary_0b00006485b568d00 (KEY)0050684220170000052000501305highbreakdownhighfmultiportstackedtransistortopolo DE-627 ger DE-627 rakwb eng 620 DE-600 Datta, Kunal verfasserin aut High-Breakdown, High- f} Multiport Stacked-Transistor Topologies for the -Band Power Amplifiers 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band frequencies (75-110 GHz), is presented in this paper. To mitigate the performance degradation in output power and PAE arising from such causes, high-breakdown voltage, high-<inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> multiport stacked-transistor topologies are proposed for realizing power amplifiers with high output power and high efficiency at 75-110 GHz. A 90-nm silicon germanium (SiGe) BiCMOS process is used to propose active structures comprising of two and three stacked transistors with integrated layout parasitics that achieve <inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> and breakdown voltage of 295 GHz and 8 V and 260 GHz and 11 V, respectively. Functionality of such multiport transistor topologies is demonstrated in proof-of-concept implementations, including a five-stage two-stacked switching power amplifier (PA) that achieves peak output power and PAE of 22 dBm and 19% at 85 GHz, and a six-stage three-stacked PA that achieves peak output power and PAE of 23.3 dBm and 17% at 83 GHz, respectively. For comparison with conventional switching PA designs using native transistor footprints, a five-stage <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band nonstacked Class-E amplifiers is also fabricated in the same 90-nm SiGe BiCMOS process with output power and PAE of 19.5 dBm and 16% at 88 GHz. The superior performance of output power and PAE in designs using the multiport transistor topologies highlights the benefit of the proposed approach. Heterojunction bipolar transistors Class-E transmitter Silicon power amplifier (PA) Gain Silicon germanium Topology millimeter wave (mm-wave) silicon germanium (SiGe) Power generation HBT Hashemi, Hossein oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 52(2017), 5, Seite 1305-1319 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:52 year:2017 number:5 pages:1305-1319 http://dx.doi.org/10.1109/JSSC.2016.2641464 Volltext http://ieeexplore.ieee.org/document/7815257 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 52 2017 5 1305-1319 |
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620 DE-600 High-Breakdown, High- f} Multiport Stacked-Transistor Topologies for the -Band Power Amplifiers Heterojunction bipolar transistors Class-E transmitter Silicon power amplifier (PA) Gain Silicon germanium Topology millimeter wave (mm-wave) silicon germanium (SiGe) Power generation HBT |
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High-Breakdown, High- f} Multiport Stacked-Transistor Topologies for the -Band Power Amplifiers |
| abstract |
Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band frequencies (75-110 GHz), is presented in this paper. To mitigate the performance degradation in output power and PAE arising from such causes, high-breakdown voltage, high-<inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> multiport stacked-transistor topologies are proposed for realizing power amplifiers with high output power and high efficiency at 75-110 GHz. A 90-nm silicon germanium (SiGe) BiCMOS process is used to propose active structures comprising of two and three stacked transistors with integrated layout parasitics that achieve <inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> and breakdown voltage of 295 GHz and 8 V and 260 GHz and 11 V, respectively. Functionality of such multiport transistor topologies is demonstrated in proof-of-concept implementations, including a five-stage two-stacked switching power amplifier (PA) that achieves peak output power and PAE of 22 dBm and 19% at 85 GHz, and a six-stage three-stacked PA that achieves peak output power and PAE of 23.3 dBm and 17% at 83 GHz, respectively. For comparison with conventional switching PA designs using native transistor footprints, a five-stage <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band nonstacked Class-E amplifiers is also fabricated in the same 90-nm SiGe BiCMOS process with output power and PAE of 19.5 dBm and 16% at 88 GHz. The superior performance of output power and PAE in designs using the multiport transistor topologies highlights the benefit of the proposed approach. |
| abstractGer |
Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band frequencies (75-110 GHz), is presented in this paper. To mitigate the performance degradation in output power and PAE arising from such causes, high-breakdown voltage, high-<inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> multiport stacked-transistor topologies are proposed for realizing power amplifiers with high output power and high efficiency at 75-110 GHz. A 90-nm silicon germanium (SiGe) BiCMOS process is used to propose active structures comprising of two and three stacked transistors with integrated layout parasitics that achieve <inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> and breakdown voltage of 295 GHz and 8 V and 260 GHz and 11 V, respectively. Functionality of such multiport transistor topologies is demonstrated in proof-of-concept implementations, including a five-stage two-stacked switching power amplifier (PA) that achieves peak output power and PAE of 22 dBm and 19% at 85 GHz, and a six-stage three-stacked PA that achieves peak output power and PAE of 23.3 dBm and 17% at 83 GHz, respectively. For comparison with conventional switching PA designs using native transistor footprints, a five-stage <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band nonstacked Class-E amplifiers is also fabricated in the same 90-nm SiGe BiCMOS process with output power and PAE of 19.5 dBm and 16% at 88 GHz. The superior performance of output power and PAE in designs using the multiport transistor topologies highlights the benefit of the proposed approach. |
| abstract_unstemmed |
Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band frequencies (75-110 GHz), is presented in this paper. To mitigate the performance degradation in output power and PAE arising from such causes, high-breakdown voltage, high-<inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> multiport stacked-transistor topologies are proposed for realizing power amplifiers with high output power and high efficiency at 75-110 GHz. A 90-nm silicon germanium (SiGe) BiCMOS process is used to propose active structures comprising of two and three stacked transistors with integrated layout parasitics that achieve <inline-formula> <tex-math notation="LaTeX">f_{\mathrm{ max}} </tex-math></inline-formula> and breakdown voltage of 295 GHz and 8 V and 260 GHz and 11 V, respectively. Functionality of such multiport transistor topologies is demonstrated in proof-of-concept implementations, including a five-stage two-stacked switching power amplifier (PA) that achieves peak output power and PAE of 22 dBm and 19% at 85 GHz, and a six-stage three-stacked PA that achieves peak output power and PAE of 23.3 dBm and 17% at 83 GHz, respectively. For comparison with conventional switching PA designs using native transistor footprints, a five-stage <inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>-band nonstacked Class-E amplifiers is also fabricated in the same 90-nm SiGe BiCMOS process with output power and PAE of 19.5 dBm and 16% at 88 GHz. The superior performance of output power and PAE in designs using the multiport transistor topologies highlights the benefit of the proposed approach. |
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