Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure
We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For t...
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| Autor*in: |
Pahwa, Girish [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2017 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on electron devices - New York, NY : IEEE, 1963, 64(2017), 3, Seite 1366-1374 |
|---|---|
| Übergeordnetes Werk: |
volume:64 ; year:2017 ; number:3 ; pages:1366-1374 |
| Links: |
|---|
| DOI / URN: |
10.1109/TED.2017.2654066 |
|---|
| Katalog-ID: |
OLC1992617732 |
|---|
| LEADER | 01000caa a2200265 4500 | ||
|---|---|---|---|
| 001 | OLC1992617732 | ||
| 003 | DE-627 | ||
| 005 | 20210716185833.0 | ||
| 007 | tu | ||
| 008 | 170512s2017 xx ||||| 00| ||eng c | ||
| 024 | 7 | |a 10.1109/TED.2017.2654066 |2 doi | |
| 028 | 5 | 2 | |a PQ20170501 |
| 035 | |a (DE-627)OLC1992617732 | ||
| 035 | |a (DE-599)GBVOLC1992617732 | ||
| 035 | |a (PRQ)c949-6e54049846848dbb995f0db6fec98f2ffacb0decc4686373e1cf7be9985924e0 | ||
| 035 | |a (KEY)0079428720170000064000301366compactmodelforferroelectricnegativecapacitancetra | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 082 | 0 | 4 | |a 620 |q DNB |
| 100 | 1 | |a Pahwa, Girish |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure |
| 264 | 1 | |c 2017 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a ohne Hilfsmittel zu benutzen |b n |2 rdamedia | ||
| 338 | |a Band |b nc |2 rdacarrier | ||
| 520 | |a We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal-ferroelectric-metal-insulator-semiconductor structure. | ||
| 650 | 4 | |a Compact model | |
| 650 | 4 | |a ferroelectric | |
| 650 | 4 | |a Logic gates | |
| 650 | 4 | |a Numerical models | |
| 650 | 4 | |a negative capacitance FET (NCFET) | |
| 650 | 4 | |a Mathematical model | |
| 650 | 4 | |a Capacitance | |
| 650 | 4 | |a MOSFET | |
| 650 | 4 | |a negative capacitance | |
| 650 | 4 | |a Computational modeling | |
| 700 | 1 | |a Dutta, Tapas |4 oth | |
| 700 | 1 | |a Agarwal, Amit |4 oth | |
| 700 | 1 | |a Chauhan, Yogesh Singh |4 oth | |
| 773 | 0 | 8 | |i Enthalten in |t IEEE transactions on electron devices |d New York, NY : IEEE, 1963 |g 64(2017), 3, Seite 1366-1374 |w (DE-627)129602922 |w (DE-600)241634-7 |w (DE-576)015096734 |x 0018-9383 |7 nnns |
| 773 | 1 | 8 | |g volume:64 |g year:2017 |g number:3 |g pages:1366-1374 |
| 856 | 4 | 1 | |u http://dx.doi.org/10.1109/TED.2017.2654066 |3 Volltext |
| 856 | 4 | 2 | |u http://ieeexplore.ieee.org/document/7837613 |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_OLC | ||
| 912 | |a SSG-OLC-TEC | ||
| 912 | |a SSG-OLC-MAT | ||
| 912 | |a GBV_ILN_70 | ||
| 912 | |a GBV_ILN_2004 | ||
| 912 | |a GBV_ILN_4313 | ||
| 951 | |a AR | ||
| 952 | |d 64 |j 2017 |e 3 |h 1366-1374 | ||
| author_variant |
g p gp |
|---|---|
| matchkey_str |
article:00189383:2017----::opcmdlofrolcrceaieaaiactass |
| hierarchy_sort_str |
2017 |
| publishDate |
2017 |
| allfields |
10.1109/TED.2017.2654066 doi PQ20170501 (DE-627)OLC1992617732 (DE-599)GBVOLC1992617732 (PRQ)c949-6e54049846848dbb995f0db6fec98f2ffacb0decc4686373e1cf7be9985924e0 (KEY)0079428720170000064000301366compactmodelforferroelectricnegativecapacitancetra DE-627 ger DE-627 rakwb eng 620 DNB Pahwa, Girish verfasserin aut Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal-ferroelectric-metal-insulator-semiconductor structure. Compact model ferroelectric Logic gates Numerical models negative capacitance FET (NCFET) Mathematical model Capacitance MOSFET negative capacitance Computational modeling Dutta, Tapas oth Agarwal, Amit oth Chauhan, Yogesh Singh oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 64(2017), 3, Seite 1366-1374 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:64 year:2017 number:3 pages:1366-1374 http://dx.doi.org/10.1109/TED.2017.2654066 Volltext http://ieeexplore.ieee.org/document/7837613 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 64 2017 3 1366-1374 |
| spelling |
10.1109/TED.2017.2654066 doi PQ20170501 (DE-627)OLC1992617732 (DE-599)GBVOLC1992617732 (PRQ)c949-6e54049846848dbb995f0db6fec98f2ffacb0decc4686373e1cf7be9985924e0 (KEY)0079428720170000064000301366compactmodelforferroelectricnegativecapacitancetra DE-627 ger DE-627 rakwb eng 620 DNB Pahwa, Girish verfasserin aut Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal-ferroelectric-metal-insulator-semiconductor structure. Compact model ferroelectric Logic gates Numerical models negative capacitance FET (NCFET) Mathematical model Capacitance MOSFET negative capacitance Computational modeling Dutta, Tapas oth Agarwal, Amit oth Chauhan, Yogesh Singh oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 64(2017), 3, Seite 1366-1374 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:64 year:2017 number:3 pages:1366-1374 http://dx.doi.org/10.1109/TED.2017.2654066 Volltext http://ieeexplore.ieee.org/document/7837613 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 64 2017 3 1366-1374 |
| allfields_unstemmed |
10.1109/TED.2017.2654066 doi PQ20170501 (DE-627)OLC1992617732 (DE-599)GBVOLC1992617732 (PRQ)c949-6e54049846848dbb995f0db6fec98f2ffacb0decc4686373e1cf7be9985924e0 (KEY)0079428720170000064000301366compactmodelforferroelectricnegativecapacitancetra DE-627 ger DE-627 rakwb eng 620 DNB Pahwa, Girish verfasserin aut Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal-ferroelectric-metal-insulator-semiconductor structure. Compact model ferroelectric Logic gates Numerical models negative capacitance FET (NCFET) Mathematical model Capacitance MOSFET negative capacitance Computational modeling Dutta, Tapas oth Agarwal, Amit oth Chauhan, Yogesh Singh oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 64(2017), 3, Seite 1366-1374 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:64 year:2017 number:3 pages:1366-1374 http://dx.doi.org/10.1109/TED.2017.2654066 Volltext http://ieeexplore.ieee.org/document/7837613 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 64 2017 3 1366-1374 |
| allfieldsGer |
10.1109/TED.2017.2654066 doi PQ20170501 (DE-627)OLC1992617732 (DE-599)GBVOLC1992617732 (PRQ)c949-6e54049846848dbb995f0db6fec98f2ffacb0decc4686373e1cf7be9985924e0 (KEY)0079428720170000064000301366compactmodelforferroelectricnegativecapacitancetra DE-627 ger DE-627 rakwb eng 620 DNB Pahwa, Girish verfasserin aut Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal-ferroelectric-metal-insulator-semiconductor structure. Compact model ferroelectric Logic gates Numerical models negative capacitance FET (NCFET) Mathematical model Capacitance MOSFET negative capacitance Computational modeling Dutta, Tapas oth Agarwal, Amit oth Chauhan, Yogesh Singh oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 64(2017), 3, Seite 1366-1374 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:64 year:2017 number:3 pages:1366-1374 http://dx.doi.org/10.1109/TED.2017.2654066 Volltext http://ieeexplore.ieee.org/document/7837613 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 64 2017 3 1366-1374 |
| allfieldsSound |
10.1109/TED.2017.2654066 doi PQ20170501 (DE-627)OLC1992617732 (DE-599)GBVOLC1992617732 (PRQ)c949-6e54049846848dbb995f0db6fec98f2ffacb0decc4686373e1cf7be9985924e0 (KEY)0079428720170000064000301366compactmodelforferroelectricnegativecapacitancetra DE-627 ger DE-627 rakwb eng 620 DNB Pahwa, Girish verfasserin aut Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal-ferroelectric-metal-insulator-semiconductor structure. Compact model ferroelectric Logic gates Numerical models negative capacitance FET (NCFET) Mathematical model Capacitance MOSFET negative capacitance Computational modeling Dutta, Tapas oth Agarwal, Amit oth Chauhan, Yogesh Singh oth Enthalten in IEEE transactions on electron devices New York, NY : IEEE, 1963 64(2017), 3, Seite 1366-1374 (DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 0018-9383 nnns volume:64 year:2017 number:3 pages:1366-1374 http://dx.doi.org/10.1109/TED.2017.2654066 Volltext http://ieeexplore.ieee.org/document/7837613 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 64 2017 3 1366-1374 |
| language |
English |
| source |
Enthalten in IEEE transactions on electron devices 64(2017), 3, Seite 1366-1374 volume:64 year:2017 number:3 pages:1366-1374 |
| sourceStr |
Enthalten in IEEE transactions on electron devices 64(2017), 3, Seite 1366-1374 volume:64 year:2017 number:3 pages:1366-1374 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Compact model ferroelectric Logic gates Numerical models negative capacitance FET (NCFET) Mathematical model Capacitance MOSFET negative capacitance Computational modeling |
| dewey-raw |
620 |
| isfreeaccess_bool |
false |
| container_title |
IEEE transactions on electron devices |
| authorswithroles_txt_mv |
Pahwa, Girish @@aut@@ Dutta, Tapas @@oth@@ Agarwal, Amit @@oth@@ Chauhan, Yogesh Singh @@oth@@ |
| publishDateDaySort_date |
2017-01-01T00:00:00Z |
| hierarchy_top_id |
129602922 |
| dewey-sort |
3620 |
| id |
OLC1992617732 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1992617732</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210716185833.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">170512s2017 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/TED.2017.2654066</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20170501</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1992617732</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1992617732</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)c949-6e54049846848dbb995f0db6fec98f2ffacb0decc4686373e1cf7be9985924e0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)0079428720170000064000301366compactmodelforferroelectricnegativecapacitancetra</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Pahwa, Girish</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2017</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal-ferroelectric-metal-insulator-semiconductor structure.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Compact model</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">ferroelectric</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic gates</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Numerical models</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">negative capacitance FET (NCFET)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Mathematical model</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Capacitance</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">MOSFET</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">negative capacitance</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computational modeling</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Dutta, Tapas</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Agarwal, Amit</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Chauhan, Yogesh Singh</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE transactions on electron devices</subfield><subfield code="d">New York, NY : IEEE, 1963</subfield><subfield code="g">64(2017), 3, Seite 1366-1374</subfield><subfield code="w">(DE-627)129602922</subfield><subfield code="w">(DE-600)241634-7</subfield><subfield code="w">(DE-576)015096734</subfield><subfield code="x">0018-9383</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:64</subfield><subfield code="g">year:2017</subfield><subfield code="g">number:3</subfield><subfield code="g">pages:1366-1374</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/TED.2017.2654066</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/document/7837613</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-MAT</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">64</subfield><subfield code="j">2017</subfield><subfield code="e">3</subfield><subfield code="h">1366-1374</subfield></datafield></record></collection>
|
| author |
Pahwa, Girish |
| spellingShingle |
Pahwa, Girish ddc 620 misc Compact model misc ferroelectric misc Logic gates misc Numerical models misc negative capacitance FET (NCFET) misc Mathematical model misc Capacitance misc MOSFET misc negative capacitance misc Computational modeling Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure |
| authorStr |
Pahwa, Girish |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)129602922 |
| format |
Article |
| dewey-ones |
620 - Engineering & allied operations |
| delete_txt_mv |
keep |
| author_role |
aut |
| collection |
OLC |
| remote_str |
false |
| illustrated |
Not Illustrated |
| issn |
0018-9383 |
| topic_title |
620 DNB Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure Compact model ferroelectric Logic gates Numerical models negative capacitance FET (NCFET) Mathematical model Capacitance MOSFET negative capacitance Computational modeling |
| topic |
ddc 620 misc Compact model misc ferroelectric misc Logic gates misc Numerical models misc negative capacitance FET (NCFET) misc Mathematical model misc Capacitance misc MOSFET misc negative capacitance misc Computational modeling |
| topic_unstemmed |
ddc 620 misc Compact model misc ferroelectric misc Logic gates misc Numerical models misc negative capacitance FET (NCFET) misc Mathematical model misc Capacitance misc MOSFET misc negative capacitance misc Computational modeling |
| topic_browse |
ddc 620 misc Compact model misc ferroelectric misc Logic gates misc Numerical models misc negative capacitance FET (NCFET) misc Mathematical model misc Capacitance misc MOSFET misc negative capacitance misc Computational modeling |
| format_facet |
Aufsätze Gedruckte Aufsätze |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
nc |
| author2_variant |
t d td a a aa y s c ys ysc |
| hierarchy_parent_title |
IEEE transactions on electron devices |
| hierarchy_parent_id |
129602922 |
| dewey-tens |
620 - Engineering |
| hierarchy_top_title |
IEEE transactions on electron devices |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)129602922 (DE-600)241634-7 (DE-576)015096734 |
| title |
Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure |
| ctrlnum |
(DE-627)OLC1992617732 (DE-599)GBVOLC1992617732 (PRQ)c949-6e54049846848dbb995f0db6fec98f2ffacb0decc4686373e1cf7be9985924e0 (KEY)0079428720170000064000301366compactmodelforferroelectricnegativecapacitancetra |
| title_full |
Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure |
| author_sort |
Pahwa, Girish |
| journal |
IEEE transactions on electron devices |
| journalStr |
IEEE transactions on electron devices |
| lang_code |
eng |
| isOA_bool |
false |
| dewey-hundreds |
600 - Technology |
| recordtype |
marc |
| publishDateSort |
2017 |
| contenttype_str_mv |
txt |
| container_start_page |
1366 |
| author_browse |
Pahwa, Girish |
| container_volume |
64 |
| class |
620 DNB |
| format_se |
Aufsätze |
| author-letter |
Pahwa, Girish |
| doi_str_mv |
10.1109/TED.2017.2654066 |
| dewey-full |
620 |
| title_sort |
compact model for ferroelectric negative capacitance transistor with mfis structure |
| title_auth |
Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure |
| abstract |
We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal-ferroelectric-metal-insulator-semiconductor structure. |
| abstractGer |
We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal-ferroelectric-metal-insulator-semiconductor structure. |
| abstract_unstemmed |
We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal-ferroelectric-metal-insulator-semiconductor structure. |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 |
| container_issue |
3 |
| title_short |
Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure |
| url |
http://dx.doi.org/10.1109/TED.2017.2654066 http://ieeexplore.ieee.org/document/7837613 |
| remote_bool |
false |
| author2 |
Dutta, Tapas Agarwal, Amit Chauhan, Yogesh Singh |
| author2Str |
Dutta, Tapas Agarwal, Amit Chauhan, Yogesh Singh |
| ppnlink |
129602922 |
| mediatype_str_mv |
n |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| author2_role |
oth oth oth |
| doi_str |
10.1109/TED.2017.2654066 |
| up_date |
2024-07-04T05:19:30.924Z |
| _version_ |
1803624509250469888 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1992617732</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210716185833.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">170512s2017 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/TED.2017.2654066</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20170501</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1992617732</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1992617732</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)c949-6e54049846848dbb995f0db6fec98f2ffacb0decc4686373e1cf7be9985924e0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)0079428720170000064000301366compactmodelforferroelectricnegativecapacitancetra</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DNB</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Pahwa, Girish</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2017</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal-ferroelectric-metal-insulator-semiconductor structure.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Compact model</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">ferroelectric</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic gates</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Numerical models</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">negative capacitance FET (NCFET)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Mathematical model</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Capacitance</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">MOSFET</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">negative capacitance</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computational modeling</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Dutta, Tapas</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Agarwal, Amit</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Chauhan, Yogesh Singh</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE transactions on electron devices</subfield><subfield code="d">New York, NY : IEEE, 1963</subfield><subfield code="g">64(2017), 3, Seite 1366-1374</subfield><subfield code="w">(DE-627)129602922</subfield><subfield code="w">(DE-600)241634-7</subfield><subfield code="w">(DE-576)015096734</subfield><subfield code="x">0018-9383</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:64</subfield><subfield code="g">year:2017</subfield><subfield code="g">number:3</subfield><subfield code="g">pages:1366-1374</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/TED.2017.2654066</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/document/7837613</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-MAT</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">64</subfield><subfield code="j">2017</subfield><subfield code="e">3</subfield><subfield code="h">1366-1374</subfield></datafield></record></collection>
|
| score |
7.4023485 |