A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC
A 4-bit, third-order, continuous-time <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the fee...
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| Autor*in: |
Cho, Je-Kwang [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2017 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on very large scale integration (VLSI) systems - New York, NY : Institute of Electrical and Electronics Engineers, 1993, 25(2017), 5, Seite 1742-1755 |
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| Übergeordnetes Werk: |
volume:25 ; year:2017 ; number:5 ; pages:1742-1755 |
| Links: |
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| DOI / URN: |
10.1109/TVLSI.2017.2651055 |
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OLC1993358552 |
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| 520 | |a A 4-bit, third-order, continuous-time <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm 2 . | ||
| 650 | 4 | |a high linearity | |
| 650 | 4 | |a continuous time (CT) | |
| 650 | 4 | |a Operational amplifiers | |
| 650 | 4 | |a Modulation | |
| 650 | 4 | |a Signal to noise ratio | |
| 650 | 4 | |a Clocks | |
| 650 | 4 | |a Wireless communication | |
| 650 | 4 | |a Quantization (signal) | |
| 650 | 4 | |a low noise | |
| 650 | 4 | |a sigma-delta modulation | |
| 650 | 4 | |a Analog-to-digital conversion | |
| 650 | 4 | |a Bandwidth | |
| 700 | 1 | |a Woo, Sunsik |4 oth | |
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10.1109/TVLSI.2017.2651055 doi PQ20170501 (DE-627)OLC1993358552 (DE-599)GBVOLC1993358552 (PRQ)c960-192d8aa0b0650b74c41ffd57ea1c17235920a1bb33f641f93ded1eab70e6f1a90 (KEY)02262649201700000250005017426mw701dbsndrand20mhzbwcontinuoustimesigmadeltamodu DE-627 ger DE-627 rakwb eng 004 620 DE-600 Cho, Je-Kwang verfasserin aut A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A 4-bit, third-order, continuous-time <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm 2 . high linearity continuous time (CT) Operational amplifiers Modulation Signal to noise ratio Clocks Wireless communication Quantization (signal) low noise sigma-delta modulation Analog-to-digital conversion Bandwidth Woo, Sunsik oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 25(2017), 5, Seite 1742-1755 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:25 year:2017 number:5 pages:1742-1755 http://dx.doi.org/10.1109/TVLSI.2017.2651055 Volltext http://ieeexplore.ieee.org/document/7839317 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 25 2017 5 1742-1755 |
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10.1109/TVLSI.2017.2651055 doi PQ20170501 (DE-627)OLC1993358552 (DE-599)GBVOLC1993358552 (PRQ)c960-192d8aa0b0650b74c41ffd57ea1c17235920a1bb33f641f93ded1eab70e6f1a90 (KEY)02262649201700000250005017426mw701dbsndrand20mhzbwcontinuoustimesigmadeltamodu DE-627 ger DE-627 rakwb eng 004 620 DE-600 Cho, Je-Kwang verfasserin aut A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A 4-bit, third-order, continuous-time <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm 2 . high linearity continuous time (CT) Operational amplifiers Modulation Signal to noise ratio Clocks Wireless communication Quantization (signal) low noise sigma-delta modulation Analog-to-digital conversion Bandwidth Woo, Sunsik oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 25(2017), 5, Seite 1742-1755 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:25 year:2017 number:5 pages:1742-1755 http://dx.doi.org/10.1109/TVLSI.2017.2651055 Volltext http://ieeexplore.ieee.org/document/7839317 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 25 2017 5 1742-1755 |
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10.1109/TVLSI.2017.2651055 doi PQ20170501 (DE-627)OLC1993358552 (DE-599)GBVOLC1993358552 (PRQ)c960-192d8aa0b0650b74c41ffd57ea1c17235920a1bb33f641f93ded1eab70e6f1a90 (KEY)02262649201700000250005017426mw701dbsndrand20mhzbwcontinuoustimesigmadeltamodu DE-627 ger DE-627 rakwb eng 004 620 DE-600 Cho, Je-Kwang verfasserin aut A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A 4-bit, third-order, continuous-time <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm 2 . high linearity continuous time (CT) Operational amplifiers Modulation Signal to noise ratio Clocks Wireless communication Quantization (signal) low noise sigma-delta modulation Analog-to-digital conversion Bandwidth Woo, Sunsik oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 25(2017), 5, Seite 1742-1755 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:25 year:2017 number:5 pages:1742-1755 http://dx.doi.org/10.1109/TVLSI.2017.2651055 Volltext http://ieeexplore.ieee.org/document/7839317 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 25 2017 5 1742-1755 |
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10.1109/TVLSI.2017.2651055 doi PQ20170501 (DE-627)OLC1993358552 (DE-599)GBVOLC1993358552 (PRQ)c960-192d8aa0b0650b74c41ffd57ea1c17235920a1bb33f641f93ded1eab70e6f1a90 (KEY)02262649201700000250005017426mw701dbsndrand20mhzbwcontinuoustimesigmadeltamodu DE-627 ger DE-627 rakwb eng 004 620 DE-600 Cho, Je-Kwang verfasserin aut A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A 4-bit, third-order, continuous-time <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm 2 . high linearity continuous time (CT) Operational amplifiers Modulation Signal to noise ratio Clocks Wireless communication Quantization (signal) low noise sigma-delta modulation Analog-to-digital conversion Bandwidth Woo, Sunsik oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 25(2017), 5, Seite 1742-1755 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:25 year:2017 number:5 pages:1742-1755 http://dx.doi.org/10.1109/TVLSI.2017.2651055 Volltext http://ieeexplore.ieee.org/document/7839317 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 25 2017 5 1742-1755 |
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10.1109/TVLSI.2017.2651055 doi PQ20170501 (DE-627)OLC1993358552 (DE-599)GBVOLC1993358552 (PRQ)c960-192d8aa0b0650b74c41ffd57ea1c17235920a1bb33f641f93ded1eab70e6f1a90 (KEY)02262649201700000250005017426mw701dbsndrand20mhzbwcontinuoustimesigmadeltamodu DE-627 ger DE-627 rakwb eng 004 620 DE-600 Cho, Je-Kwang verfasserin aut A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A 4-bit, third-order, continuous-time <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm 2 . high linearity continuous time (CT) Operational amplifiers Modulation Signal to noise ratio Clocks Wireless communication Quantization (signal) low noise sigma-delta modulation Analog-to-digital conversion Bandwidth Woo, Sunsik oth Enthalten in IEEE transactions on very large scale integration (VLSI) systems New York, NY : Institute of Electrical and Electronics Engineers, 1993 25(2017), 5, Seite 1742-1755 (DE-627)165670282 (DE-600)1151835-2 (DE-576)034204024 1063-8210 nnns volume:25 year:2017 number:5 pages:1742-1755 http://dx.doi.org/10.1109/TVLSI.2017.2651055 Volltext http://ieeexplore.ieee.org/document/7839317 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 AR 25 2017 5 1742-1755 |
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Cho, Je-Kwang ddc 004 misc high linearity misc continuous time (CT) misc Operational amplifiers misc Modulation misc Signal to noise ratio misc Clocks misc Wireless communication misc Quantization (signal) misc low noise misc sigma-delta modulation misc Analog-to-digital conversion misc Bandwidth A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC |
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6-mw, 70.1-db sndr, and 20-mhz bw continuous-time sigma-delta modulator using low-noise high-linearity feedback dac |
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A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC |
| abstract |
A 4-bit, third-order, continuous-time <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm 2 . |
| abstractGer |
A 4-bit, third-order, continuous-time <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm 2 . |
| abstract_unstemmed |
A 4-bit, third-order, continuous-time <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm 2 . |
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A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC |
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