Quantum circuit physical design flow for 2D nearest‐neighbor architectures
The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gat...
Ausführliche Beschreibung
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| Autor*in: |
Farghadan, Azim [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2017 |
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| Rechteinformationen: |
Nutzungsrecht: Copyright © 2017 John Wiley & Sons, Ltd. |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: International journal of circuit theory and applications - London : Wiley, 1973, 45(2017), 7, Seite 989-1000 |
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| Übergeordnetes Werk: |
volume:45 ; year:2017 ; number:7 ; pages:989-1000 |
| Links: |
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| DOI / URN: |
10.1002/cta.2335 |
|---|
| Katalog-ID: |
OLC1994686812 |
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| 520 | |a The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd. In this paper, a physical design flow was proposed for 2D nearest‐neighbor architecture. Three algorithms introduced for order finding, placement, and routing showed great performance in decreasing the number of swap gates and the runtime compared with PAQCS that is the best in the literature. Scalability is illustrated through simulations with circuits involving dozens of qubits and thousands of gates. | ||
| 540 | |a Nutzungsrecht: Copyright © 2017 John Wiley & Sons, Ltd. | ||
| 650 | 4 | |a placement | |
| 650 | 4 | |a routing | |
| 650 | 4 | |a physical design | |
| 650 | 4 | |a quantum circuits | |
| 650 | 4 | |a nearest‐neighbor architecture | |
| 650 | 4 | |a Qubits (quantum computing) | |
| 650 | 4 | |a Electronic design automation | |
| 650 | 4 | |a Algorithms | |
| 650 | 4 | |a Gates (circuits) | |
| 650 | 4 | |a Gates | |
| 650 | 4 | |a Placement | |
| 650 | 4 | |a Two dimensional flow | |
| 650 | 4 | |a Platforms | |
| 650 | 4 | |a Logic | |
| 650 | 4 | |a Computer simulation | |
| 650 | 4 | |a Circuit design | |
| 650 | 4 | |a Logic synthesis | |
| 650 | 4 | |a Mapping | |
| 650 | 4 | |a Run time (computers) | |
| 650 | 4 | |a Electronics industry | |
| 700 | 1 | |a Mohammadzadeh, Naser |4 oth | |
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10.1002/cta.2335 doi PQ20170721 (DE-627)OLC1994686812 (DE-599)GBVOLC1994686812 (PRQ)p1195-83943b79c44cb28b309bcdc23e42bb1ed9e1111ccabc862e58245033146398143 (KEY)0080156920170000045000700989quantumcircuitphysicaldesignflowfor2dnearestneighb DE-627 ger DE-627 rakwb eng 620 ZDB Farghadan, Azim verfasserin aut Quantum circuit physical design flow for 2D nearest‐neighbor architectures 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd. In this paper, a physical design flow was proposed for 2D nearest‐neighbor architecture. Three algorithms introduced for order finding, placement, and routing showed great performance in decreasing the number of swap gates and the runtime compared with PAQCS that is the best in the literature. Scalability is illustrated through simulations with circuits involving dozens of qubits and thousands of gates. Nutzungsrecht: Copyright © 2017 John Wiley & Sons, Ltd. placement routing physical design quantum circuits nearest‐neighbor architecture Qubits (quantum computing) Electronic design automation Algorithms Gates (circuits) Gates Placement Two dimensional flow Platforms Logic Computer simulation Circuit design Logic synthesis Mapping Run time (computers) Electronics industry Mohammadzadeh, Naser oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 45(2017), 7, Seite 989-1000 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:45 year:2017 number:7 pages:989-1000 http://dx.doi.org/10.1002/cta.2335 Volltext http://onlinelibrary.wiley.com/doi/10.1002/cta.2335/abstract https://search.proquest.com/docview/1918728216 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 45 2017 7 989-1000 |
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10.1002/cta.2335 doi PQ20170721 (DE-627)OLC1994686812 (DE-599)GBVOLC1994686812 (PRQ)p1195-83943b79c44cb28b309bcdc23e42bb1ed9e1111ccabc862e58245033146398143 (KEY)0080156920170000045000700989quantumcircuitphysicaldesignflowfor2dnearestneighb DE-627 ger DE-627 rakwb eng 620 ZDB Farghadan, Azim verfasserin aut Quantum circuit physical design flow for 2D nearest‐neighbor architectures 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd. In this paper, a physical design flow was proposed for 2D nearest‐neighbor architecture. Three algorithms introduced for order finding, placement, and routing showed great performance in decreasing the number of swap gates and the runtime compared with PAQCS that is the best in the literature. Scalability is illustrated through simulations with circuits involving dozens of qubits and thousands of gates. Nutzungsrecht: Copyright © 2017 John Wiley & Sons, Ltd. placement routing physical design quantum circuits nearest‐neighbor architecture Qubits (quantum computing) Electronic design automation Algorithms Gates (circuits) Gates Placement Two dimensional flow Platforms Logic Computer simulation Circuit design Logic synthesis Mapping Run time (computers) Electronics industry Mohammadzadeh, Naser oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 45(2017), 7, Seite 989-1000 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:45 year:2017 number:7 pages:989-1000 http://dx.doi.org/10.1002/cta.2335 Volltext http://onlinelibrary.wiley.com/doi/10.1002/cta.2335/abstract https://search.proquest.com/docview/1918728216 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 45 2017 7 989-1000 |
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10.1002/cta.2335 doi PQ20170721 (DE-627)OLC1994686812 (DE-599)GBVOLC1994686812 (PRQ)p1195-83943b79c44cb28b309bcdc23e42bb1ed9e1111ccabc862e58245033146398143 (KEY)0080156920170000045000700989quantumcircuitphysicaldesignflowfor2dnearestneighb DE-627 ger DE-627 rakwb eng 620 ZDB Farghadan, Azim verfasserin aut Quantum circuit physical design flow for 2D nearest‐neighbor architectures 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd. In this paper, a physical design flow was proposed for 2D nearest‐neighbor architecture. Three algorithms introduced for order finding, placement, and routing showed great performance in decreasing the number of swap gates and the runtime compared with PAQCS that is the best in the literature. Scalability is illustrated through simulations with circuits involving dozens of qubits and thousands of gates. Nutzungsrecht: Copyright © 2017 John Wiley & Sons, Ltd. placement routing physical design quantum circuits nearest‐neighbor architecture Qubits (quantum computing) Electronic design automation Algorithms Gates (circuits) Gates Placement Two dimensional flow Platforms Logic Computer simulation Circuit design Logic synthesis Mapping Run time (computers) Electronics industry Mohammadzadeh, Naser oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 45(2017), 7, Seite 989-1000 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:45 year:2017 number:7 pages:989-1000 http://dx.doi.org/10.1002/cta.2335 Volltext http://onlinelibrary.wiley.com/doi/10.1002/cta.2335/abstract https://search.proquest.com/docview/1918728216 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 45 2017 7 989-1000 |
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10.1002/cta.2335 doi PQ20170721 (DE-627)OLC1994686812 (DE-599)GBVOLC1994686812 (PRQ)p1195-83943b79c44cb28b309bcdc23e42bb1ed9e1111ccabc862e58245033146398143 (KEY)0080156920170000045000700989quantumcircuitphysicaldesignflowfor2dnearestneighb DE-627 ger DE-627 rakwb eng 620 ZDB Farghadan, Azim verfasserin aut Quantum circuit physical design flow for 2D nearest‐neighbor architectures 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd. In this paper, a physical design flow was proposed for 2D nearest‐neighbor architecture. Three algorithms introduced for order finding, placement, and routing showed great performance in decreasing the number of swap gates and the runtime compared with PAQCS that is the best in the literature. Scalability is illustrated through simulations with circuits involving dozens of qubits and thousands of gates. Nutzungsrecht: Copyright © 2017 John Wiley & Sons, Ltd. placement routing physical design quantum circuits nearest‐neighbor architecture Qubits (quantum computing) Electronic design automation Algorithms Gates (circuits) Gates Placement Two dimensional flow Platforms Logic Computer simulation Circuit design Logic synthesis Mapping Run time (computers) Electronics industry Mohammadzadeh, Naser oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 45(2017), 7, Seite 989-1000 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:45 year:2017 number:7 pages:989-1000 http://dx.doi.org/10.1002/cta.2335 Volltext http://onlinelibrary.wiley.com/doi/10.1002/cta.2335/abstract https://search.proquest.com/docview/1918728216 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 45 2017 7 989-1000 |
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10.1002/cta.2335 doi PQ20170721 (DE-627)OLC1994686812 (DE-599)GBVOLC1994686812 (PRQ)p1195-83943b79c44cb28b309bcdc23e42bb1ed9e1111ccabc862e58245033146398143 (KEY)0080156920170000045000700989quantumcircuitphysicaldesignflowfor2dnearestneighb DE-627 ger DE-627 rakwb eng 620 ZDB Farghadan, Azim verfasserin aut Quantum circuit physical design flow for 2D nearest‐neighbor architectures 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd. In this paper, a physical design flow was proposed for 2D nearest‐neighbor architecture. Three algorithms introduced for order finding, placement, and routing showed great performance in decreasing the number of swap gates and the runtime compared with PAQCS that is the best in the literature. Scalability is illustrated through simulations with circuits involving dozens of qubits and thousands of gates. Nutzungsrecht: Copyright © 2017 John Wiley & Sons, Ltd. placement routing physical design quantum circuits nearest‐neighbor architecture Qubits (quantum computing) Electronic design automation Algorithms Gates (circuits) Gates Placement Two dimensional flow Platforms Logic Computer simulation Circuit design Logic synthesis Mapping Run time (computers) Electronics industry Mohammadzadeh, Naser oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 45(2017), 7, Seite 989-1000 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:45 year:2017 number:7 pages:989-1000 http://dx.doi.org/10.1002/cta.2335 Volltext http://onlinelibrary.wiley.com/doi/10.1002/cta.2335/abstract https://search.proquest.com/docview/1918728216 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 45 2017 7 989-1000 |
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In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd. In this paper, a physical design flow was proposed for 2D nearest‐neighbor architecture. Three algorithms introduced for order finding, placement, and routing showed great performance in decreasing the number of swap gates and the runtime compared with PAQCS that is the best in the literature. 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The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd. In this paper, a physical design flow was proposed for 2D nearest‐neighbor architecture. Three algorithms introduced for order finding, placement, and routing showed great performance in decreasing the number of swap gates and the runtime compared with PAQCS that is the best in the literature. Scalability is illustrated through simulations with circuits involving dozens of qubits and thousands of gates. |
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The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd. In this paper, a physical design flow was proposed for 2D nearest‐neighbor architecture. Three algorithms introduced for order finding, placement, and routing showed great performance in decreasing the number of swap gates and the runtime compared with PAQCS that is the best in the literature. Scalability is illustrated through simulations with circuits involving dozens of qubits and thousands of gates. |
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The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd. In this paper, a physical design flow was proposed for 2D nearest‐neighbor architecture. Three algorithms introduced for order finding, placement, and routing showed great performance in decreasing the number of swap gates and the runtime compared with PAQCS that is the best in the literature. Scalability is illustrated through simulations with circuits involving dozens of qubits and thousands of gates. |
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