FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency
Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code...
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| Autor*in: |
Guo, Jie [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2017 |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on computer-aided design of integrated circuits and systems - New York, NY : Institute of Electrical and Electronics Engineers, 1982, 36(2017), 7, Seite 1167-1180 |
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| Übergeordnetes Werk: |
volume:36 ; year:2017 ; number:7 ; pages:1167-1180 |
| Links: |
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| DOI / URN: |
10.1109/TCAD.2016.2619480 |
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| 520 | |a Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction capability. However, to achieve better performance, LDPC code demands extra memory sensing operations and more data transfer cycles, directly leading to longer read latency. To achieve both system reliability and read efficiency, we propose the FlexLevel NAND flash storage system design in this paper. FlexLevel consists of two levels of optimization: 1) LevelAdjust and 2) AccessEval. At device level, the LevelAdjust technique is proposed to reduce BER by broadening noise margin via threshold voltage level reduction. With LevelAdjust, BER is greatly reduced and no extra sensing levels are required to protect data integrity. Hence, read performance is improved. However, while LevelAdjust can improve system reliability and read performance, it causes density loss. To balance read performance improvement and density loss, we propose the AccessEval technique at system level. AccessEval identifies data with high LDPC overhead and only applies LevelAdjust technique to these data. The experimental results show that compared with the best existing works, the proposed design can achieve up to 11% read speedup with negligible density loss. | ||
| 650 | 4 | |a noise margin | |
| 650 | 4 | |a Logic gates | |
| 650 | 4 | |a Sensors | |
| 650 | 4 | |a Bit error rate (BER) | |
| 650 | 4 | |a Reliability | |
| 650 | 4 | |a low density parity check (LDPC) | |
| 650 | 4 | |a read latency | |
| 650 | 4 | |a NAND flash | |
| 650 | 4 | |a Interference | |
| 650 | 4 | |a Bit error rate | |
| 650 | 4 | |a Error correction codes | |
| 650 | 4 | |a Parity check codes | |
| 700 | 1 | |a Wen, Wujie |4 oth | |
| 700 | 1 | |a Hu, Jingtong |4 oth | |
| 700 | 1 | |a Wang, Danghui |4 oth | |
| 700 | 1 | |a Li, Hai |4 oth | |
| 700 | 1 | |a Chen, Yiran |4 oth | |
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10.1109/TCAD.2016.2619480 doi PQ20170721 (DE-627)OLC1994851899 (DE-599)GBVOLC1994851899 (PRQ)c1079-fd1dfff7e5b53484c0f41c4b12162e606166a3070c36e3bfa4c77631a42bd7530 (KEY)0113814620170000036000701167flexlevelnandflashstoragesystemdesigntoreduceldpcl DE-627 ger DE-627 rakwb eng 620 DE-600 Guo, Jie verfasserin aut FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction capability. However, to achieve better performance, LDPC code demands extra memory sensing operations and more data transfer cycles, directly leading to longer read latency. To achieve both system reliability and read efficiency, we propose the FlexLevel NAND flash storage system design in this paper. FlexLevel consists of two levels of optimization: 1) LevelAdjust and 2) AccessEval. At device level, the LevelAdjust technique is proposed to reduce BER by broadening noise margin via threshold voltage level reduction. With LevelAdjust, BER is greatly reduced and no extra sensing levels are required to protect data integrity. Hence, read performance is improved. However, while LevelAdjust can improve system reliability and read performance, it causes density loss. To balance read performance improvement and density loss, we propose the AccessEval technique at system level. AccessEval identifies data with high LDPC overhead and only applies LevelAdjust technique to these data. The experimental results show that compared with the best existing works, the proposed design can achieve up to 11% read speedup with negligible density loss. noise margin Logic gates Sensors Bit error rate (BER) Reliability low density parity check (LDPC) read latency NAND flash Interference Bit error rate Error correction codes Parity check codes Wen, Wujie oth Hu, Jingtong oth Wang, Danghui oth Li, Hai oth Chen, Yiran oth Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems New York, NY : Institute of Electrical and Electronics Engineers, 1982 36(2017), 7, Seite 1167-1180 (DE-627)13041705X (DE-600)627344-0 (DE-576)015919471 0278-0070 nnns volume:36 year:2017 number:7 pages:1167-1180 http://dx.doi.org/10.1109/TCAD.2016.2619480 Volltext http://ieeexplore.ieee.org/document/7605542 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_4313 AR 36 2017 7 1167-1180 |
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10.1109/TCAD.2016.2619480 doi PQ20170721 (DE-627)OLC1994851899 (DE-599)GBVOLC1994851899 (PRQ)c1079-fd1dfff7e5b53484c0f41c4b12162e606166a3070c36e3bfa4c77631a42bd7530 (KEY)0113814620170000036000701167flexlevelnandflashstoragesystemdesigntoreduceldpcl DE-627 ger DE-627 rakwb eng 620 DE-600 Guo, Jie verfasserin aut FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction capability. However, to achieve better performance, LDPC code demands extra memory sensing operations and more data transfer cycles, directly leading to longer read latency. To achieve both system reliability and read efficiency, we propose the FlexLevel NAND flash storage system design in this paper. FlexLevel consists of two levels of optimization: 1) LevelAdjust and 2) AccessEval. At device level, the LevelAdjust technique is proposed to reduce BER by broadening noise margin via threshold voltage level reduction. With LevelAdjust, BER is greatly reduced and no extra sensing levels are required to protect data integrity. Hence, read performance is improved. However, while LevelAdjust can improve system reliability and read performance, it causes density loss. To balance read performance improvement and density loss, we propose the AccessEval technique at system level. AccessEval identifies data with high LDPC overhead and only applies LevelAdjust technique to these data. The experimental results show that compared with the best existing works, the proposed design can achieve up to 11% read speedup with negligible density loss. noise margin Logic gates Sensors Bit error rate (BER) Reliability low density parity check (LDPC) read latency NAND flash Interference Bit error rate Error correction codes Parity check codes Wen, Wujie oth Hu, Jingtong oth Wang, Danghui oth Li, Hai oth Chen, Yiran oth Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems New York, NY : Institute of Electrical and Electronics Engineers, 1982 36(2017), 7, Seite 1167-1180 (DE-627)13041705X (DE-600)627344-0 (DE-576)015919471 0278-0070 nnns volume:36 year:2017 number:7 pages:1167-1180 http://dx.doi.org/10.1109/TCAD.2016.2619480 Volltext http://ieeexplore.ieee.org/document/7605542 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_4313 AR 36 2017 7 1167-1180 |
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10.1109/TCAD.2016.2619480 doi PQ20170721 (DE-627)OLC1994851899 (DE-599)GBVOLC1994851899 (PRQ)c1079-fd1dfff7e5b53484c0f41c4b12162e606166a3070c36e3bfa4c77631a42bd7530 (KEY)0113814620170000036000701167flexlevelnandflashstoragesystemdesigntoreduceldpcl DE-627 ger DE-627 rakwb eng 620 DE-600 Guo, Jie verfasserin aut FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction capability. However, to achieve better performance, LDPC code demands extra memory sensing operations and more data transfer cycles, directly leading to longer read latency. To achieve both system reliability and read efficiency, we propose the FlexLevel NAND flash storage system design in this paper. FlexLevel consists of two levels of optimization: 1) LevelAdjust and 2) AccessEval. At device level, the LevelAdjust technique is proposed to reduce BER by broadening noise margin via threshold voltage level reduction. With LevelAdjust, BER is greatly reduced and no extra sensing levels are required to protect data integrity. Hence, read performance is improved. However, while LevelAdjust can improve system reliability and read performance, it causes density loss. To balance read performance improvement and density loss, we propose the AccessEval technique at system level. AccessEval identifies data with high LDPC overhead and only applies LevelAdjust technique to these data. The experimental results show that compared with the best existing works, the proposed design can achieve up to 11% read speedup with negligible density loss. noise margin Logic gates Sensors Bit error rate (BER) Reliability low density parity check (LDPC) read latency NAND flash Interference Bit error rate Error correction codes Parity check codes Wen, Wujie oth Hu, Jingtong oth Wang, Danghui oth Li, Hai oth Chen, Yiran oth Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems New York, NY : Institute of Electrical and Electronics Engineers, 1982 36(2017), 7, Seite 1167-1180 (DE-627)13041705X (DE-600)627344-0 (DE-576)015919471 0278-0070 nnns volume:36 year:2017 number:7 pages:1167-1180 http://dx.doi.org/10.1109/TCAD.2016.2619480 Volltext http://ieeexplore.ieee.org/document/7605542 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_4313 AR 36 2017 7 1167-1180 |
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10.1109/TCAD.2016.2619480 doi PQ20170721 (DE-627)OLC1994851899 (DE-599)GBVOLC1994851899 (PRQ)c1079-fd1dfff7e5b53484c0f41c4b12162e606166a3070c36e3bfa4c77631a42bd7530 (KEY)0113814620170000036000701167flexlevelnandflashstoragesystemdesigntoreduceldpcl DE-627 ger DE-627 rakwb eng 620 DE-600 Guo, Jie verfasserin aut FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction capability. However, to achieve better performance, LDPC code demands extra memory sensing operations and more data transfer cycles, directly leading to longer read latency. To achieve both system reliability and read efficiency, we propose the FlexLevel NAND flash storage system design in this paper. FlexLevel consists of two levels of optimization: 1) LevelAdjust and 2) AccessEval. At device level, the LevelAdjust technique is proposed to reduce BER by broadening noise margin via threshold voltage level reduction. With LevelAdjust, BER is greatly reduced and no extra sensing levels are required to protect data integrity. Hence, read performance is improved. However, while LevelAdjust can improve system reliability and read performance, it causes density loss. To balance read performance improvement and density loss, we propose the AccessEval technique at system level. AccessEval identifies data with high LDPC overhead and only applies LevelAdjust technique to these data. The experimental results show that compared with the best existing works, the proposed design can achieve up to 11% read speedup with negligible density loss. noise margin Logic gates Sensors Bit error rate (BER) Reliability low density parity check (LDPC) read latency NAND flash Interference Bit error rate Error correction codes Parity check codes Wen, Wujie oth Hu, Jingtong oth Wang, Danghui oth Li, Hai oth Chen, Yiran oth Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems New York, NY : Institute of Electrical and Electronics Engineers, 1982 36(2017), 7, Seite 1167-1180 (DE-627)13041705X (DE-600)627344-0 (DE-576)015919471 0278-0070 nnns volume:36 year:2017 number:7 pages:1167-1180 http://dx.doi.org/10.1109/TCAD.2016.2619480 Volltext http://ieeexplore.ieee.org/document/7605542 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_4313 AR 36 2017 7 1167-1180 |
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10.1109/TCAD.2016.2619480 doi PQ20170721 (DE-627)OLC1994851899 (DE-599)GBVOLC1994851899 (PRQ)c1079-fd1dfff7e5b53484c0f41c4b12162e606166a3070c36e3bfa4c77631a42bd7530 (KEY)0113814620170000036000701167flexlevelnandflashstoragesystemdesigntoreduceldpcl DE-627 ger DE-627 rakwb eng 620 DE-600 Guo, Jie verfasserin aut FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction capability. However, to achieve better performance, LDPC code demands extra memory sensing operations and more data transfer cycles, directly leading to longer read latency. To achieve both system reliability and read efficiency, we propose the FlexLevel NAND flash storage system design in this paper. FlexLevel consists of two levels of optimization: 1) LevelAdjust and 2) AccessEval. At device level, the LevelAdjust technique is proposed to reduce BER by broadening noise margin via threshold voltage level reduction. With LevelAdjust, BER is greatly reduced and no extra sensing levels are required to protect data integrity. Hence, read performance is improved. However, while LevelAdjust can improve system reliability and read performance, it causes density loss. To balance read performance improvement and density loss, we propose the AccessEval technique at system level. AccessEval identifies data with high LDPC overhead and only applies LevelAdjust technique to these data. The experimental results show that compared with the best existing works, the proposed design can achieve up to 11% read speedup with negligible density loss. noise margin Logic gates Sensors Bit error rate (BER) Reliability low density parity check (LDPC) read latency NAND flash Interference Bit error rate Error correction codes Parity check codes Wen, Wujie oth Hu, Jingtong oth Wang, Danghui oth Li, Hai oth Chen, Yiran oth Enthalten in IEEE transactions on computer-aided design of integrated circuits and systems New York, NY : Institute of Electrical and Electronics Engineers, 1982 36(2017), 7, Seite 1167-1180 (DE-627)13041705X (DE-600)627344-0 (DE-576)015919471 0278-0070 nnns volume:36 year:2017 number:7 pages:1167-1180 http://dx.doi.org/10.1109/TCAD.2016.2619480 Volltext http://ieeexplore.ieee.org/document/7605542 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2002 GBV_ILN_2004 GBV_ILN_4313 AR 36 2017 7 1167-1180 |
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To balance read performance improvement and density loss, we propose the AccessEval technique at system level. AccessEval identifies data with high LDPC overhead and only applies LevelAdjust technique to these data. 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FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency |
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Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction capability. However, to achieve better performance, LDPC code demands extra memory sensing operations and more data transfer cycles, directly leading to longer read latency. To achieve both system reliability and read efficiency, we propose the FlexLevel NAND flash storage system design in this paper. FlexLevel consists of two levels of optimization: 1) LevelAdjust and 2) AccessEval. At device level, the LevelAdjust technique is proposed to reduce BER by broadening noise margin via threshold voltage level reduction. With LevelAdjust, BER is greatly reduced and no extra sensing levels are required to protect data integrity. Hence, read performance is improved. However, while LevelAdjust can improve system reliability and read performance, it causes density loss. To balance read performance improvement and density loss, we propose the AccessEval technique at system level. AccessEval identifies data with high LDPC overhead and only applies LevelAdjust technique to these data. The experimental results show that compared with the best existing works, the proposed design can achieve up to 11% read speedup with negligible density loss. |
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Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction capability. However, to achieve better performance, LDPC code demands extra memory sensing operations and more data transfer cycles, directly leading to longer read latency. To achieve both system reliability and read efficiency, we propose the FlexLevel NAND flash storage system design in this paper. FlexLevel consists of two levels of optimization: 1) LevelAdjust and 2) AccessEval. At device level, the LevelAdjust technique is proposed to reduce BER by broadening noise margin via threshold voltage level reduction. With LevelAdjust, BER is greatly reduced and no extra sensing levels are required to protect data integrity. Hence, read performance is improved. However, while LevelAdjust can improve system reliability and read performance, it causes density loss. To balance read performance improvement and density loss, we propose the AccessEval technique at system level. AccessEval identifies data with high LDPC overhead and only applies LevelAdjust technique to these data. The experimental results show that compared with the best existing works, the proposed design can achieve up to 11% read speedup with negligible density loss. |
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Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction capability. However, to achieve better performance, LDPC code demands extra memory sensing operations and more data transfer cycles, directly leading to longer read latency. To achieve both system reliability and read efficiency, we propose the FlexLevel NAND flash storage system design in this paper. FlexLevel consists of two levels of optimization: 1) LevelAdjust and 2) AccessEval. At device level, the LevelAdjust technique is proposed to reduce BER by broadening noise margin via threshold voltage level reduction. With LevelAdjust, BER is greatly reduced and no extra sensing levels are required to protect data integrity. Hence, read performance is improved. However, while LevelAdjust can improve system reliability and read performance, it causes density loss. To balance read performance improvement and density loss, we propose the AccessEval technique at system level. AccessEval identifies data with high LDPC overhead and only applies LevelAdjust technique to these data. The experimental results show that compared with the best existing works, the proposed design can achieve up to 11% read speedup with negligible density loss. |
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