A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer

A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator. Operating with a r...
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Gespeichert in:

Autor*in:	Kong, Long [verfasserIn] Razavi, Behzad

Format:	Artikel
Sprache:	Englisch

Erschienen:	2017

Schlagwörter:	Voltage-controlled oscillators Synthesizers fractional-N synthesizer noise trap Phase locked loops cascaded phase-locked loop (PLL) noise filter Phase noise Delays Delay lines noise PLL Bandwidth

Übergeordnetes Werk:	Enthalten in: IEEE journal of solid state circuits - New York, NY : IEEE, 1966, 52(2017), 8, Seite 2117-2127
Übergeordnetes Werk:	volume:52 ; year:2017 ; number:8 ; pages:2117-2127

Links:	Volltext Link aufrufen

DOI / URN:	10.1109/JSSC.2017.2686838

Katalog-ID:	OLC1995930636

Internformat


LEADER	01000caa a2200265 4500
001	OLC1995930636
003	DE-627
005	20210716210101.0
007	tu
008	170901s2017 xx \|\|\|\|\| 00\| \|\|eng c
024	7		\|a 10.1109/JSSC.2017.2686838 \|2 doi
028	5	2	\|a PQ20171228
035			\|a (DE-627)OLC1995930636
035			\|a (DE-599)GBVOLC1995930636
035			\|a (PRQ)i940-4ffb01b760173bdb0f5c70bf9cfc8f48b5f931287eba8f876731549b6daf26150
035			\|a (KEY)005068422017000005200080211724ghz64mwfractionalninductorlessrfsynthesizer
040			\|a DE-627 \|b ger \|c DE-627 \|e rakwb
041			\|a eng
082	0	4	\|a 620 \|q DE-600
100	1		\|a Kong, Long \|e verfasserin \|4 aut
245	1	2	\|a A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer
264		1	\|c 2017
336			\|a Text \|b txt \|2 rdacontent
337			\|a ohne Hilfsmittel zu benutzen \|b n \|2 rdamedia
338			\|a Band \|b nc \|2 rdacarrier
520			\|a A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of −109 dBc/Hz and an integrated jitter of 1.68 ps rms .
650		4	\|a Voltage-controlled oscillators
650		4	\|a Synthesizers
650		4	\|a fractional-N synthesizer
650		4	\|a noise trap
650		4	\|a Phase locked loops
650		4	\|a cascaded phase-locked loop (PLL)
650		4	\|a noise filter
650		4	\|a Phase noise
650		4	\|a Delays
650		4	\|a Delay lines
650		4	\|a noise
650		4	\|a PLL
650		4	\|a Bandwidth
700	1		\|a Razavi, Behzad \|4 oth
773	0	8	\|i Enthalten in \|t IEEE journal of solid state circuits \|d New York, NY : IEEE, 1966 \|g 52(2017), 8, Seite 2117-2127 \|w (DE-627)129594865 \|w (DE-600)240580-5 \|w (DE-576)01508776X \|x 0018-9200 \|7 nnns
773	1	8	\|g volume:52 \|g year:2017 \|g number:8 \|g pages:2117-2127
856	4	1	\|u http://dx.doi.org/10.1109/JSSC.2017.2686838 \|3 Volltext
856	4	2	\|u http://ieeexplore.ieee.org/document/7907263
912			\|a GBV_USEFLAG_A
912			\|a SYSFLAG_A
912			\|a GBV_OLC
912			\|a SSG-OLC-TEC
912			\|a SSG-OLC-PHY
912			\|a GBV_ILN_70
912			\|a GBV_ILN_2004
912			\|a GBV_ILN_4313
951			\|a AR
952			\|d 52 \|j 2017 \|e 8 \|h 2117-2127

Indexfelder

author_variant	l k lk
matchkey_str	article:00189200:2017----::2gz4wrcinlidcols
hierarchy_sort_str	2017
publishDate	2017
allfields	10.1109/JSSC.2017.2686838 doi PQ20171228 (DE-627)OLC1995930636 (DE-599)GBVOLC1995930636 (PRQ)i940-4ffb01b760173bdb0f5c70bf9cfc8f48b5f931287eba8f876731549b6daf26150 (KEY)005068422017000005200080211724ghz64mwfractionalninductorlessrfsynthesizer DE-627 ger DE-627 rakwb eng 620 DE-600 Kong, Long verfasserin aut A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of −109 dBc/Hz and an integrated jitter of 1.68 ps rms . Voltage-controlled oscillators Synthesizers fractional-N synthesizer noise trap Phase locked loops cascaded phase-locked loop (PLL) noise filter Phase noise Delays Delay lines noise PLL Bandwidth Razavi, Behzad oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 52(2017), 8, Seite 2117-2127 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:52 year:2017 number:8 pages:2117-2127 http://dx.doi.org/10.1109/JSSC.2017.2686838 Volltext http://ieeexplore.ieee.org/document/7907263 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 52 2017 8 2117-2127
spelling	10.1109/JSSC.2017.2686838 doi PQ20171228 (DE-627)OLC1995930636 (DE-599)GBVOLC1995930636 (PRQ)i940-4ffb01b760173bdb0f5c70bf9cfc8f48b5f931287eba8f876731549b6daf26150 (KEY)005068422017000005200080211724ghz64mwfractionalninductorlessrfsynthesizer DE-627 ger DE-627 rakwb eng 620 DE-600 Kong, Long verfasserin aut A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of −109 dBc/Hz and an integrated jitter of 1.68 ps rms . Voltage-controlled oscillators Synthesizers fractional-N synthesizer noise trap Phase locked loops cascaded phase-locked loop (PLL) noise filter Phase noise Delays Delay lines noise PLL Bandwidth Razavi, Behzad oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 52(2017), 8, Seite 2117-2127 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:52 year:2017 number:8 pages:2117-2127 http://dx.doi.org/10.1109/JSSC.2017.2686838 Volltext http://ieeexplore.ieee.org/document/7907263 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 52 2017 8 2117-2127
allfields_unstemmed	10.1109/JSSC.2017.2686838 doi PQ20171228 (DE-627)OLC1995930636 (DE-599)GBVOLC1995930636 (PRQ)i940-4ffb01b760173bdb0f5c70bf9cfc8f48b5f931287eba8f876731549b6daf26150 (KEY)005068422017000005200080211724ghz64mwfractionalninductorlessrfsynthesizer DE-627 ger DE-627 rakwb eng 620 DE-600 Kong, Long verfasserin aut A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of −109 dBc/Hz and an integrated jitter of 1.68 ps rms . Voltage-controlled oscillators Synthesizers fractional-N synthesizer noise trap Phase locked loops cascaded phase-locked loop (PLL) noise filter Phase noise Delays Delay lines noise PLL Bandwidth Razavi, Behzad oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 52(2017), 8, Seite 2117-2127 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:52 year:2017 number:8 pages:2117-2127 http://dx.doi.org/10.1109/JSSC.2017.2686838 Volltext http://ieeexplore.ieee.org/document/7907263 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 52 2017 8 2117-2127
allfieldsGer	10.1109/JSSC.2017.2686838 doi PQ20171228 (DE-627)OLC1995930636 (DE-599)GBVOLC1995930636 (PRQ)i940-4ffb01b760173bdb0f5c70bf9cfc8f48b5f931287eba8f876731549b6daf26150 (KEY)005068422017000005200080211724ghz64mwfractionalninductorlessrfsynthesizer DE-627 ger DE-627 rakwb eng 620 DE-600 Kong, Long verfasserin aut A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of −109 dBc/Hz and an integrated jitter of 1.68 ps rms . Voltage-controlled oscillators Synthesizers fractional-N synthesizer noise trap Phase locked loops cascaded phase-locked loop (PLL) noise filter Phase noise Delays Delay lines noise PLL Bandwidth Razavi, Behzad oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 52(2017), 8, Seite 2117-2127 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:52 year:2017 number:8 pages:2117-2127 http://dx.doi.org/10.1109/JSSC.2017.2686838 Volltext http://ieeexplore.ieee.org/document/7907263 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 52 2017 8 2117-2127
allfieldsSound	10.1109/JSSC.2017.2686838 doi PQ20171228 (DE-627)OLC1995930636 (DE-599)GBVOLC1995930636 (PRQ)i940-4ffb01b760173bdb0f5c70bf9cfc8f48b5f931287eba8f876731549b6daf26150 (KEY)005068422017000005200080211724ghz64mwfractionalninductorlessrfsynthesizer DE-627 ger DE-627 rakwb eng 620 DE-600 Kong, Long verfasserin aut A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of −109 dBc/Hz and an integrated jitter of 1.68 ps rms . Voltage-controlled oscillators Synthesizers fractional-N synthesizer noise trap Phase locked loops cascaded phase-locked loop (PLL) noise filter Phase noise Delays Delay lines noise PLL Bandwidth Razavi, Behzad oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 52(2017), 8, Seite 2117-2127 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:52 year:2017 number:8 pages:2117-2127 http://dx.doi.org/10.1109/JSSC.2017.2686838 Volltext http://ieeexplore.ieee.org/document/7907263 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR 52 2017 8 2117-2127
language	English
source	Enthalten in IEEE journal of solid state circuits 52(2017), 8, Seite 2117-2127 volume:52 year:2017 number:8 pages:2117-2127
sourceStr	Enthalten in IEEE journal of solid state circuits 52(2017), 8, Seite 2117-2127 volume:52 year:2017 number:8 pages:2117-2127
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	Voltage-controlled oscillators Synthesizers fractional-N synthesizer noise trap Phase locked loops cascaded phase-locked loop (PLL) noise filter Phase noise Delays Delay lines noise PLL Bandwidth
dewey-raw	620
isfreeaccess_bool	false
container_title	IEEE journal of solid state circuits
authorswithroles_txt_mv	Kong, Long @@aut@@ Razavi, Behzad @@oth@@
publishDateDaySort_date	2017-01-01T00:00:00Z
hierarchy_top_id	129594865
dewey-sort	3620
id	OLC1995930636
language_de	englisch
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1995930636</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210716210101.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">170901s2017 xx \|\|\|\|\| 00\| \|\|eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/JSSC.2017.2686838</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20171228</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1995930636</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1995930636</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)i940-4ffb01b760173bdb0f5c70bf9cfc8f48b5f931287eba8f876731549b6daf26150</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)005068422017000005200080211724ghz64mwfractionalninductorlessrfsynthesizer</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DE-600</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kong, Long</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2017</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of −109 dBc/Hz and an integrated jitter of 1.68 ps rms .</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Voltage-controlled oscillators</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Synthesizers</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">fractional-N synthesizer</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">noise trap</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase locked loops</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">cascaded phase-locked loop (PLL)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">noise filter</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase noise</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Delays</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Delay lines</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">noise</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">PLL</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Bandwidth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Razavi, Behzad</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE journal of solid state circuits</subfield><subfield code="d">New York, NY : IEEE, 1966</subfield><subfield code="g">52(2017), 8, Seite 2117-2127</subfield><subfield code="w">(DE-627)129594865</subfield><subfield code="w">(DE-600)240580-5</subfield><subfield code="w">(DE-576)01508776X</subfield><subfield code="x">0018-9200</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:52</subfield><subfield code="g">year:2017</subfield><subfield code="g">number:8</subfield><subfield code="g">pages:2117-2127</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/JSSC.2017.2686838</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/document/7907263</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-PHY</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">52</subfield><subfield code="j">2017</subfield><subfield code="e">8</subfield><subfield code="h">2117-2127</subfield></datafield></record></collection>
author	Kong, Long
spellingShingle	Kong, Long ddc 620 misc Voltage-controlled oscillators misc Synthesizers misc fractional-N synthesizer misc noise trap misc Phase locked loops misc cascaded phase-locked loop (PLL) misc noise filter misc Phase noise misc Delays misc Delay lines misc noise misc PLL misc Bandwidth A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer
authorStr	Kong, Long
ppnlink_with_tag_str_mv	@@773@@(DE-627)129594865
format	Article
dewey-ones	620 - Engineering & allied operations
delete_txt_mv	keep
author_role	aut
collection	OLC
remote_str	false
illustrated	Not Illustrated
issn	0018-9200
topic_title	620 DE-600 A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer Voltage-controlled oscillators Synthesizers fractional-N synthesizer noise trap Phase locked loops cascaded phase-locked loop (PLL) noise filter Phase noise Delays Delay lines noise PLL Bandwidth
topic	ddc 620 misc Voltage-controlled oscillators misc Synthesizers misc fractional-N synthesizer misc noise trap misc Phase locked loops misc cascaded phase-locked loop (PLL) misc noise filter misc Phase noise misc Delays misc Delay lines misc noise misc PLL misc Bandwidth
topic_unstemmed	ddc 620 misc Voltage-controlled oscillators misc Synthesizers misc fractional-N synthesizer misc noise trap misc Phase locked loops misc cascaded phase-locked loop (PLL) misc noise filter misc Phase noise misc Delays misc Delay lines misc noise misc PLL misc Bandwidth
topic_browse	ddc 620 misc Voltage-controlled oscillators misc Synthesizers misc fractional-N synthesizer misc noise trap misc Phase locked loops misc cascaded phase-locked loop (PLL) misc noise filter misc Phase noise misc Delays misc Delay lines misc noise misc PLL misc Bandwidth
format_facet	Aufsätze Gedruckte Aufsätze
format_main_str_mv	Text Zeitschrift/Artikel
carriertype_str_mv	nc
author2_variant	b r br
hierarchy_parent_title	IEEE journal of solid state circuits
hierarchy_parent_id	129594865
dewey-tens	620 - Engineering
hierarchy_top_title	IEEE journal of solid state circuits
isfreeaccess_txt	false
familylinks_str_mv	(DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X
title	A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer
ctrlnum	(DE-627)OLC1995930636 (DE-599)GBVOLC1995930636 (PRQ)i940-4ffb01b760173bdb0f5c70bf9cfc8f48b5f931287eba8f876731549b6daf26150 (KEY)005068422017000005200080211724ghz64mwfractionalninductorlessrfsynthesizer
title_full	A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer
author_sort	Kong, Long
journal	IEEE journal of solid state circuits
journalStr	IEEE journal of solid state circuits
lang_code	eng
isOA_bool	false
dewey-hundreds	600 - Technology
recordtype	marc
publishDateSort	2017
contenttype_str_mv	txt
container_start_page	2117
author_browse	Kong, Long
container_volume	52
class	620 DE-600
format_se	Aufsätze
author-letter	Kong, Long
doi_str_mv	10.1109/JSSC.2017.2686838
dewey-full	620
title_sort	2.4-ghz 6.4-mw fractional-n inductorless rf synthesizer
title_auth	A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer
abstract	A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of −109 dBc/Hz and an integrated jitter of 1.68 ps rms .
abstractGer	A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of −109 dBc/Hz and an integrated jitter of 1.68 ps rms .
abstract_unstemmed	A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of −109 dBc/Hz and an integrated jitter of 1.68 ps rms .
collection_details	GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313
container_issue	8
title_short	A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer
url	http://dx.doi.org/10.1109/JSSC.2017.2686838 http://ieeexplore.ieee.org/document/7907263
remote_bool	false
author2	Razavi, Behzad
author2Str	Razavi, Behzad
ppnlink	129594865
mediatype_str_mv	n
isOA_txt	false
hochschulschrift_bool	false
author2_role	oth
doi_str	10.1109/JSSC.2017.2686838
up_date	2024-07-03T23:14:05.666Z
_version_	1803601518964768769
fullrecord_marcxml	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a2200265 4500</leader><controlfield tag="001">OLC1995930636</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20210716210101.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">170901s2017 xx \|\|\|\|\| 00\| \|\|eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1109/JSSC.2017.2686838</subfield><subfield code="2">doi</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">PQ20171228</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC1995930636</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBVOLC1995930636</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(PRQ)i940-4ffb01b760173bdb0f5c70bf9cfc8f48b5f931287eba8f876731549b6daf26150</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(KEY)005068422017000005200080211724ghz64mwfractionalninductorlessrfsynthesizer</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="q">DE-600</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kong, Long</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2017</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an analog noise trap to suppress the quantization noise of the <inline-formula> <tex-math notation="LaTeX">\Sigma \Delta </tex-math></inline-formula> modulator. Operating with a reference frequency of 22.6 MHz, the synthesizer achieves a bandwidth of 10 MHz in the first loop and 12 MHz in the second, heavily suppressing the phase noise of its constituent ring oscillators. Realized in 45-nm digital CMOS technology, the synthesizer exhibits an in-band phase noise of −109 dBc/Hz and an integrated jitter of 1.68 ps rms .</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Voltage-controlled oscillators</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Synthesizers</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">fractional-N synthesizer</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">noise trap</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase locked loops</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">cascaded phase-locked loop (PLL)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">noise filter</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase noise</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Delays</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Delay lines</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">noise</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">PLL</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Bandwidth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Razavi, Behzad</subfield><subfield code="4">oth</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">IEEE journal of solid state circuits</subfield><subfield code="d">New York, NY : IEEE, 1966</subfield><subfield code="g">52(2017), 8, Seite 2117-2127</subfield><subfield code="w">(DE-627)129594865</subfield><subfield code="w">(DE-600)240580-5</subfield><subfield code="w">(DE-576)01508776X</subfield><subfield code="x">0018-9200</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:52</subfield><subfield code="g">year:2017</subfield><subfield code="g">number:8</subfield><subfield code="g">pages:2117-2127</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">http://dx.doi.org/10.1109/JSSC.2017.2686838</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="u">http://ieeexplore.ieee.org/document/7907263</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-PHY</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">52</subfield><subfield code="j">2017</subfield><subfield code="e">8</subfield><subfield code="h">2117-2127</subfield></datafield></record></collection>
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