Design and Analysis of a 1.8-GHz Open-Loop Modulator for Phase Modulation and Frequency Synthesis Using TDC-Based Calibration
A nonlinearity calibration technique is proposed for an open-loop phase modulator (PM), for wideband phase modulation, and for multiple-output, low-jitter clock generation. The design considerations and key performance aspects of the calibration technique are discussed. The PM integrates a digital p...
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| Autor*in: |
Nidhi, Nitin [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2017 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: IEEE transactions on microwave theory and techniques - New York, NY : IEEE, 1963, 65(2017), 10, Seite 3975-3988 |
|---|---|
| Übergeordnetes Werk: |
volume:65 ; year:2017 ; number:10 ; pages:3975-3988 |
| Links: |
|---|
| DOI / URN: |
10.1109/TMTT.2017.2697879 |
|---|
| Katalog-ID: |
OLC1996891960 |
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| 520 | |a A nonlinearity calibration technique is proposed for an open-loop phase modulator (PM), for wideband phase modulation, and for multiple-output, low-jitter clock generation. The design considerations and key performance aspects of the calibration technique are discussed. The PM integrates a digital phase-locked loop, local oscillator distribution network, and digital calibration. A prototype was implemented in 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS 1.8-GHz Gaussian frequency shift keying (GFSK) transmitter integrated circuit. Measurements on the prototype show that out-of-band quantization noise is 56 dB lower than that of the signal when transmitting 20-Mb/s GFSK signal and the rms error is only 3.2%. The power consumption of the PM is 18 mW. The measured spurious tones of the clock generation unit are below −46 dBc. | ||
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| 650 | 4 | |a power amplifiers | |
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| 650 | 4 | |a Calibration | |
| 650 | 4 | |a Phase locked loops | |
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10.1109/TMTT.2017.2697879 doi PQ20171228 (DE-627)OLC1996891960 (DE-599)GBVOLC1996891960 (PRQ)i652-41ed130a0a5b264ef757e8fc6411b88f426c27e5dbcb7a62e42ba3576984614c0 (KEY)0017514520170000065001003975designandanalysisofa18ghzopenloopmodulatorforphase DE-627 ger DE-627 rakwb eng 620 DE-600 53.00 bkl Nidhi, Nitin verfasserin aut Design and Analysis of a 1.8-GHz Open-Loop Modulator for Phase Modulation and Frequency Synthesis Using TDC-Based Calibration 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A nonlinearity calibration technique is proposed for an open-loop phase modulator (PM), for wideband phase modulation, and for multiple-output, low-jitter clock generation. The design considerations and key performance aspects of the calibration technique are discussed. The PM integrates a digital phase-locked loop, local oscillator distribution network, and digital calibration. A prototype was implemented in 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS 1.8-GHz Gaussian frequency shift keying (GFSK) transmitter integrated circuit. Measurements on the prototype show that out-of-band quantization noise is 56 dB lower than that of the signal when transmitting 20-Mb/s GFSK signal and the rms error is only 3.2%. The power consumption of the PM is 18 mW. The measured spurious tones of the clock generation unit are below −46 dBc. Phase measurement Phase modulation phase-locked loops (PLLs) Frequency synthesizers Frequency modulation power amplifiers Clocks Calibration Phase locked loops Pamarti, Sudhakar oth Enthalten in IEEE transactions on microwave theory and techniques New York, NY : IEEE, 1963 65(2017), 10, Seite 3975-3988 (DE-627)129547344 (DE-600)218509-X (DE-576)01499822X 0018-9480 nnns volume:65 year:2017 number:10 pages:3975-3988 http://dx.doi.org/10.1109/TMTT.2017.2697879 Volltext http://ieeexplore.ieee.org/document/7930424 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_2016 GBV_ILN_4313 53.00 AVZ AR 65 2017 10 3975-3988 |
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10.1109/TMTT.2017.2697879 doi PQ20171228 (DE-627)OLC1996891960 (DE-599)GBVOLC1996891960 (PRQ)i652-41ed130a0a5b264ef757e8fc6411b88f426c27e5dbcb7a62e42ba3576984614c0 (KEY)0017514520170000065001003975designandanalysisofa18ghzopenloopmodulatorforphase DE-627 ger DE-627 rakwb eng 620 DE-600 53.00 bkl Nidhi, Nitin verfasserin aut Design and Analysis of a 1.8-GHz Open-Loop Modulator for Phase Modulation and Frequency Synthesis Using TDC-Based Calibration 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A nonlinearity calibration technique is proposed for an open-loop phase modulator (PM), for wideband phase modulation, and for multiple-output, low-jitter clock generation. The design considerations and key performance aspects of the calibration technique are discussed. The PM integrates a digital phase-locked loop, local oscillator distribution network, and digital calibration. A prototype was implemented in 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS 1.8-GHz Gaussian frequency shift keying (GFSK) transmitter integrated circuit. Measurements on the prototype show that out-of-band quantization noise is 56 dB lower than that of the signal when transmitting 20-Mb/s GFSK signal and the rms error is only 3.2%. The power consumption of the PM is 18 mW. The measured spurious tones of the clock generation unit are below −46 dBc. Phase measurement Phase modulation phase-locked loops (PLLs) Frequency synthesizers Frequency modulation power amplifiers Clocks Calibration Phase locked loops Pamarti, Sudhakar oth Enthalten in IEEE transactions on microwave theory and techniques New York, NY : IEEE, 1963 65(2017), 10, Seite 3975-3988 (DE-627)129547344 (DE-600)218509-X (DE-576)01499822X 0018-9480 nnns volume:65 year:2017 number:10 pages:3975-3988 http://dx.doi.org/10.1109/TMTT.2017.2697879 Volltext http://ieeexplore.ieee.org/document/7930424 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_2016 GBV_ILN_4313 53.00 AVZ AR 65 2017 10 3975-3988 |
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10.1109/TMTT.2017.2697879 doi PQ20171228 (DE-627)OLC1996891960 (DE-599)GBVOLC1996891960 (PRQ)i652-41ed130a0a5b264ef757e8fc6411b88f426c27e5dbcb7a62e42ba3576984614c0 (KEY)0017514520170000065001003975designandanalysisofa18ghzopenloopmodulatorforphase DE-627 ger DE-627 rakwb eng 620 DE-600 53.00 bkl Nidhi, Nitin verfasserin aut Design and Analysis of a 1.8-GHz Open-Loop Modulator for Phase Modulation and Frequency Synthesis Using TDC-Based Calibration 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A nonlinearity calibration technique is proposed for an open-loop phase modulator (PM), for wideband phase modulation, and for multiple-output, low-jitter clock generation. The design considerations and key performance aspects of the calibration technique are discussed. The PM integrates a digital phase-locked loop, local oscillator distribution network, and digital calibration. A prototype was implemented in 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS 1.8-GHz Gaussian frequency shift keying (GFSK) transmitter integrated circuit. Measurements on the prototype show that out-of-band quantization noise is 56 dB lower than that of the signal when transmitting 20-Mb/s GFSK signal and the rms error is only 3.2%. The power consumption of the PM is 18 mW. The measured spurious tones of the clock generation unit are below −46 dBc. Phase measurement Phase modulation phase-locked loops (PLLs) Frequency synthesizers Frequency modulation power amplifiers Clocks Calibration Phase locked loops Pamarti, Sudhakar oth Enthalten in IEEE transactions on microwave theory and techniques New York, NY : IEEE, 1963 65(2017), 10, Seite 3975-3988 (DE-627)129547344 (DE-600)218509-X (DE-576)01499822X 0018-9480 nnns volume:65 year:2017 number:10 pages:3975-3988 http://dx.doi.org/10.1109/TMTT.2017.2697879 Volltext http://ieeexplore.ieee.org/document/7930424 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_2016 GBV_ILN_4313 53.00 AVZ AR 65 2017 10 3975-3988 |
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10.1109/TMTT.2017.2697879 doi PQ20171228 (DE-627)OLC1996891960 (DE-599)GBVOLC1996891960 (PRQ)i652-41ed130a0a5b264ef757e8fc6411b88f426c27e5dbcb7a62e42ba3576984614c0 (KEY)0017514520170000065001003975designandanalysisofa18ghzopenloopmodulatorforphase DE-627 ger DE-627 rakwb eng 620 DE-600 53.00 bkl Nidhi, Nitin verfasserin aut Design and Analysis of a 1.8-GHz Open-Loop Modulator for Phase Modulation and Frequency Synthesis Using TDC-Based Calibration 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A nonlinearity calibration technique is proposed for an open-loop phase modulator (PM), for wideband phase modulation, and for multiple-output, low-jitter clock generation. The design considerations and key performance aspects of the calibration technique are discussed. The PM integrates a digital phase-locked loop, local oscillator distribution network, and digital calibration. A prototype was implemented in 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS 1.8-GHz Gaussian frequency shift keying (GFSK) transmitter integrated circuit. Measurements on the prototype show that out-of-band quantization noise is 56 dB lower than that of the signal when transmitting 20-Mb/s GFSK signal and the rms error is only 3.2%. The power consumption of the PM is 18 mW. The measured spurious tones of the clock generation unit are below −46 dBc. Phase measurement Phase modulation phase-locked loops (PLLs) Frequency synthesizers Frequency modulation power amplifiers Clocks Calibration Phase locked loops Pamarti, Sudhakar oth Enthalten in IEEE transactions on microwave theory and techniques New York, NY : IEEE, 1963 65(2017), 10, Seite 3975-3988 (DE-627)129547344 (DE-600)218509-X (DE-576)01499822X 0018-9480 nnns volume:65 year:2017 number:10 pages:3975-3988 http://dx.doi.org/10.1109/TMTT.2017.2697879 Volltext http://ieeexplore.ieee.org/document/7930424 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_2016 GBV_ILN_4313 53.00 AVZ AR 65 2017 10 3975-3988 |
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10.1109/TMTT.2017.2697879 doi PQ20171228 (DE-627)OLC1996891960 (DE-599)GBVOLC1996891960 (PRQ)i652-41ed130a0a5b264ef757e8fc6411b88f426c27e5dbcb7a62e42ba3576984614c0 (KEY)0017514520170000065001003975designandanalysisofa18ghzopenloopmodulatorforphase DE-627 ger DE-627 rakwb eng 620 DE-600 53.00 bkl Nidhi, Nitin verfasserin aut Design and Analysis of a 1.8-GHz Open-Loop Modulator for Phase Modulation and Frequency Synthesis Using TDC-Based Calibration 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A nonlinearity calibration technique is proposed for an open-loop phase modulator (PM), for wideband phase modulation, and for multiple-output, low-jitter clock generation. The design considerations and key performance aspects of the calibration technique are discussed. The PM integrates a digital phase-locked loop, local oscillator distribution network, and digital calibration. A prototype was implemented in 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS 1.8-GHz Gaussian frequency shift keying (GFSK) transmitter integrated circuit. Measurements on the prototype show that out-of-band quantization noise is 56 dB lower than that of the signal when transmitting 20-Mb/s GFSK signal and the rms error is only 3.2%. The power consumption of the PM is 18 mW. The measured spurious tones of the clock generation unit are below −46 dBc. Phase measurement Phase modulation phase-locked loops (PLLs) Frequency synthesizers Frequency modulation power amplifiers Clocks Calibration Phase locked loops Pamarti, Sudhakar oth Enthalten in IEEE transactions on microwave theory and techniques New York, NY : IEEE, 1963 65(2017), 10, Seite 3975-3988 (DE-627)129547344 (DE-600)218509-X (DE-576)01499822X 0018-9480 nnns volume:65 year:2017 number:10 pages:3975-3988 http://dx.doi.org/10.1109/TMTT.2017.2697879 Volltext http://ieeexplore.ieee.org/document/7930424 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_2016 GBV_ILN_4313 53.00 AVZ AR 65 2017 10 3975-3988 |
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Design and Analysis of a 1.8-GHz Open-Loop Modulator for Phase Modulation and Frequency Synthesis Using TDC-Based Calibration |
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Design and Analysis of a 1.8-GHz Open-Loop Modulator for Phase Modulation and Frequency Synthesis Using TDC-Based Calibration |
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Nidhi, Nitin |
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IEEE transactions on microwave theory and techniques |
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IEEE transactions on microwave theory and techniques |
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Nidhi, Nitin |
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10.1109/TMTT.2017.2697879 |
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620 |
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design and analysis of a 1.8-ghz open-loop modulator for phase modulation and frequency synthesis using tdc-based calibration |
| title_auth |
Design and Analysis of a 1.8-GHz Open-Loop Modulator for Phase Modulation and Frequency Synthesis Using TDC-Based Calibration |
| abstract |
A nonlinearity calibration technique is proposed for an open-loop phase modulator (PM), for wideband phase modulation, and for multiple-output, low-jitter clock generation. The design considerations and key performance aspects of the calibration technique are discussed. The PM integrates a digital phase-locked loop, local oscillator distribution network, and digital calibration. A prototype was implemented in 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS 1.8-GHz Gaussian frequency shift keying (GFSK) transmitter integrated circuit. Measurements on the prototype show that out-of-band quantization noise is 56 dB lower than that of the signal when transmitting 20-Mb/s GFSK signal and the rms error is only 3.2%. The power consumption of the PM is 18 mW. The measured spurious tones of the clock generation unit are below −46 dBc. |
| abstractGer |
A nonlinearity calibration technique is proposed for an open-loop phase modulator (PM), for wideband phase modulation, and for multiple-output, low-jitter clock generation. The design considerations and key performance aspects of the calibration technique are discussed. The PM integrates a digital phase-locked loop, local oscillator distribution network, and digital calibration. A prototype was implemented in 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS 1.8-GHz Gaussian frequency shift keying (GFSK) transmitter integrated circuit. Measurements on the prototype show that out-of-band quantization noise is 56 dB lower than that of the signal when transmitting 20-Mb/s GFSK signal and the rms error is only 3.2%. The power consumption of the PM is 18 mW. The measured spurious tones of the clock generation unit are below −46 dBc. |
| abstract_unstemmed |
A nonlinearity calibration technique is proposed for an open-loop phase modulator (PM), for wideband phase modulation, and for multiple-output, low-jitter clock generation. The design considerations and key performance aspects of the calibration technique are discussed. The PM integrates a digital phase-locked loop, local oscillator distribution network, and digital calibration. A prototype was implemented in 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS 1.8-GHz Gaussian frequency shift keying (GFSK) transmitter integrated circuit. Measurements on the prototype show that out-of-band quantization noise is 56 dB lower than that of the signal when transmitting 20-Mb/s GFSK signal and the rms error is only 3.2%. The power consumption of the PM is 18 mW. The measured spurious tones of the clock generation unit are below −46 dBc. |
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10 |
| title_short |
Design and Analysis of a 1.8-GHz Open-Loop Modulator for Phase Modulation and Frequency Synthesis Using TDC-Based Calibration |
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http://dx.doi.org/10.1109/TMTT.2017.2697879 http://ieeexplore.ieee.org/document/7930424 |
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