A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology

A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, an...
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Autor*in:	Devarajan, Siddharth [verfasserIn] Devarajan, Siddharth Singer, Larry Kelly, Dan Pan, Tao Silva, Jose Brunsilius, Janet Rey-Losada, Daniel Murden, Frank Speir, Carroll Bray, Jeffery Otte, Eric Rakuljic, Nevena Brown, Phil Weigandt, Todd Yu, Qicheng Paterson, Donald Petersen, Corey Gealow, Jeffrey Manganaro, Gabriele

Format:	Artikel
Sprache:	Englisch

Erschienen:	2017

Schlagwörter:	Timing pipeline ADC Calibration Clocks CMOS interleaved (IL) ADC gigahertz data conversion direct RF sampling analog-to-digital converter (ADC) Power demand Power capacitors digitally assisted analog design switched capacitor Pipelines CMOS technology

Übergeordnetes Werk:	Enthalten in: IEEE journal of solid state circuits - New York, NY : IEEE, 1966, PP(2017), 99, Seite 1-3218
Übergeordnetes Werk:	volume:PP ; year:2017 ; number:99 ; pages:1-3218

Links:	Volltext Link aufrufen

DOI / URN:	10.1109/JSSC.2017.2747758

Katalog-ID:	OLC1998958590

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520			\|a A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push-pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs.
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700	1		\|a Rey-Losada, Daniel \|4 oth
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700	1		\|a Murden, Frank \|4 oth
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700	1		\|a Bray, Jeffery \|4 oth
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700	1		\|a Otte, Eric \|4 oth
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700	1		\|a Rakuljic, Nevena \|4 oth
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700	1		\|a Brown, Phil \|4 oth
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700	1		\|a Weigandt, Todd \|4 oth
700	1		\|a Weigandt, Todd \|4 oth
700	1		\|a Yu, Qicheng \|4 oth
700	1		\|a Yu, Qicheng \|4 oth
700	1		\|a Paterson, Donald \|4 oth
700	1		\|a Paterson, Donald \|4 oth
700	1		\|a Petersen, Corey \|4 oth
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700	1		\|a Gealow, Jeffrey \|4 oth
700	1		\|a Gealow, Jeffrey \|4 oth
700	1		\|a Manganaro, Gabriele \|4 oth
700	1		\|a Manganaro, Gabriele \|4 oth
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publishDate	2017
allfields	10.1109/JSSC.2017.2747758 doi PQ20171228 (DE-627)OLC1998958590 (DE-599)GBVOLC1998958590 (PRQ)i949-b37485587cb84cd12f432562da909e1b38912b7d58cbe1895ec265df02b379300 (KEY)005068422017000000000990000112b10gssinterleavedpipelineadcin28nmcmostechnology DE-627 ger DE-627 rakwb eng 620 DE-600 Devarajan, Siddharth verfasserin aut A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push-pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs. Timing pipeline ADC Calibration Clocks CMOS interleaved (IL) ADC gigahertz data conversion direct RF sampling analog-to-digital converter (ADC) Power demand Power capacitors digitally assisted analog design switched capacitor Pipelines CMOS technology Devarajan, Siddharth oth Singer, Larry oth Singer, Larry oth Kelly, Dan oth Kelly, Dan oth Pan, Tao oth Pan, Tao oth Silva, Jose oth Silva, Jose oth Brunsilius, Janet oth Brunsilius, Janet oth Rey-Losada, Daniel oth Rey-Losada, Daniel oth Murden, Frank oth Murden, Frank oth Speir, Carroll oth Speir, Carroll oth Bray, Jeffery oth Bray, Jeffery oth Otte, Eric oth Otte, Eric oth Rakuljic, Nevena oth Rakuljic, Nevena oth Brown, Phil oth Brown, Phil oth Weigandt, Todd oth Weigandt, Todd oth Yu, Qicheng oth Yu, Qicheng oth Paterson, Donald oth Paterson, Donald oth Petersen, Corey oth Petersen, Corey oth Gealow, Jeffrey oth Gealow, Jeffrey oth Manganaro, Gabriele oth Manganaro, Gabriele oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 PP(2017), 99, Seite 1-3218 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:PP year:2017 number:99 pages:1-3218 http://dx.doi.org/10.1109/JSSC.2017.2747758 Volltext http://ieeexplore.ieee.org/document/8100718 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR PP 2017 99 1-3218
spelling	10.1109/JSSC.2017.2747758 doi PQ20171228 (DE-627)OLC1998958590 (DE-599)GBVOLC1998958590 (PRQ)i949-b37485587cb84cd12f432562da909e1b38912b7d58cbe1895ec265df02b379300 (KEY)005068422017000000000990000112b10gssinterleavedpipelineadcin28nmcmostechnology DE-627 ger DE-627 rakwb eng 620 DE-600 Devarajan, Siddharth verfasserin aut A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push-pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs. Timing pipeline ADC Calibration Clocks CMOS interleaved (IL) ADC gigahertz data conversion direct RF sampling analog-to-digital converter (ADC) Power demand Power capacitors digitally assisted analog design switched capacitor Pipelines CMOS technology Devarajan, Siddharth oth Singer, Larry oth Singer, Larry oth Kelly, Dan oth Kelly, Dan oth Pan, Tao oth Pan, Tao oth Silva, Jose oth Silva, Jose oth Brunsilius, Janet oth Brunsilius, Janet oth Rey-Losada, Daniel oth Rey-Losada, Daniel oth Murden, Frank oth Murden, Frank oth Speir, Carroll oth Speir, Carroll oth Bray, Jeffery oth Bray, Jeffery oth Otte, Eric oth Otte, Eric oth Rakuljic, Nevena oth Rakuljic, Nevena oth Brown, Phil oth Brown, Phil oth Weigandt, Todd oth Weigandt, Todd oth Yu, Qicheng oth Yu, Qicheng oth Paterson, Donald oth Paterson, Donald oth Petersen, Corey oth Petersen, Corey oth Gealow, Jeffrey oth Gealow, Jeffrey oth Manganaro, Gabriele oth Manganaro, Gabriele oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 PP(2017), 99, Seite 1-3218 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:PP year:2017 number:99 pages:1-3218 http://dx.doi.org/10.1109/JSSC.2017.2747758 Volltext http://ieeexplore.ieee.org/document/8100718 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR PP 2017 99 1-3218
allfields_unstemmed	10.1109/JSSC.2017.2747758 doi PQ20171228 (DE-627)OLC1998958590 (DE-599)GBVOLC1998958590 (PRQ)i949-b37485587cb84cd12f432562da909e1b38912b7d58cbe1895ec265df02b379300 (KEY)005068422017000000000990000112b10gssinterleavedpipelineadcin28nmcmostechnology DE-627 ger DE-627 rakwb eng 620 DE-600 Devarajan, Siddharth verfasserin aut A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push-pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs. Timing pipeline ADC Calibration Clocks CMOS interleaved (IL) ADC gigahertz data conversion direct RF sampling analog-to-digital converter (ADC) Power demand Power capacitors digitally assisted analog design switched capacitor Pipelines CMOS technology Devarajan, Siddharth oth Singer, Larry oth Singer, Larry oth Kelly, Dan oth Kelly, Dan oth Pan, Tao oth Pan, Tao oth Silva, Jose oth Silva, Jose oth Brunsilius, Janet oth Brunsilius, Janet oth Rey-Losada, Daniel oth Rey-Losada, Daniel oth Murden, Frank oth Murden, Frank oth Speir, Carroll oth Speir, Carroll oth Bray, Jeffery oth Bray, Jeffery oth Otte, Eric oth Otte, Eric oth Rakuljic, Nevena oth Rakuljic, Nevena oth Brown, Phil oth Brown, Phil oth Weigandt, Todd oth Weigandt, Todd oth Yu, Qicheng oth Yu, Qicheng oth Paterson, Donald oth Paterson, Donald oth Petersen, Corey oth Petersen, Corey oth Gealow, Jeffrey oth Gealow, Jeffrey oth Manganaro, Gabriele oth Manganaro, Gabriele oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 PP(2017), 99, Seite 1-3218 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:PP year:2017 number:99 pages:1-3218 http://dx.doi.org/10.1109/JSSC.2017.2747758 Volltext http://ieeexplore.ieee.org/document/8100718 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR PP 2017 99 1-3218
allfieldsGer	10.1109/JSSC.2017.2747758 doi PQ20171228 (DE-627)OLC1998958590 (DE-599)GBVOLC1998958590 (PRQ)i949-b37485587cb84cd12f432562da909e1b38912b7d58cbe1895ec265df02b379300 (KEY)005068422017000000000990000112b10gssinterleavedpipelineadcin28nmcmostechnology DE-627 ger DE-627 rakwb eng 620 DE-600 Devarajan, Siddharth verfasserin aut A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push-pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs. Timing pipeline ADC Calibration Clocks CMOS interleaved (IL) ADC gigahertz data conversion direct RF sampling analog-to-digital converter (ADC) Power demand Power capacitors digitally assisted analog design switched capacitor Pipelines CMOS technology Devarajan, Siddharth oth Singer, Larry oth Singer, Larry oth Kelly, Dan oth Kelly, Dan oth Pan, Tao oth Pan, Tao oth Silva, Jose oth Silva, Jose oth Brunsilius, Janet oth Brunsilius, Janet oth Rey-Losada, Daniel oth Rey-Losada, Daniel oth Murden, Frank oth Murden, Frank oth Speir, Carroll oth Speir, Carroll oth Bray, Jeffery oth Bray, Jeffery oth Otte, Eric oth Otte, Eric oth Rakuljic, Nevena oth Rakuljic, Nevena oth Brown, Phil oth Brown, Phil oth Weigandt, Todd oth Weigandt, Todd oth Yu, Qicheng oth Yu, Qicheng oth Paterson, Donald oth Paterson, Donald oth Petersen, Corey oth Petersen, Corey oth Gealow, Jeffrey oth Gealow, Jeffrey oth Manganaro, Gabriele oth Manganaro, Gabriele oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 PP(2017), 99, Seite 1-3218 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:PP year:2017 number:99 pages:1-3218 http://dx.doi.org/10.1109/JSSC.2017.2747758 Volltext http://ieeexplore.ieee.org/document/8100718 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR PP 2017 99 1-3218
allfieldsSound	10.1109/JSSC.2017.2747758 doi PQ20171228 (DE-627)OLC1998958590 (DE-599)GBVOLC1998958590 (PRQ)i949-b37485587cb84cd12f432562da909e1b38912b7d58cbe1895ec265df02b379300 (KEY)005068422017000000000990000112b10gssinterleavedpipelineadcin28nmcmostechnology DE-627 ger DE-627 rakwb eng 620 DE-600 Devarajan, Siddharth verfasserin aut A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push-pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs. Timing pipeline ADC Calibration Clocks CMOS interleaved (IL) ADC gigahertz data conversion direct RF sampling analog-to-digital converter (ADC) Power demand Power capacitors digitally assisted analog design switched capacitor Pipelines CMOS technology Devarajan, Siddharth oth Singer, Larry oth Singer, Larry oth Kelly, Dan oth Kelly, Dan oth Pan, Tao oth Pan, Tao oth Silva, Jose oth Silva, Jose oth Brunsilius, Janet oth Brunsilius, Janet oth Rey-Losada, Daniel oth Rey-Losada, Daniel oth Murden, Frank oth Murden, Frank oth Speir, Carroll oth Speir, Carroll oth Bray, Jeffery oth Bray, Jeffery oth Otte, Eric oth Otte, Eric oth Rakuljic, Nevena oth Rakuljic, Nevena oth Brown, Phil oth Brown, Phil oth Weigandt, Todd oth Weigandt, Todd oth Yu, Qicheng oth Yu, Qicheng oth Paterson, Donald oth Paterson, Donald oth Petersen, Corey oth Petersen, Corey oth Gealow, Jeffrey oth Gealow, Jeffrey oth Manganaro, Gabriele oth Manganaro, Gabriele oth Enthalten in IEEE journal of solid state circuits New York, NY : IEEE, 1966 PP(2017), 99, Seite 1-3218 (DE-627)129594865 (DE-600)240580-5 (DE-576)01508776X 0018-9200 nnns volume:PP year:2017 number:99 pages:1-3218 http://dx.doi.org/10.1109/JSSC.2017.2747758 Volltext http://ieeexplore.ieee.org/document/8100718 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_4313 AR PP 2017 99 1-3218
language	English
source	Enthalten in IEEE journal of solid state circuits PP(2017), 99, Seite 1-3218 volume:PP year:2017 number:99 pages:1-3218
sourceStr	Enthalten in IEEE journal of solid state circuits PP(2017), 99, Seite 1-3218 volume:PP year:2017 number:99 pages:1-3218
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	Timing pipeline ADC Calibration Clocks CMOS interleaved (IL) ADC gigahertz data conversion direct RF sampling analog-to-digital converter (ADC) Power demand Power capacitors digitally assisted analog design switched capacitor Pipelines CMOS technology
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authorswithroles_txt_mv	Devarajan, Siddharth @@aut@@ Devarajan, Siddharth @@oth@@ Singer, Larry @@oth@@ Kelly, Dan @@oth@@ Pan, Tao @@oth@@ Silva, Jose @@oth@@ Brunsilius, Janet @@oth@@ Rey-Losada, Daniel @@oth@@ Murden, Frank @@oth@@ Speir, Carroll @@oth@@ Bray, Jeffery @@oth@@ Otte, Eric @@oth@@ Rakuljic, Nevena @@oth@@ Brown, Phil @@oth@@ Weigandt, Todd @@oth@@ Yu, Qicheng @@oth@@ Paterson, Donald @@oth@@ Petersen, Corey @@oth@@ Gealow, Jeffrey @@oth@@ Manganaro, Gabriele @@oth@@
publishDateDaySort_date	2017-01-01T00:00:00Z
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author	Devarajan, Siddharth
spellingShingle	Devarajan, Siddharth ddc 620 misc Timing misc pipeline ADC misc Calibration misc Clocks misc CMOS misc interleaved (IL) ADC misc gigahertz data conversion misc direct RF sampling analog-to-digital converter (ADC) misc Power demand misc Power capacitors misc digitally assisted analog design misc switched capacitor misc Pipelines misc CMOS technology A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology
authorStr	Devarajan, Siddharth
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topic_title	620 DE-600 A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology Timing pipeline ADC Calibration Clocks CMOS interleaved (IL) ADC gigahertz data conversion direct RF sampling analog-to-digital converter (ADC) Power demand Power capacitors digitally assisted analog design switched capacitor Pipelines CMOS technology
topic	ddc 620 misc Timing misc pipeline ADC misc Calibration misc Clocks misc CMOS misc interleaved (IL) ADC misc gigahertz data conversion misc direct RF sampling analog-to-digital converter (ADC) misc Power demand misc Power capacitors misc digitally assisted analog design misc switched capacitor misc Pipelines misc CMOS technology
topic_unstemmed	ddc 620 misc Timing misc pipeline ADC misc Calibration misc Clocks misc CMOS misc interleaved (IL) ADC misc gigahertz data conversion misc direct RF sampling analog-to-digital converter (ADC) misc Power demand misc Power capacitors misc digitally assisted analog design misc switched capacitor misc Pipelines misc CMOS technology
topic_browse	ddc 620 misc Timing misc pipeline ADC misc Calibration misc Clocks misc CMOS misc interleaved (IL) ADC misc gigahertz data conversion misc direct RF sampling analog-to-digital converter (ADC) misc Power demand misc Power capacitors misc digitally assisted analog design misc switched capacitor misc Pipelines misc CMOS technology
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hierarchy_parent_title	IEEE journal of solid state circuits
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title	A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology
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title_full	A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology
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journal	IEEE journal of solid state circuits
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doi_str_mv	10.1109/JSSC.2017.2747758
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title_sort	12-b 10-gs/s interleaved pipeline adc in 28-nm cmos technology
title_auth	A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology
abstract	A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push-pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs.
abstractGer	A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push-pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs.
abstract_unstemmed	A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push-pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs.
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title_short	A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology
url	http://dx.doi.org/10.1109/JSSC.2017.2747758 http://ieeexplore.ieee.org/document/8100718
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author2	Devarajan, Siddharth Singer, Larry Kelly, Dan Pan, Tao Silva, Jose Brunsilius, Janet Rey-Losada, Daniel Murden, Frank Speir, Carroll Bray, Jeffery Otte, Eric Rakuljic, Nevena Brown, Phil Weigandt, Todd Yu, Qicheng Paterson, Donald Petersen, Corey Gealow, Jeffrey Manganaro, Gabriele
author2Str	Devarajan, Siddharth Singer, Larry Kelly, Dan Pan, Tao Silva, Jose Brunsilius, Janet Rey-Losada, Daniel Murden, Frank Speir, Carroll Bray, Jeffery Otte, Eric Rakuljic, Nevena Brown, Phil Weigandt, Todd Yu, Qicheng Paterson, Donald Petersen, Corey Gealow, Jeffrey Manganaro, Gabriele
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doi_str	10.1109/JSSC.2017.2747758
up_date	2024-07-04T06:04:50.077Z
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A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology

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