Low-leakage sub-threshold 9T-SRAM cell in 14-nm FinFET technology
Summary A novel sub-threshold 9T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9T-SRAM cell offers an improved access time in comparison to the 8T-SRAM cell. Furthermore, an assist circuit is proposed by which the le...
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Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2017 |
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Enthalten in: International journal of circuit theory and applications - London : Wiley, 1973, 45(2017), 11, Seite 1647 |
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| Übergeordnetes Werk: |
volume:45 ; year:2017 ; number:11 ; pages:1647 |
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10.1002/cta.2280 |
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| 520 | |a Summary A novel sub-threshold 9T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9T-SRAM cell offers an improved access time in comparison to the 8T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53MHz at VDD=270mV. Copyright © 2016 John Wiley & Sons, Ltd. | ||
| 650 | 4 | |a Leakage current | |
| 650 | 4 | |a Static random access memory | |
| 650 | 4 | |a Random access memory | |
| 650 | 4 | |a Access time | |
| 650 | 4 | |a Circuits | |
| 650 | 4 | |a Product development | |
| 650 | 4 | |a Network interface cards | |
| 700 | 0 | |a Jens Kargaard Madsen |4 oth | |
| 700 | 0 | |a Praveen Raghavan |4 oth | |
| 700 | 0 | |a Farshad Moradi |4 oth | |
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10.1002/cta.2280 doi PQ20171228 (DE-627)OLC1999149904 (DE-599)GBVOLC1999149904 (PRQ)p1172-f7e7045d134d0aeeb52b07747fba4dcaf12ba7f64746f544c4cb8cbca2a904573 (KEY)0080156920170000045001101647lowleakagesubthreshold9tsramcellin14nmfinfettechno DE-627 ger DE-627 rakwb eng 620 ZDB Behzad Zeinali verfasserin aut Low-leakage sub-threshold 9T-SRAM cell in 14-nm FinFET technology 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Summary A novel sub-threshold 9T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9T-SRAM cell offers an improved access time in comparison to the 8T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53MHz at VDD=270mV. Copyright © 2016 John Wiley & Sons, Ltd. Leakage current Static random access memory Random access memory Access time Circuits Product development Network interface cards Jens Kargaard Madsen oth Praveen Raghavan oth Farshad Moradi oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 45(2017), 11, Seite 1647 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:45 year:2017 number:11 pages:1647 http://dx.doi.org/10.1002/cta.2280 Volltext https://search.proquest.com/docview/1966282121 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 45 2017 11 1647 |
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10.1002/cta.2280 doi PQ20171228 (DE-627)OLC1999149904 (DE-599)GBVOLC1999149904 (PRQ)p1172-f7e7045d134d0aeeb52b07747fba4dcaf12ba7f64746f544c4cb8cbca2a904573 (KEY)0080156920170000045001101647lowleakagesubthreshold9tsramcellin14nmfinfettechno DE-627 ger DE-627 rakwb eng 620 ZDB Behzad Zeinali verfasserin aut Low-leakage sub-threshold 9T-SRAM cell in 14-nm FinFET technology 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Summary A novel sub-threshold 9T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9T-SRAM cell offers an improved access time in comparison to the 8T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53MHz at VDD=270mV. Copyright © 2016 John Wiley & Sons, Ltd. Leakage current Static random access memory Random access memory Access time Circuits Product development Network interface cards Jens Kargaard Madsen oth Praveen Raghavan oth Farshad Moradi oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 45(2017), 11, Seite 1647 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:45 year:2017 number:11 pages:1647 http://dx.doi.org/10.1002/cta.2280 Volltext https://search.proquest.com/docview/1966282121 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 45 2017 11 1647 |
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10.1002/cta.2280 doi PQ20171228 (DE-627)OLC1999149904 (DE-599)GBVOLC1999149904 (PRQ)p1172-f7e7045d134d0aeeb52b07747fba4dcaf12ba7f64746f544c4cb8cbca2a904573 (KEY)0080156920170000045001101647lowleakagesubthreshold9tsramcellin14nmfinfettechno DE-627 ger DE-627 rakwb eng 620 ZDB Behzad Zeinali verfasserin aut Low-leakage sub-threshold 9T-SRAM cell in 14-nm FinFET technology 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Summary A novel sub-threshold 9T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9T-SRAM cell offers an improved access time in comparison to the 8T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53MHz at VDD=270mV. Copyright © 2016 John Wiley & Sons, Ltd. Leakage current Static random access memory Random access memory Access time Circuits Product development Network interface cards Jens Kargaard Madsen oth Praveen Raghavan oth Farshad Moradi oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 45(2017), 11, Seite 1647 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:45 year:2017 number:11 pages:1647 http://dx.doi.org/10.1002/cta.2280 Volltext https://search.proquest.com/docview/1966282121 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 45 2017 11 1647 |
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10.1002/cta.2280 doi PQ20171228 (DE-627)OLC1999149904 (DE-599)GBVOLC1999149904 (PRQ)p1172-f7e7045d134d0aeeb52b07747fba4dcaf12ba7f64746f544c4cb8cbca2a904573 (KEY)0080156920170000045001101647lowleakagesubthreshold9tsramcellin14nmfinfettechno DE-627 ger DE-627 rakwb eng 620 ZDB Behzad Zeinali verfasserin aut Low-leakage sub-threshold 9T-SRAM cell in 14-nm FinFET technology 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Summary A novel sub-threshold 9T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9T-SRAM cell offers an improved access time in comparison to the 8T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53MHz at VDD=270mV. Copyright © 2016 John Wiley & Sons, Ltd. Leakage current Static random access memory Random access memory Access time Circuits Product development Network interface cards Jens Kargaard Madsen oth Praveen Raghavan oth Farshad Moradi oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 45(2017), 11, Seite 1647 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:45 year:2017 number:11 pages:1647 http://dx.doi.org/10.1002/cta.2280 Volltext https://search.proquest.com/docview/1966282121 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 45 2017 11 1647 |
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10.1002/cta.2280 doi PQ20171228 (DE-627)OLC1999149904 (DE-599)GBVOLC1999149904 (PRQ)p1172-f7e7045d134d0aeeb52b07747fba4dcaf12ba7f64746f544c4cb8cbca2a904573 (KEY)0080156920170000045001101647lowleakagesubthreshold9tsramcellin14nmfinfettechno DE-627 ger DE-627 rakwb eng 620 ZDB Behzad Zeinali verfasserin aut Low-leakage sub-threshold 9T-SRAM cell in 14-nm FinFET technology 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier Summary A novel sub-threshold 9T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9T-SRAM cell offers an improved access time in comparison to the 8T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53MHz at VDD=270mV. Copyright © 2016 John Wiley & Sons, Ltd. Leakage current Static random access memory Random access memory Access time Circuits Product development Network interface cards Jens Kargaard Madsen oth Praveen Raghavan oth Farshad Moradi oth Enthalten in International journal of circuit theory and applications London : Wiley, 1973 45(2017), 11, Seite 1647 (DE-627)129399531 (DE-600)186276-5 (DE-576)01478226X 0098-9886 nnns volume:45 year:2017 number:11 pages:1647 http://dx.doi.org/10.1002/cta.2280 Volltext https://search.proquest.com/docview/1966282121 GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 AR 45 2017 11 1647 |
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Summary A novel sub-threshold 9T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9T-SRAM cell offers an improved access time in comparison to the 8T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53MHz at VDD=270mV. Copyright © 2016 John Wiley & Sons, Ltd. |
| abstractGer |
Summary A novel sub-threshold 9T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9T-SRAM cell offers an improved access time in comparison to the 8T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53MHz at VDD=270mV. Copyright © 2016 John Wiley & Sons, Ltd. |
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Summary A novel sub-threshold 9T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9T-SRAM cell offers an improved access time in comparison to the 8T-SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding '0' and an equal leakage current during hold '1' in comparison to the 8T-SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8T-SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53MHz at VDD=270mV. Copyright © 2016 John Wiley & Sons, Ltd. |
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Low-leakage sub-threshold 9T-SRAM cell in 14-nm FinFET technology |
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http://dx.doi.org/10.1002/cta.2280 https://search.proquest.com/docview/1966282121 |
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Jens Kargaard Madsen Praveen Raghavan Farshad Moradi |
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Jens Kargaard Madsen Praveen Raghavan Farshad Moradi |
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10.1002/cta.2280 |
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2024-07-04T06:29:01.721Z |
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