Non deterministic caches: a simple and effective defense against side channel attacks
Abstract Side channel cryptanalysis has received significant attention lately, because it provides a low-cost and facile way to reveal the secret information held on a secure computing system. One particular type of side channel attacks, called cache-based side channel attacks, aims to deduce inform...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Keramidas, G. [verfasserIn] |
|---|
| Format: |
Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
2008 |
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| Schlagwörter: |
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| Anmerkung: |
© Springer Science+Business Media, LLC 2008 |
|---|
| Übergeordnetes Werk: |
Enthalten in: Design automation for embedded systems - Springer US, 1996, 12(2008), 3 vom: 26. Apr., Seite 221-230 |
|---|---|
| Übergeordnetes Werk: |
volume:12 ; year:2008 ; number:3 ; day:26 ; month:04 ; pages:221-230 |
| Links: |
|---|
| DOI / URN: |
10.1007/s10617-008-9018-y |
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OLC202705362X |
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| 520 | |a Abstract Side channel cryptanalysis has received significant attention lately, because it provides a low-cost and facile way to reveal the secret information held on a secure computing system. One particular type of side channel attacks, called cache-based side channel attacks, aims to deduce information about the state of a cryptographic algorithm or its key by observing the data-dependent behavior of a microprocessor’s cache memory. These attacks have been proven successful and very hard to protect against. In this paper, we introduce the use of the Cache Decay approach as an aid to guard against cache-based side channel attacks. Cache Decay controls the lifetime (called decay interval) of the cache items and was initially proposed for cache power leakage savings. By randomly selecting the decay interval of the cache, we actually create caches with non-deterministic behavior in regard to their statistics. Thus, as we demonstrate, multiple runs of the same algorithm (performing on the same input) will result in different cache statistics, defending against the attacker and reinforcing the protection offered by the system. In our work, we use a cycle-based processor simulator, enhanced with the required modifications, in order to evaluate our proposal and show that our technique can be used effectively to protect against cache-based side channel attacks. | ||
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| 700 | 1 | |a Serpanos, D. N. |4 aut | |
| 700 | 1 | |a Kaxiras, S. |4 aut | |
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10.1007/s10617-008-9018-y doi (DE-627)OLC202705362X (DE-He213)s10617-008-9018-y-p DE-627 ger DE-627 rakwb eng 004 690 VZ Keramidas, G. verfasserin aut Non deterministic caches: a simple and effective defense against side channel attacks 2008 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2008 Abstract Side channel cryptanalysis has received significant attention lately, because it provides a low-cost and facile way to reveal the secret information held on a secure computing system. One particular type of side channel attacks, called cache-based side channel attacks, aims to deduce information about the state of a cryptographic algorithm or its key by observing the data-dependent behavior of a microprocessor’s cache memory. These attacks have been proven successful and very hard to protect against. In this paper, we introduce the use of the Cache Decay approach as an aid to guard against cache-based side channel attacks. Cache Decay controls the lifetime (called decay interval) of the cache items and was initially proposed for cache power leakage savings. By randomly selecting the decay interval of the cache, we actually create caches with non-deterministic behavior in regard to their statistics. Thus, as we demonstrate, multiple runs of the same algorithm (performing on the same input) will result in different cache statistics, defending against the attacker and reinforcing the protection offered by the system. In our work, we use a cycle-based processor simulator, enhanced with the required modifications, in order to evaluate our proposal and show that our technique can be used effectively to protect against cache-based side channel attacks. Side channel cryptanalysis Side channel attack Cache attack Cache decay Antonopoulos, A. aut Serpanos, D. N. aut Kaxiras, S. aut Enthalten in Design automation for embedded systems Springer US, 1996 12(2008), 3 vom: 26. Apr., Seite 221-230 (DE-627)191069248 (DE-600)1293324-7 (DE-576)054257751 0929-5585 nnns volume:12 year:2008 number:3 day:26 month:04 pages:221-230 https://doi.org/10.1007/s10617-008-9018-y lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-UMW SSG-OLC-ARC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_65 GBV_ILN_70 GBV_ILN_120 GBV_ILN_2020 GBV_ILN_4307 GBV_ILN_4324 AR 12 2008 3 26 04 221-230 |
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10.1007/s10617-008-9018-y doi (DE-627)OLC202705362X (DE-He213)s10617-008-9018-y-p DE-627 ger DE-627 rakwb eng 004 690 VZ Keramidas, G. verfasserin aut Non deterministic caches: a simple and effective defense against side channel attacks 2008 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2008 Abstract Side channel cryptanalysis has received significant attention lately, because it provides a low-cost and facile way to reveal the secret information held on a secure computing system. One particular type of side channel attacks, called cache-based side channel attacks, aims to deduce information about the state of a cryptographic algorithm or its key by observing the data-dependent behavior of a microprocessor’s cache memory. These attacks have been proven successful and very hard to protect against. In this paper, we introduce the use of the Cache Decay approach as an aid to guard against cache-based side channel attacks. Cache Decay controls the lifetime (called decay interval) of the cache items and was initially proposed for cache power leakage savings. By randomly selecting the decay interval of the cache, we actually create caches with non-deterministic behavior in regard to their statistics. Thus, as we demonstrate, multiple runs of the same algorithm (performing on the same input) will result in different cache statistics, defending against the attacker and reinforcing the protection offered by the system. In our work, we use a cycle-based processor simulator, enhanced with the required modifications, in order to evaluate our proposal and show that our technique can be used effectively to protect against cache-based side channel attacks. Side channel cryptanalysis Side channel attack Cache attack Cache decay Antonopoulos, A. aut Serpanos, D. N. aut Kaxiras, S. aut Enthalten in Design automation for embedded systems Springer US, 1996 12(2008), 3 vom: 26. Apr., Seite 221-230 (DE-627)191069248 (DE-600)1293324-7 (DE-576)054257751 0929-5585 nnns volume:12 year:2008 number:3 day:26 month:04 pages:221-230 https://doi.org/10.1007/s10617-008-9018-y lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-UMW SSG-OLC-ARC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_65 GBV_ILN_70 GBV_ILN_120 GBV_ILN_2020 GBV_ILN_4307 GBV_ILN_4324 AR 12 2008 3 26 04 221-230 |
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Keramidas, G. Antonopoulos, A. Serpanos, D. N. Kaxiras, S. |
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Keramidas, G. |
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004 690 |
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non deterministic caches: a simple and effective defense against side channel attacks |
| title_auth |
Non deterministic caches: a simple and effective defense against side channel attacks |
| abstract |
Abstract Side channel cryptanalysis has received significant attention lately, because it provides a low-cost and facile way to reveal the secret information held on a secure computing system. One particular type of side channel attacks, called cache-based side channel attacks, aims to deduce information about the state of a cryptographic algorithm or its key by observing the data-dependent behavior of a microprocessor’s cache memory. These attacks have been proven successful and very hard to protect against. In this paper, we introduce the use of the Cache Decay approach as an aid to guard against cache-based side channel attacks. Cache Decay controls the lifetime (called decay interval) of the cache items and was initially proposed for cache power leakage savings. By randomly selecting the decay interval of the cache, we actually create caches with non-deterministic behavior in regard to their statistics. Thus, as we demonstrate, multiple runs of the same algorithm (performing on the same input) will result in different cache statistics, defending against the attacker and reinforcing the protection offered by the system. In our work, we use a cycle-based processor simulator, enhanced with the required modifications, in order to evaluate our proposal and show that our technique can be used effectively to protect against cache-based side channel attacks. © Springer Science+Business Media, LLC 2008 |
| abstractGer |
Abstract Side channel cryptanalysis has received significant attention lately, because it provides a low-cost and facile way to reveal the secret information held on a secure computing system. One particular type of side channel attacks, called cache-based side channel attacks, aims to deduce information about the state of a cryptographic algorithm or its key by observing the data-dependent behavior of a microprocessor’s cache memory. These attacks have been proven successful and very hard to protect against. In this paper, we introduce the use of the Cache Decay approach as an aid to guard against cache-based side channel attacks. Cache Decay controls the lifetime (called decay interval) of the cache items and was initially proposed for cache power leakage savings. By randomly selecting the decay interval of the cache, we actually create caches with non-deterministic behavior in regard to their statistics. Thus, as we demonstrate, multiple runs of the same algorithm (performing on the same input) will result in different cache statistics, defending against the attacker and reinforcing the protection offered by the system. In our work, we use a cycle-based processor simulator, enhanced with the required modifications, in order to evaluate our proposal and show that our technique can be used effectively to protect against cache-based side channel attacks. © Springer Science+Business Media, LLC 2008 |
| abstract_unstemmed |
Abstract Side channel cryptanalysis has received significant attention lately, because it provides a low-cost and facile way to reveal the secret information held on a secure computing system. One particular type of side channel attacks, called cache-based side channel attacks, aims to deduce information about the state of a cryptographic algorithm or its key by observing the data-dependent behavior of a microprocessor’s cache memory. These attacks have been proven successful and very hard to protect against. In this paper, we introduce the use of the Cache Decay approach as an aid to guard against cache-based side channel attacks. Cache Decay controls the lifetime (called decay interval) of the cache items and was initially proposed for cache power leakage savings. By randomly selecting the decay interval of the cache, we actually create caches with non-deterministic behavior in regard to their statistics. Thus, as we demonstrate, multiple runs of the same algorithm (performing on the same input) will result in different cache statistics, defending against the attacker and reinforcing the protection offered by the system. In our work, we use a cycle-based processor simulator, enhanced with the required modifications, in order to evaluate our proposal and show that our technique can be used effectively to protect against cache-based side channel attacks. © Springer Science+Business Media, LLC 2008 |
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Non deterministic caches: a simple and effective defense against side channel attacks |
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