LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM
Abstract Packet classification is an important method implemented in modern network processors used in embedded systems such as routers. Current software-based packet classification techniques exhibit low performance, prompting researchers to move their focus to architectures encompassing both softw...
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| Autor*in: |
He, Xin [verfasserIn] |
|---|
| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2010 |
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| Schlagwörter: |
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| Anmerkung: |
© Springer Science+Business Media, LLC 2010 |
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| Übergeordnetes Werk: |
Enthalten in: Design automation for embedded systems - Springer US, 1996, 14(2010), 3 vom: 16. Juli, Seite 231-263 |
|---|---|
| Übergeordnetes Werk: |
volume:14 ; year:2010 ; number:3 ; day:16 ; month:07 ; pages:231-263 |
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| DOI / URN: |
10.1007/s10617-010-9056-0 |
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| 520 | |a Abstract Packet classification is an important method implemented in modern network processors used in embedded systems such as routers. Current software-based packet classification techniques exhibit low performance, prompting researchers to move their focus to architectures encompassing both software and hardware components. Some of the newer hardware architectures exclusively utilize Ternary Content Addressable Memory (TCAM) to improve the performance of rule matching. However, this results in systems with high power consumption. In this paper, we propose LOP, a novel SRAM-based architecture where incoming packets are compared against parts of all rules simultaneously until a single matching rule is found for the compared bits in the packets. LOP significantly reduces power consumption as only a segment of the memory is compared against the incoming packet. Despite the additional time penalty to match a single packet, parallel comparison of multiple packets can improve throughput beyond that of the TCAM approaches, while consuming significantly less power. Compared with a state-of-the-art TCAM implementation (throughput of 495 Million Search per Second (Msps)) in 65 nm CMOS technology, on average, LOP saves 43% of energy consumption with a throughput of 590 Msps. In addition, an analysis of how the area scales is provided. | ||
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10.1007/s10617-010-9056-0 doi (DE-627)OLC2027053921 (DE-He213)s10617-010-9056-0-p DE-627 ger DE-627 rakwb eng 004 690 VZ He, Xin verfasserin aut LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM 2010 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2010 Abstract Packet classification is an important method implemented in modern network processors used in embedded systems such as routers. Current software-based packet classification techniques exhibit low performance, prompting researchers to move their focus to architectures encompassing both software and hardware components. Some of the newer hardware architectures exclusively utilize Ternary Content Addressable Memory (TCAM) to improve the performance of rule matching. However, this results in systems with high power consumption. In this paper, we propose LOP, a novel SRAM-based architecture where incoming packets are compared against parts of all rules simultaneously until a single matching rule is found for the compared bits in the packets. LOP significantly reduces power consumption as only a segment of the memory is compared against the incoming packet. Despite the additional time penalty to match a single packet, parallel comparison of multiple packets can improve throughput beyond that of the TCAM approaches, while consuming significantly less power. Compared with a state-of-the-art TCAM implementation (throughput of 495 Million Search per Second (Msps)) in 65 nm CMOS technology, on average, LOP saves 43% of energy consumption with a throughput of 590 Msps. In addition, an analysis of how the area scales is provided. Packet classification Low-power Hardware design Peddersen, Jorgen aut Parameswaran, Sri aut Enthalten in Design automation for embedded systems Springer US, 1996 14(2010), 3 vom: 16. Juli, Seite 231-263 (DE-627)191069248 (DE-600)1293324-7 (DE-576)054257751 0929-5585 nnns volume:14 year:2010 number:3 day:16 month:07 pages:231-263 https://doi.org/10.1007/s10617-010-9056-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-UMW SSG-OLC-ARC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_65 GBV_ILN_70 GBV_ILN_120 GBV_ILN_2020 GBV_ILN_4307 AR 14 2010 3 16 07 231-263 |
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10.1007/s10617-010-9056-0 doi (DE-627)OLC2027053921 (DE-He213)s10617-010-9056-0-p DE-627 ger DE-627 rakwb eng 004 690 VZ He, Xin verfasserin aut LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM 2010 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2010 Abstract Packet classification is an important method implemented in modern network processors used in embedded systems such as routers. Current software-based packet classification techniques exhibit low performance, prompting researchers to move their focus to architectures encompassing both software and hardware components. Some of the newer hardware architectures exclusively utilize Ternary Content Addressable Memory (TCAM) to improve the performance of rule matching. However, this results in systems with high power consumption. In this paper, we propose LOP, a novel SRAM-based architecture where incoming packets are compared against parts of all rules simultaneously until a single matching rule is found for the compared bits in the packets. LOP significantly reduces power consumption as only a segment of the memory is compared against the incoming packet. Despite the additional time penalty to match a single packet, parallel comparison of multiple packets can improve throughput beyond that of the TCAM approaches, while consuming significantly less power. Compared with a state-of-the-art TCAM implementation (throughput of 495 Million Search per Second (Msps)) in 65 nm CMOS technology, on average, LOP saves 43% of energy consumption with a throughput of 590 Msps. In addition, an analysis of how the area scales is provided. Packet classification Low-power Hardware design Peddersen, Jorgen aut Parameswaran, Sri aut Enthalten in Design automation for embedded systems Springer US, 1996 14(2010), 3 vom: 16. Juli, Seite 231-263 (DE-627)191069248 (DE-600)1293324-7 (DE-576)054257751 0929-5585 nnns volume:14 year:2010 number:3 day:16 month:07 pages:231-263 https://doi.org/10.1007/s10617-010-9056-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-UMW SSG-OLC-ARC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_65 GBV_ILN_70 GBV_ILN_120 GBV_ILN_2020 GBV_ILN_4307 AR 14 2010 3 16 07 231-263 |
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10.1007/s10617-010-9056-0 doi (DE-627)OLC2027053921 (DE-He213)s10617-010-9056-0-p DE-627 ger DE-627 rakwb eng 004 690 VZ He, Xin verfasserin aut LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM 2010 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2010 Abstract Packet classification is an important method implemented in modern network processors used in embedded systems such as routers. Current software-based packet classification techniques exhibit low performance, prompting researchers to move their focus to architectures encompassing both software and hardware components. Some of the newer hardware architectures exclusively utilize Ternary Content Addressable Memory (TCAM) to improve the performance of rule matching. However, this results in systems with high power consumption. In this paper, we propose LOP, a novel SRAM-based architecture where incoming packets are compared against parts of all rules simultaneously until a single matching rule is found for the compared bits in the packets. LOP significantly reduces power consumption as only a segment of the memory is compared against the incoming packet. Despite the additional time penalty to match a single packet, parallel comparison of multiple packets can improve throughput beyond that of the TCAM approaches, while consuming significantly less power. Compared with a state-of-the-art TCAM implementation (throughput of 495 Million Search per Second (Msps)) in 65 nm CMOS technology, on average, LOP saves 43% of energy consumption with a throughput of 590 Msps. In addition, an analysis of how the area scales is provided. Packet classification Low-power Hardware design Peddersen, Jorgen aut Parameswaran, Sri aut Enthalten in Design automation for embedded systems Springer US, 1996 14(2010), 3 vom: 16. Juli, Seite 231-263 (DE-627)191069248 (DE-600)1293324-7 (DE-576)054257751 0929-5585 nnns volume:14 year:2010 number:3 day:16 month:07 pages:231-263 https://doi.org/10.1007/s10617-010-9056-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-UMW SSG-OLC-ARC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_65 GBV_ILN_70 GBV_ILN_120 GBV_ILN_2020 GBV_ILN_4307 AR 14 2010 3 16 07 231-263 |
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LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM |
| abstract |
Abstract Packet classification is an important method implemented in modern network processors used in embedded systems such as routers. Current software-based packet classification techniques exhibit low performance, prompting researchers to move their focus to architectures encompassing both software and hardware components. Some of the newer hardware architectures exclusively utilize Ternary Content Addressable Memory (TCAM) to improve the performance of rule matching. However, this results in systems with high power consumption. In this paper, we propose LOP, a novel SRAM-based architecture where incoming packets are compared against parts of all rules simultaneously until a single matching rule is found for the compared bits in the packets. LOP significantly reduces power consumption as only a segment of the memory is compared against the incoming packet. Despite the additional time penalty to match a single packet, parallel comparison of multiple packets can improve throughput beyond that of the TCAM approaches, while consuming significantly less power. Compared with a state-of-the-art TCAM implementation (throughput of 495 Million Search per Second (Msps)) in 65 nm CMOS technology, on average, LOP saves 43% of energy consumption with a throughput of 590 Msps. In addition, an analysis of how the area scales is provided. © Springer Science+Business Media, LLC 2010 |
| abstractGer |
Abstract Packet classification is an important method implemented in modern network processors used in embedded systems such as routers. Current software-based packet classification techniques exhibit low performance, prompting researchers to move their focus to architectures encompassing both software and hardware components. Some of the newer hardware architectures exclusively utilize Ternary Content Addressable Memory (TCAM) to improve the performance of rule matching. However, this results in systems with high power consumption. In this paper, we propose LOP, a novel SRAM-based architecture where incoming packets are compared against parts of all rules simultaneously until a single matching rule is found for the compared bits in the packets. LOP significantly reduces power consumption as only a segment of the memory is compared against the incoming packet. Despite the additional time penalty to match a single packet, parallel comparison of multiple packets can improve throughput beyond that of the TCAM approaches, while consuming significantly less power. Compared with a state-of-the-art TCAM implementation (throughput of 495 Million Search per Second (Msps)) in 65 nm CMOS technology, on average, LOP saves 43% of energy consumption with a throughput of 590 Msps. In addition, an analysis of how the area scales is provided. © Springer Science+Business Media, LLC 2010 |
| abstract_unstemmed |
Abstract Packet classification is an important method implemented in modern network processors used in embedded systems such as routers. Current software-based packet classification techniques exhibit low performance, prompting researchers to move their focus to architectures encompassing both software and hardware components. Some of the newer hardware architectures exclusively utilize Ternary Content Addressable Memory (TCAM) to improve the performance of rule matching. However, this results in systems with high power consumption. In this paper, we propose LOP, a novel SRAM-based architecture where incoming packets are compared against parts of all rules simultaneously until a single matching rule is found for the compared bits in the packets. LOP significantly reduces power consumption as only a segment of the memory is compared against the incoming packet. Despite the additional time penalty to match a single packet, parallel comparison of multiple packets can improve throughput beyond that of the TCAM approaches, while consuming significantly less power. Compared with a state-of-the-art TCAM implementation (throughput of 495 Million Search per Second (Msps)) in 65 nm CMOS technology, on average, LOP saves 43% of energy consumption with a throughput of 590 Msps. In addition, an analysis of how the area scales is provided. © Springer Science+Business Media, LLC 2010 |
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| container_issue |
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| title_short |
LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM |
| url |
https://doi.org/10.1007/s10617-010-9056-0 |
| remote_bool |
false |
| author2 |
Peddersen, Jorgen Parameswaran, Sri |
| author2Str |
Peddersen, Jorgen Parameswaran, Sri |
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| doi_str |
10.1007/s10617-010-9056-0 |
| up_date |
2024-07-03T13:35:34.526Z |
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7.4004087 |