Towards closing the specification gap by integrating algorithm-level and system-level design
Abstract Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely...
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| Autor*in: |
Zhang, Jiaxing [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2015 |
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| Schlagwörter: |
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| Anmerkung: |
© Springer Science+Business Media New York 2015 |
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| Übergeordnetes Werk: |
Enthalten in: Design automation for embedded systems - Springer US, 1996, 19(2015), 4 vom: 17. Apr., Seite 389-419 |
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| Übergeordnetes Werk: |
volume:19 ; year:2015 ; number:4 ; day:17 ; month:04 ; pages:389-419 |
| Links: |
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| DOI / URN: |
10.1007/s10617-015-9161-1 |
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| Katalog-ID: |
OLC2027054928 |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | OLC2027054928 | ||
| 003 | DE-627 | ||
| 005 | 20230503034646.0 | ||
| 007 | tu | ||
| 008 | 200819s2015 xx ||||| 00| ||eng c | ||
| 024 | 7 | |a 10.1007/s10617-015-9161-1 |2 doi | |
| 035 | |a (DE-627)OLC2027054928 | ||
| 035 | |a (DE-He213)s10617-015-9161-1-p | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 082 | 0 | 4 | |a 004 |a 690 |q VZ |
| 100 | 1 | |a Zhang, Jiaxing |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a Towards closing the specification gap by integrating algorithm-level and system-level design |
| 264 | 1 | |c 2015 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a ohne Hilfsmittel zu benutzen |b n |2 rdamedia | ||
| 338 | |a Band |b nc |2 rdacarrier | ||
| 500 | |a © Springer Science+Business Media New York 2015 | ||
| 520 | |a Abstract Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models. | ||
| 650 | 4 | |a Specification synthesis | |
| 650 | 4 | |a Simulink | |
| 650 | 4 | |a MPSoC design methodology | |
| 650 | 4 | |a Design space exploration | |
| 650 | 4 | |a Algorithm-Architecture co-design | |
| 700 | 1 | |a Schirner, Gunar |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t Design automation for embedded systems |d Springer US, 1996 |g 19(2015), 4 vom: 17. Apr., Seite 389-419 |w (DE-627)191069248 |w (DE-600)1293324-7 |w (DE-576)054257751 |x 0929-5585 |7 nnns |
| 773 | 1 | 8 | |g volume:19 |g year:2015 |g number:4 |g day:17 |g month:04 |g pages:389-419 |
| 856 | 4 | 1 | |u https://doi.org/10.1007/s10617-015-9161-1 |z lizenzpflichtig |3 Volltext |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_OLC | ||
| 912 | |a SSG-OLC-UMW | ||
| 912 | |a SSG-OLC-ARC | ||
| 912 | |a SSG-OLC-TEC | ||
| 912 | |a SSG-OLC-MAT | ||
| 912 | |a GBV_ILN_70 | ||
| 951 | |a AR | ||
| 952 | |d 19 |j 2015 |e 4 |b 17 |c 04 |h 389-419 | ||
| author_variant |
j z jz g s gs |
|---|---|
| matchkey_str |
article:09295585:2015----::oadcoighseiiainabitgaigloihlvl |
| hierarchy_sort_str |
2015 |
| publishDate |
2015 |
| allfields |
10.1007/s10617-015-9161-1 doi (DE-627)OLC2027054928 (DE-He213)s10617-015-9161-1-p DE-627 ger DE-627 rakwb eng 004 690 VZ Zhang, Jiaxing verfasserin aut Towards closing the specification gap by integrating algorithm-level and system-level design 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media New York 2015 Abstract Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models. Specification synthesis Simulink MPSoC design methodology Design space exploration Algorithm-Architecture co-design Schirner, Gunar aut Enthalten in Design automation for embedded systems Springer US, 1996 19(2015), 4 vom: 17. Apr., Seite 389-419 (DE-627)191069248 (DE-600)1293324-7 (DE-576)054257751 0929-5585 nnns volume:19 year:2015 number:4 day:17 month:04 pages:389-419 https://doi.org/10.1007/s10617-015-9161-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-UMW SSG-OLC-ARC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 AR 19 2015 4 17 04 389-419 |
| spelling |
10.1007/s10617-015-9161-1 doi (DE-627)OLC2027054928 (DE-He213)s10617-015-9161-1-p DE-627 ger DE-627 rakwb eng 004 690 VZ Zhang, Jiaxing verfasserin aut Towards closing the specification gap by integrating algorithm-level and system-level design 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media New York 2015 Abstract Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models. Specification synthesis Simulink MPSoC design methodology Design space exploration Algorithm-Architecture co-design Schirner, Gunar aut Enthalten in Design automation for embedded systems Springer US, 1996 19(2015), 4 vom: 17. Apr., Seite 389-419 (DE-627)191069248 (DE-600)1293324-7 (DE-576)054257751 0929-5585 nnns volume:19 year:2015 number:4 day:17 month:04 pages:389-419 https://doi.org/10.1007/s10617-015-9161-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-UMW SSG-OLC-ARC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 AR 19 2015 4 17 04 389-419 |
| allfields_unstemmed |
10.1007/s10617-015-9161-1 doi (DE-627)OLC2027054928 (DE-He213)s10617-015-9161-1-p DE-627 ger DE-627 rakwb eng 004 690 VZ Zhang, Jiaxing verfasserin aut Towards closing the specification gap by integrating algorithm-level and system-level design 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media New York 2015 Abstract Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models. Specification synthesis Simulink MPSoC design methodology Design space exploration Algorithm-Architecture co-design Schirner, Gunar aut Enthalten in Design automation for embedded systems Springer US, 1996 19(2015), 4 vom: 17. Apr., Seite 389-419 (DE-627)191069248 (DE-600)1293324-7 (DE-576)054257751 0929-5585 nnns volume:19 year:2015 number:4 day:17 month:04 pages:389-419 https://doi.org/10.1007/s10617-015-9161-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-UMW SSG-OLC-ARC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 AR 19 2015 4 17 04 389-419 |
| allfieldsGer |
10.1007/s10617-015-9161-1 doi (DE-627)OLC2027054928 (DE-He213)s10617-015-9161-1-p DE-627 ger DE-627 rakwb eng 004 690 VZ Zhang, Jiaxing verfasserin aut Towards closing the specification gap by integrating algorithm-level and system-level design 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media New York 2015 Abstract Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models. Specification synthesis Simulink MPSoC design methodology Design space exploration Algorithm-Architecture co-design Schirner, Gunar aut Enthalten in Design automation for embedded systems Springer US, 1996 19(2015), 4 vom: 17. Apr., Seite 389-419 (DE-627)191069248 (DE-600)1293324-7 (DE-576)054257751 0929-5585 nnns volume:19 year:2015 number:4 day:17 month:04 pages:389-419 https://doi.org/10.1007/s10617-015-9161-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-UMW SSG-OLC-ARC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 AR 19 2015 4 17 04 389-419 |
| allfieldsSound |
10.1007/s10617-015-9161-1 doi (DE-627)OLC2027054928 (DE-He213)s10617-015-9161-1-p DE-627 ger DE-627 rakwb eng 004 690 VZ Zhang, Jiaxing verfasserin aut Towards closing the specification gap by integrating algorithm-level and system-level design 2015 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media New York 2015 Abstract Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models. Specification synthesis Simulink MPSoC design methodology Design space exploration Algorithm-Architecture co-design Schirner, Gunar aut Enthalten in Design automation for embedded systems Springer US, 1996 19(2015), 4 vom: 17. Apr., Seite 389-419 (DE-627)191069248 (DE-600)1293324-7 (DE-576)054257751 0929-5585 nnns volume:19 year:2015 number:4 day:17 month:04 pages:389-419 https://doi.org/10.1007/s10617-015-9161-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-UMW SSG-OLC-ARC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 AR 19 2015 4 17 04 389-419 |
| language |
English |
| source |
Enthalten in Design automation for embedded systems 19(2015), 4 vom: 17. Apr., Seite 389-419 volume:19 year:2015 number:4 day:17 month:04 pages:389-419 |
| sourceStr |
Enthalten in Design automation for embedded systems 19(2015), 4 vom: 17. Apr., Seite 389-419 volume:19 year:2015 number:4 day:17 month:04 pages:389-419 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Specification synthesis Simulink MPSoC design methodology Design space exploration Algorithm-Architecture co-design |
| dewey-raw |
004 |
| isfreeaccess_bool |
false |
| container_title |
Design automation for embedded systems |
| authorswithroles_txt_mv |
Zhang, Jiaxing @@aut@@ Schirner, Gunar @@aut@@ |
| publishDateDaySort_date |
2015-04-17T00:00:00Z |
| hierarchy_top_id |
191069248 |
| dewey-sort |
14 |
| id |
OLC2027054928 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">OLC2027054928</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230503034646.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">200819s2015 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s10617-015-9161-1</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC2027054928</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-He213)s10617-015-9161-1-p</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">004</subfield><subfield code="a">690</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Zhang, Jiaxing</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Towards closing the specification gap by integrating algorithm-level and system-level design</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2015</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© Springer Science+Business Media New York 2015</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Specification synthesis</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Simulink</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">MPSoC design methodology</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Design space exploration</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Algorithm-Architecture co-design</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Schirner, Gunar</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Design automation for embedded systems</subfield><subfield code="d">Springer US, 1996</subfield><subfield code="g">19(2015), 4 vom: 17. Apr., Seite 389-419</subfield><subfield code="w">(DE-627)191069248</subfield><subfield code="w">(DE-600)1293324-7</subfield><subfield code="w">(DE-576)054257751</subfield><subfield code="x">0929-5585</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:19</subfield><subfield code="g">year:2015</subfield><subfield code="g">number:4</subfield><subfield code="g">day:17</subfield><subfield code="g">month:04</subfield><subfield code="g">pages:389-419</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">https://doi.org/10.1007/s10617-015-9161-1</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-UMW</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-ARC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-MAT</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">19</subfield><subfield code="j">2015</subfield><subfield code="e">4</subfield><subfield code="b">17</subfield><subfield code="c">04</subfield><subfield code="h">389-419</subfield></datafield></record></collection>
|
| author |
Zhang, Jiaxing |
| spellingShingle |
Zhang, Jiaxing ddc 004 misc Specification synthesis misc Simulink misc MPSoC design methodology misc Design space exploration misc Algorithm-Architecture co-design Towards closing the specification gap by integrating algorithm-level and system-level design |
| authorStr |
Zhang, Jiaxing |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)191069248 |
| format |
Article |
| dewey-ones |
004 - Data processing & computer science 690 - Buildings |
| delete_txt_mv |
keep |
| author_role |
aut aut |
| collection |
OLC |
| remote_str |
false |
| illustrated |
Not Illustrated |
| issn |
0929-5585 |
| topic_title |
004 690 VZ Towards closing the specification gap by integrating algorithm-level and system-level design Specification synthesis Simulink MPSoC design methodology Design space exploration Algorithm-Architecture co-design |
| topic |
ddc 004 misc Specification synthesis misc Simulink misc MPSoC design methodology misc Design space exploration misc Algorithm-Architecture co-design |
| topic_unstemmed |
ddc 004 misc Specification synthesis misc Simulink misc MPSoC design methodology misc Design space exploration misc Algorithm-Architecture co-design |
| topic_browse |
ddc 004 misc Specification synthesis misc Simulink misc MPSoC design methodology misc Design space exploration misc Algorithm-Architecture co-design |
| format_facet |
Aufsätze Gedruckte Aufsätze |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
nc |
| hierarchy_parent_title |
Design automation for embedded systems |
| hierarchy_parent_id |
191069248 |
| dewey-tens |
000 - Computer science, knowledge & systems 690 - Building & construction |
| hierarchy_top_title |
Design automation for embedded systems |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)191069248 (DE-600)1293324-7 (DE-576)054257751 |
| title |
Towards closing the specification gap by integrating algorithm-level and system-level design |
| ctrlnum |
(DE-627)OLC2027054928 (DE-He213)s10617-015-9161-1-p |
| title_full |
Towards closing the specification gap by integrating algorithm-level and system-level design |
| author_sort |
Zhang, Jiaxing |
| journal |
Design automation for embedded systems |
| journalStr |
Design automation for embedded systems |
| lang_code |
eng |
| isOA_bool |
false |
| dewey-hundreds |
000 - Computer science, information & general works 600 - Technology |
| recordtype |
marc |
| publishDateSort |
2015 |
| contenttype_str_mv |
txt |
| container_start_page |
389 |
| author_browse |
Zhang, Jiaxing Schirner, Gunar |
| container_volume |
19 |
| class |
004 690 VZ |
| format_se |
Aufsätze |
| author-letter |
Zhang, Jiaxing |
| doi_str_mv |
10.1007/s10617-015-9161-1 |
| dewey-full |
004 690 |
| title_sort |
towards closing the specification gap by integrating algorithm-level and system-level design |
| title_auth |
Towards closing the specification gap by integrating algorithm-level and system-level design |
| abstract |
Abstract Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models. © Springer Science+Business Media New York 2015 |
| abstractGer |
Abstract Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models. © Springer Science+Business Media New York 2015 |
| abstract_unstemmed |
Abstract Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models. © Springer Science+Business Media New York 2015 |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-UMW SSG-OLC-ARC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 |
| container_issue |
4 |
| title_short |
Towards closing the specification gap by integrating algorithm-level and system-level design |
| url |
https://doi.org/10.1007/s10617-015-9161-1 |
| remote_bool |
false |
| author2 |
Schirner, Gunar |
| author2Str |
Schirner, Gunar |
| ppnlink |
191069248 |
| mediatype_str_mv |
n |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| doi_str |
10.1007/s10617-015-9161-1 |
| up_date |
2024-07-03T13:35:51.723Z |
| _version_ |
1803565139725647872 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">OLC2027054928</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230503034646.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">200819s2015 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s10617-015-9161-1</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC2027054928</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-He213)s10617-015-9161-1-p</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">004</subfield><subfield code="a">690</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Zhang, Jiaxing</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Towards closing the specification gap by integrating algorithm-level and system-level design</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2015</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© Springer Science+Business Media New York 2015</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Specification synthesis</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Simulink</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">MPSoC design methodology</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Design space exploration</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Algorithm-Architecture co-design</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Schirner, Gunar</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Design automation for embedded systems</subfield><subfield code="d">Springer US, 1996</subfield><subfield code="g">19(2015), 4 vom: 17. Apr., Seite 389-419</subfield><subfield code="w">(DE-627)191069248</subfield><subfield code="w">(DE-600)1293324-7</subfield><subfield code="w">(DE-576)054257751</subfield><subfield code="x">0929-5585</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:19</subfield><subfield code="g">year:2015</subfield><subfield code="g">number:4</subfield><subfield code="g">day:17</subfield><subfield code="g">month:04</subfield><subfield code="g">pages:389-419</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">https://doi.org/10.1007/s10617-015-9161-1</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-UMW</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-ARC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-MAT</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">19</subfield><subfield code="j">2015</subfield><subfield code="e">4</subfield><subfield code="b">17</subfield><subfield code="c">04</subfield><subfield code="h">389-419</subfield></datafield></record></collection>
|
| score |
7.3981 |