Exploring the performance limits of simultaneous multithreading for memory intensive applications
Abstract Simultaneous multithreading (SMT) has been proposed to improve system throughput by overlapping instructions from multiple threads on a single wide-issue processor. Recent studies have demonstrated that diversity of simultaneously executed applications can bring up significant performance g...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Athanasaki, Evangelia [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2007 |
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| Schlagwörter: |
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| Anmerkung: |
© Springer Science+Business Media, LLC 2007 |
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| Übergeordnetes Werk: |
Enthalten in: The journal of supercomputing - Springer US, 1987, 44(2007), 1 vom: 06. Okt., Seite 64-97 |
|---|---|
| Übergeordnetes Werk: |
volume:44 ; year:2007 ; number:1 ; day:06 ; month:10 ; pages:64-97 |
| Links: |
|---|
| DOI / URN: |
10.1007/s11227-007-0149-x |
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OLC203393537X |
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| 520 | |a Abstract Simultaneous multithreading (SMT) has been proposed to improve system throughput by overlapping instructions from multiple threads on a single wide-issue processor. Recent studies have demonstrated that diversity of simultaneously executed applications can bring up significant performance gains due to SMT. However, the speedup of a single application that is parallelized into multiple threads, is often sensitive to its inherent instruction level parallelism (ILP), as well as the efficiency of synchronization and communication mechanisms between its separate, but possibly dependent threads. Moreover, as these separate threads tend to put pressure on the same architectural resources, no significant speedup can be observed. In this paper, we evaluate and contrast thread-level parallelism (TLP) and speculative precomputation (SPR) techniques for a series of memory intensive codes executed on a specific SMT processor implementation. We explore the performance limits by evaluating the tradeoffs between ILP and TLP for various kinds of instruction streams. By obtaining knowledge on how such streams interact when executed simultaneously on the processor, and quantifying their presence within each application’s threads, we try to interpret the observed performance for each application when parallelized according to the aforementioned techniques. In order to amplify this evaluation process, we also present results gathered from the performance monitoring hardware of the processor. | ||
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10.1007/s11227-007-0149-x doi (DE-627)OLC203393537X (DE-He213)s11227-007-0149-x-p DE-627 ger DE-627 rakwb eng 004 620 VZ Athanasaki, Evangelia verfasserin aut Exploring the performance limits of simultaneous multithreading for memory intensive applications 2007 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2007 Abstract Simultaneous multithreading (SMT) has been proposed to improve system throughput by overlapping instructions from multiple threads on a single wide-issue processor. Recent studies have demonstrated that diversity of simultaneously executed applications can bring up significant performance gains due to SMT. However, the speedup of a single application that is parallelized into multiple threads, is often sensitive to its inherent instruction level parallelism (ILP), as well as the efficiency of synchronization and communication mechanisms between its separate, but possibly dependent threads. Moreover, as these separate threads tend to put pressure on the same architectural resources, no significant speedup can be observed. In this paper, we evaluate and contrast thread-level parallelism (TLP) and speculative precomputation (SPR) techniques for a series of memory intensive codes executed on a specific SMT processor implementation. We explore the performance limits by evaluating the tradeoffs between ILP and TLP for various kinds of instruction streams. By obtaining knowledge on how such streams interact when executed simultaneously on the processor, and quantifying their presence within each application’s threads, we try to interpret the observed performance for each application when parallelized according to the aforementioned techniques. In order to amplify this evaluation process, we also present results gathered from the performance monitoring hardware of the processor. Simultaneous multithreading Thread-level parallelism Instruction-level parallelism Software prefetching Speculative precomputation Performance analysis Anastopoulos, Nikos aut Kourtis, Kornilios aut Koziris, Nectarios aut Enthalten in The journal of supercomputing Springer US, 1987 44(2007), 1 vom: 06. Okt., Seite 64-97 (DE-627)13046466X (DE-600)740510-8 (DE-576)018667775 0920-8542 nnns volume:44 year:2007 number:1 day:06 month:10 pages:64-97 https://doi.org/10.1007/s11227-007-0149-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_62 GBV_ILN_70 GBV_ILN_2010 GBV_ILN_4307 GBV_ILN_4324 AR 44 2007 1 06 10 64-97 |
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10.1007/s11227-007-0149-x doi (DE-627)OLC203393537X (DE-He213)s11227-007-0149-x-p DE-627 ger DE-627 rakwb eng 004 620 VZ Athanasaki, Evangelia verfasserin aut Exploring the performance limits of simultaneous multithreading for memory intensive applications 2007 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2007 Abstract Simultaneous multithreading (SMT) has been proposed to improve system throughput by overlapping instructions from multiple threads on a single wide-issue processor. Recent studies have demonstrated that diversity of simultaneously executed applications can bring up significant performance gains due to SMT. However, the speedup of a single application that is parallelized into multiple threads, is often sensitive to its inherent instruction level parallelism (ILP), as well as the efficiency of synchronization and communication mechanisms between its separate, but possibly dependent threads. Moreover, as these separate threads tend to put pressure on the same architectural resources, no significant speedup can be observed. In this paper, we evaluate and contrast thread-level parallelism (TLP) and speculative precomputation (SPR) techniques for a series of memory intensive codes executed on a specific SMT processor implementation. We explore the performance limits by evaluating the tradeoffs between ILP and TLP for various kinds of instruction streams. By obtaining knowledge on how such streams interact when executed simultaneously on the processor, and quantifying their presence within each application’s threads, we try to interpret the observed performance for each application when parallelized according to the aforementioned techniques. In order to amplify this evaluation process, we also present results gathered from the performance monitoring hardware of the processor. Simultaneous multithreading Thread-level parallelism Instruction-level parallelism Software prefetching Speculative precomputation Performance analysis Anastopoulos, Nikos aut Kourtis, Kornilios aut Koziris, Nectarios aut Enthalten in The journal of supercomputing Springer US, 1987 44(2007), 1 vom: 06. Okt., Seite 64-97 (DE-627)13046466X (DE-600)740510-8 (DE-576)018667775 0920-8542 nnns volume:44 year:2007 number:1 day:06 month:10 pages:64-97 https://doi.org/10.1007/s11227-007-0149-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_62 GBV_ILN_70 GBV_ILN_2010 GBV_ILN_4307 GBV_ILN_4324 AR 44 2007 1 06 10 64-97 |
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10.1007/s11227-007-0149-x doi (DE-627)OLC203393537X (DE-He213)s11227-007-0149-x-p DE-627 ger DE-627 rakwb eng 004 620 VZ Athanasaki, Evangelia verfasserin aut Exploring the performance limits of simultaneous multithreading for memory intensive applications 2007 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2007 Abstract Simultaneous multithreading (SMT) has been proposed to improve system throughput by overlapping instructions from multiple threads on a single wide-issue processor. Recent studies have demonstrated that diversity of simultaneously executed applications can bring up significant performance gains due to SMT. However, the speedup of a single application that is parallelized into multiple threads, is often sensitive to its inherent instruction level parallelism (ILP), as well as the efficiency of synchronization and communication mechanisms between its separate, but possibly dependent threads. Moreover, as these separate threads tend to put pressure on the same architectural resources, no significant speedup can be observed. In this paper, we evaluate and contrast thread-level parallelism (TLP) and speculative precomputation (SPR) techniques for a series of memory intensive codes executed on a specific SMT processor implementation. We explore the performance limits by evaluating the tradeoffs between ILP and TLP for various kinds of instruction streams. By obtaining knowledge on how such streams interact when executed simultaneously on the processor, and quantifying their presence within each application’s threads, we try to interpret the observed performance for each application when parallelized according to the aforementioned techniques. In order to amplify this evaluation process, we also present results gathered from the performance monitoring hardware of the processor. Simultaneous multithreading Thread-level parallelism Instruction-level parallelism Software prefetching Speculative precomputation Performance analysis Anastopoulos, Nikos aut Kourtis, Kornilios aut Koziris, Nectarios aut Enthalten in The journal of supercomputing Springer US, 1987 44(2007), 1 vom: 06. Okt., Seite 64-97 (DE-627)13046466X (DE-600)740510-8 (DE-576)018667775 0920-8542 nnns volume:44 year:2007 number:1 day:06 month:10 pages:64-97 https://doi.org/10.1007/s11227-007-0149-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_62 GBV_ILN_70 GBV_ILN_2010 GBV_ILN_4307 GBV_ILN_4324 AR 44 2007 1 06 10 64-97 |
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10.1007/s11227-007-0149-x doi (DE-627)OLC203393537X (DE-He213)s11227-007-0149-x-p DE-627 ger DE-627 rakwb eng 004 620 VZ Athanasaki, Evangelia verfasserin aut Exploring the performance limits of simultaneous multithreading for memory intensive applications 2007 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2007 Abstract Simultaneous multithreading (SMT) has been proposed to improve system throughput by overlapping instructions from multiple threads on a single wide-issue processor. Recent studies have demonstrated that diversity of simultaneously executed applications can bring up significant performance gains due to SMT. However, the speedup of a single application that is parallelized into multiple threads, is often sensitive to its inherent instruction level parallelism (ILP), as well as the efficiency of synchronization and communication mechanisms between its separate, but possibly dependent threads. Moreover, as these separate threads tend to put pressure on the same architectural resources, no significant speedup can be observed. In this paper, we evaluate and contrast thread-level parallelism (TLP) and speculative precomputation (SPR) techniques for a series of memory intensive codes executed on a specific SMT processor implementation. We explore the performance limits by evaluating the tradeoffs between ILP and TLP for various kinds of instruction streams. By obtaining knowledge on how such streams interact when executed simultaneously on the processor, and quantifying their presence within each application’s threads, we try to interpret the observed performance for each application when parallelized according to the aforementioned techniques. In order to amplify this evaluation process, we also present results gathered from the performance monitoring hardware of the processor. Simultaneous multithreading Thread-level parallelism Instruction-level parallelism Software prefetching Speculative precomputation Performance analysis Anastopoulos, Nikos aut Kourtis, Kornilios aut Koziris, Nectarios aut Enthalten in The journal of supercomputing Springer US, 1987 44(2007), 1 vom: 06. Okt., Seite 64-97 (DE-627)13046466X (DE-600)740510-8 (DE-576)018667775 0920-8542 nnns volume:44 year:2007 number:1 day:06 month:10 pages:64-97 https://doi.org/10.1007/s11227-007-0149-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_62 GBV_ILN_70 GBV_ILN_2010 GBV_ILN_4307 GBV_ILN_4324 AR 44 2007 1 06 10 64-97 |
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Athanasaki, Evangelia |
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The journal of supercomputing |
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The journal of supercomputing |
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2007 |
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Athanasaki, Evangelia Anastopoulos, Nikos Kourtis, Kornilios Koziris, Nectarios |
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Athanasaki, Evangelia |
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10.1007/s11227-007-0149-x |
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004 620 |
| title_sort |
exploring the performance limits of simultaneous multithreading for memory intensive applications |
| title_auth |
Exploring the performance limits of simultaneous multithreading for memory intensive applications |
| abstract |
Abstract Simultaneous multithreading (SMT) has been proposed to improve system throughput by overlapping instructions from multiple threads on a single wide-issue processor. Recent studies have demonstrated that diversity of simultaneously executed applications can bring up significant performance gains due to SMT. However, the speedup of a single application that is parallelized into multiple threads, is often sensitive to its inherent instruction level parallelism (ILP), as well as the efficiency of synchronization and communication mechanisms between its separate, but possibly dependent threads. Moreover, as these separate threads tend to put pressure on the same architectural resources, no significant speedup can be observed. In this paper, we evaluate and contrast thread-level parallelism (TLP) and speculative precomputation (SPR) techniques for a series of memory intensive codes executed on a specific SMT processor implementation. We explore the performance limits by evaluating the tradeoffs between ILP and TLP for various kinds of instruction streams. By obtaining knowledge on how such streams interact when executed simultaneously on the processor, and quantifying their presence within each application’s threads, we try to interpret the observed performance for each application when parallelized according to the aforementioned techniques. In order to amplify this evaluation process, we also present results gathered from the performance monitoring hardware of the processor. © Springer Science+Business Media, LLC 2007 |
| abstractGer |
Abstract Simultaneous multithreading (SMT) has been proposed to improve system throughput by overlapping instructions from multiple threads on a single wide-issue processor. Recent studies have demonstrated that diversity of simultaneously executed applications can bring up significant performance gains due to SMT. However, the speedup of a single application that is parallelized into multiple threads, is often sensitive to its inherent instruction level parallelism (ILP), as well as the efficiency of synchronization and communication mechanisms between its separate, but possibly dependent threads. Moreover, as these separate threads tend to put pressure on the same architectural resources, no significant speedup can be observed. In this paper, we evaluate and contrast thread-level parallelism (TLP) and speculative precomputation (SPR) techniques for a series of memory intensive codes executed on a specific SMT processor implementation. We explore the performance limits by evaluating the tradeoffs between ILP and TLP for various kinds of instruction streams. By obtaining knowledge on how such streams interact when executed simultaneously on the processor, and quantifying their presence within each application’s threads, we try to interpret the observed performance for each application when parallelized according to the aforementioned techniques. In order to amplify this evaluation process, we also present results gathered from the performance monitoring hardware of the processor. © Springer Science+Business Media, LLC 2007 |
| abstract_unstemmed |
Abstract Simultaneous multithreading (SMT) has been proposed to improve system throughput by overlapping instructions from multiple threads on a single wide-issue processor. Recent studies have demonstrated that diversity of simultaneously executed applications can bring up significant performance gains due to SMT. However, the speedup of a single application that is parallelized into multiple threads, is often sensitive to its inherent instruction level parallelism (ILP), as well as the efficiency of synchronization and communication mechanisms between its separate, but possibly dependent threads. Moreover, as these separate threads tend to put pressure on the same architectural resources, no significant speedup can be observed. In this paper, we evaluate and contrast thread-level parallelism (TLP) and speculative precomputation (SPR) techniques for a series of memory intensive codes executed on a specific SMT processor implementation. We explore the performance limits by evaluating the tradeoffs between ILP and TLP for various kinds of instruction streams. By obtaining knowledge on how such streams interact when executed simultaneously on the processor, and quantifying their presence within each application’s threads, we try to interpret the observed performance for each application when parallelized according to the aforementioned techniques. In order to amplify this evaluation process, we also present results gathered from the performance monitoring hardware of the processor. © Springer Science+Business Media, LLC 2007 |
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Exploring the performance limits of simultaneous multithreading for memory intensive applications |
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Anastopoulos, Nikos Kourtis, Kornilios Koziris, Nectarios |
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