Combating I-O bottleneck using prefetching: model, algorithms, and ramifications
Abstract Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter (Commun. ACM 31(9):1116–1127, [1988]). More than a decade of architectural advancements have led to new features that are not captured in the I-O model—mo...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Verma, Akshat [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2008 |
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| Schlagwörter: |
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| Anmerkung: |
© Springer Science+Business Media, LLC 2008 |
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| Übergeordnetes Werk: |
Enthalten in: The journal of supercomputing - Springer US, 1987, 45(2008), 2 vom: 16. Jan., Seite 205-235 |
|---|---|
| Übergeordnetes Werk: |
volume:45 ; year:2008 ; number:2 ; day:16 ; month:01 ; pages:205-235 |
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| DOI / URN: |
10.1007/s11227-007-0170-0 |
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| 520 | |a Abstract Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter (Commun. ACM 31(9):1116–1127, [1988]). More than a decade of architectural advancements have led to new features that are not captured in the I-O model—most notably the prefetching capability. We propose a relatively simple Prefetch model that incorporates data prefetching in the traditional I-O models and show how to design optimal algorithms that can attain close to peak memory bandwidth. Unlike (the inverse of) memory latency, the memory bandwidth is much closer to the processing speed, thereby, intelligent use of prefetching can considerably mitigate the I-O bottleneck. For some fundamental problems, our algorithms attain running times approaching that of the idealized random access machines under reasonable assumptions. Our work also explains more precisely the significantly superior performance of the I-O efficient algorithms in systems that support prefetching compared to ones that do not. | ||
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10.1007/s11227-007-0170-0 doi (DE-627)OLC2033935604 (DE-He213)s11227-007-0170-0-p DE-627 ger DE-627 rakwb eng 004 620 VZ Verma, Akshat verfasserin aut Combating I-O bottleneck using prefetching: model, algorithms, and ramifications 2008 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2008 Abstract Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter (Commun. ACM 31(9):1116–1127, [1988]). More than a decade of architectural advancements have led to new features that are not captured in the I-O model—most notably the prefetching capability. We propose a relatively simple Prefetch model that incorporates data prefetching in the traditional I-O models and show how to design optimal algorithms that can attain close to peak memory bandwidth. Unlike (the inverse of) memory latency, the memory bandwidth is much closer to the processing speed, thereby, intelligent use of prefetching can considerably mitigate the I-O bottleneck. For some fundamental problems, our algorithms attain running times approaching that of the idealized random access machines under reasonable assumptions. Our work also explains more precisely the significantly superior performance of the I-O efficient algorithms in systems that support prefetching compared to ones that do not. External memory algorithms Prefetching Memory hierarchy Sorting Prediction sequence Sen, Sandeep aut Enthalten in The journal of supercomputing Springer US, 1987 45(2008), 2 vom: 16. Jan., Seite 205-235 (DE-627)13046466X (DE-600)740510-8 (DE-576)018667775 0920-8542 nnns volume:45 year:2008 number:2 day:16 month:01 pages:205-235 https://doi.org/10.1007/s11227-007-0170-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2010 GBV_ILN_4324 AR 45 2008 2 16 01 205-235 |
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10.1007/s11227-007-0170-0 doi (DE-627)OLC2033935604 (DE-He213)s11227-007-0170-0-p DE-627 ger DE-627 rakwb eng 004 620 VZ Verma, Akshat verfasserin aut Combating I-O bottleneck using prefetching: model, algorithms, and ramifications 2008 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2008 Abstract Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter (Commun. ACM 31(9):1116–1127, [1988]). More than a decade of architectural advancements have led to new features that are not captured in the I-O model—most notably the prefetching capability. We propose a relatively simple Prefetch model that incorporates data prefetching in the traditional I-O models and show how to design optimal algorithms that can attain close to peak memory bandwidth. Unlike (the inverse of) memory latency, the memory bandwidth is much closer to the processing speed, thereby, intelligent use of prefetching can considerably mitigate the I-O bottleneck. For some fundamental problems, our algorithms attain running times approaching that of the idealized random access machines under reasonable assumptions. Our work also explains more precisely the significantly superior performance of the I-O efficient algorithms in systems that support prefetching compared to ones that do not. External memory algorithms Prefetching Memory hierarchy Sorting Prediction sequence Sen, Sandeep aut Enthalten in The journal of supercomputing Springer US, 1987 45(2008), 2 vom: 16. Jan., Seite 205-235 (DE-627)13046466X (DE-600)740510-8 (DE-576)018667775 0920-8542 nnns volume:45 year:2008 number:2 day:16 month:01 pages:205-235 https://doi.org/10.1007/s11227-007-0170-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2010 GBV_ILN_4324 AR 45 2008 2 16 01 205-235 |
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Abstract Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter (Commun. ACM 31(9):1116–1127, [1988]). More than a decade of architectural advancements have led to new features that are not captured in the I-O model—most notably the prefetching capability. We propose a relatively simple Prefetch model that incorporates data prefetching in the traditional I-O models and show how to design optimal algorithms that can attain close to peak memory bandwidth. Unlike (the inverse of) memory latency, the memory bandwidth is much closer to the processing speed, thereby, intelligent use of prefetching can considerably mitigate the I-O bottleneck. For some fundamental problems, our algorithms attain running times approaching that of the idealized random access machines under reasonable assumptions. Our work also explains more precisely the significantly superior performance of the I-O efficient algorithms in systems that support prefetching compared to ones that do not. © Springer Science+Business Media, LLC 2008 |
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Abstract Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter (Commun. ACM 31(9):1116–1127, [1988]). More than a decade of architectural advancements have led to new features that are not captured in the I-O model—most notably the prefetching capability. We propose a relatively simple Prefetch model that incorporates data prefetching in the traditional I-O models and show how to design optimal algorithms that can attain close to peak memory bandwidth. Unlike (the inverse of) memory latency, the memory bandwidth is much closer to the processing speed, thereby, intelligent use of prefetching can considerably mitigate the I-O bottleneck. For some fundamental problems, our algorithms attain running times approaching that of the idealized random access machines under reasonable assumptions. Our work also explains more precisely the significantly superior performance of the I-O efficient algorithms in systems that support prefetching compared to ones that do not. © Springer Science+Business Media, LLC 2008 |
| abstract_unstemmed |
Abstract Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter (Commun. ACM 31(9):1116–1127, [1988]). More than a decade of architectural advancements have led to new features that are not captured in the I-O model—most notably the prefetching capability. We propose a relatively simple Prefetch model that incorporates data prefetching in the traditional I-O models and show how to design optimal algorithms that can attain close to peak memory bandwidth. Unlike (the inverse of) memory latency, the memory bandwidth is much closer to the processing speed, thereby, intelligent use of prefetching can considerably mitigate the I-O bottleneck. For some fundamental problems, our algorithms attain running times approaching that of the idealized random access machines under reasonable assumptions. Our work also explains more precisely the significantly superior performance of the I-O efficient algorithms in systems that support prefetching compared to ones that do not. © Springer Science+Business Media, LLC 2008 |
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Combating I-O bottleneck using prefetching: model, algorithms, and ramifications |
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