Energy minimization in the STT-RAM-based high-capacity last-level caches
Abstract Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in the large last-level caches ($ L^{3} $Cs) on account of low leakage, the absence of refresh energy and good scalability. However, long latency and high energy consumption for write operations are disadv...
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| Autor*in: |
Khajekarimi, Elyas [verfasserIn] |
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| Format: |
Artikel |
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Englisch |
| Erschienen: |
2019 |
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| Schlagwörter: |
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| Anmerkung: |
© Springer Science+Business Media, LLC, part of Springer Nature 2019 |
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| Übergeordnetes Werk: |
Enthalten in: The journal of supercomputing - Springer US, 1987, 75(2019), 10 vom: 05. Juni, Seite 6831-6854 |
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volume:75 ; year:2019 ; number:10 ; day:05 ; month:06 ; pages:6831-6854 |
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10.1007/s11227-019-02918-2 |
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| 520 | |a Abstract Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in the large last-level caches ($ L^{3} $Cs) on account of low leakage, the absence of refresh energy and good scalability. However, long latency and high energy consumption for write operations are disadvantages of this technology. The proper utilization of row buffer locality can improve energy efficiency and mitigate negative effects of writing operations in the STT-RAM $ L^{3} $Cs. In this paper, we present an integer linear programming (ILP) formulation which minimizes energy consumption in the STT-RAM-based $ L^{3} $C exploiting the row buffer locality and the prominent features of STT-RAM. Since ILP solvers may not achieve the better result in a reasonable time, we propose a sub-optimal algorithm that obtains the results in a polynomial time. Evaluations demonstrate that on average, our ILP model reduces dynamic energy about 19% and improves row buffer hit rate about 23% compared to the state of the art. | ||
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10.1007/s11227-019-02918-2 doi (DE-627)OLC2033960013 (DE-He213)s11227-019-02918-2-p DE-627 ger DE-627 rakwb eng 004 620 VZ Khajekarimi, Elyas verfasserin aut Energy minimization in the STT-RAM-based high-capacity last-level caches 2019 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC, part of Springer Nature 2019 Abstract Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in the large last-level caches ($ L^{3} $Cs) on account of low leakage, the absence of refresh energy and good scalability. However, long latency and high energy consumption for write operations are disadvantages of this technology. The proper utilization of row buffer locality can improve energy efficiency and mitigate negative effects of writing operations in the STT-RAM $ L^{3} $Cs. In this paper, we present an integer linear programming (ILP) formulation which minimizes energy consumption in the STT-RAM-based $ L^{3} $C exploiting the row buffer locality and the prominent features of STT-RAM. Since ILP solvers may not achieve the better result in a reasonable time, we propose a sub-optimal algorithm that obtains the results in a polynomial time. Evaluations demonstrate that on average, our ILP model reduces dynamic energy about 19% and improves row buffer hit rate about 23% compared to the state of the art. Last-level cache STT-RAM Integer linear programming Row buffer locality Jamshidi, Kamal aut Vafaei, Abbas aut Enthalten in The journal of supercomputing Springer US, 1987 75(2019), 10 vom: 05. Juni, Seite 6831-6854 (DE-627)13046466X (DE-600)740510-8 (DE-576)018667775 0920-8542 nnns volume:75 year:2019 number:10 day:05 month:06 pages:6831-6854 https://doi.org/10.1007/s11227-019-02918-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 AR 75 2019 10 05 06 6831-6854 |
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10.1007/s11227-019-02918-2 doi (DE-627)OLC2033960013 (DE-He213)s11227-019-02918-2-p DE-627 ger DE-627 rakwb eng 004 620 VZ Khajekarimi, Elyas verfasserin aut Energy minimization in the STT-RAM-based high-capacity last-level caches 2019 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC, part of Springer Nature 2019 Abstract Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in the large last-level caches ($ L^{3} $Cs) on account of low leakage, the absence of refresh energy and good scalability. However, long latency and high energy consumption for write operations are disadvantages of this technology. The proper utilization of row buffer locality can improve energy efficiency and mitigate negative effects of writing operations in the STT-RAM $ L^{3} $Cs. In this paper, we present an integer linear programming (ILP) formulation which minimizes energy consumption in the STT-RAM-based $ L^{3} $C exploiting the row buffer locality and the prominent features of STT-RAM. Since ILP solvers may not achieve the better result in a reasonable time, we propose a sub-optimal algorithm that obtains the results in a polynomial time. Evaluations demonstrate that on average, our ILP model reduces dynamic energy about 19% and improves row buffer hit rate about 23% compared to the state of the art. Last-level cache STT-RAM Integer linear programming Row buffer locality Jamshidi, Kamal aut Vafaei, Abbas aut Enthalten in The journal of supercomputing Springer US, 1987 75(2019), 10 vom: 05. Juni, Seite 6831-6854 (DE-627)13046466X (DE-600)740510-8 (DE-576)018667775 0920-8542 nnns volume:75 year:2019 number:10 day:05 month:06 pages:6831-6854 https://doi.org/10.1007/s11227-019-02918-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 AR 75 2019 10 05 06 6831-6854 |
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10.1007/s11227-019-02918-2 doi (DE-627)OLC2033960013 (DE-He213)s11227-019-02918-2-p DE-627 ger DE-627 rakwb eng 004 620 VZ Khajekarimi, Elyas verfasserin aut Energy minimization in the STT-RAM-based high-capacity last-level caches 2019 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC, part of Springer Nature 2019 Abstract Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in the large last-level caches ($ L^{3} $Cs) on account of low leakage, the absence of refresh energy and good scalability. However, long latency and high energy consumption for write operations are disadvantages of this technology. The proper utilization of row buffer locality can improve energy efficiency and mitigate negative effects of writing operations in the STT-RAM $ L^{3} $Cs. In this paper, we present an integer linear programming (ILP) formulation which minimizes energy consumption in the STT-RAM-based $ L^{3} $C exploiting the row buffer locality and the prominent features of STT-RAM. Since ILP solvers may not achieve the better result in a reasonable time, we propose a sub-optimal algorithm that obtains the results in a polynomial time. Evaluations demonstrate that on average, our ILP model reduces dynamic energy about 19% and improves row buffer hit rate about 23% compared to the state of the art. Last-level cache STT-RAM Integer linear programming Row buffer locality Jamshidi, Kamal aut Vafaei, Abbas aut Enthalten in The journal of supercomputing Springer US, 1987 75(2019), 10 vom: 05. Juni, Seite 6831-6854 (DE-627)13046466X (DE-600)740510-8 (DE-576)018667775 0920-8542 nnns volume:75 year:2019 number:10 day:05 month:06 pages:6831-6854 https://doi.org/10.1007/s11227-019-02918-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 AR 75 2019 10 05 06 6831-6854 |
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Abstract Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in the large last-level caches ($ L^{3} $Cs) on account of low leakage, the absence of refresh energy and good scalability. However, long latency and high energy consumption for write operations are disadvantages of this technology. The proper utilization of row buffer locality can improve energy efficiency and mitigate negative effects of writing operations in the STT-RAM $ L^{3} $Cs. In this paper, we present an integer linear programming (ILP) formulation which minimizes energy consumption in the STT-RAM-based $ L^{3} $C exploiting the row buffer locality and the prominent features of STT-RAM. Since ILP solvers may not achieve the better result in a reasonable time, we propose a sub-optimal algorithm that obtains the results in a polynomial time. Evaluations demonstrate that on average, our ILP model reduces dynamic energy about 19% and improves row buffer hit rate about 23% compared to the state of the art. © Springer Science+Business Media, LLC, part of Springer Nature 2019 |
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Abstract Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in the large last-level caches ($ L^{3} $Cs) on account of low leakage, the absence of refresh energy and good scalability. However, long latency and high energy consumption for write operations are disadvantages of this technology. The proper utilization of row buffer locality can improve energy efficiency and mitigate negative effects of writing operations in the STT-RAM $ L^{3} $Cs. In this paper, we present an integer linear programming (ILP) formulation which minimizes energy consumption in the STT-RAM-based $ L^{3} $C exploiting the row buffer locality and the prominent features of STT-RAM. Since ILP solvers may not achieve the better result in a reasonable time, we propose a sub-optimal algorithm that obtains the results in a polynomial time. Evaluations demonstrate that on average, our ILP model reduces dynamic energy about 19% and improves row buffer hit rate about 23% compared to the state of the art. © Springer Science+Business Media, LLC, part of Springer Nature 2019 |
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Abstract Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in the large last-level caches ($ L^{3} $Cs) on account of low leakage, the absence of refresh energy and good scalability. However, long latency and high energy consumption for write operations are disadvantages of this technology. The proper utilization of row buffer locality can improve energy efficiency and mitigate negative effects of writing operations in the STT-RAM $ L^{3} $Cs. In this paper, we present an integer linear programming (ILP) formulation which minimizes energy consumption in the STT-RAM-based $ L^{3} $C exploiting the row buffer locality and the prominent features of STT-RAM. Since ILP solvers may not achieve the better result in a reasonable time, we propose a sub-optimal algorithm that obtains the results in a polynomial time. Evaluations demonstrate that on average, our ILP model reduces dynamic energy about 19% and improves row buffer hit rate about 23% compared to the state of the art. © Springer Science+Business Media, LLC, part of Springer Nature 2019 |
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Energy minimization in the STT-RAM-based high-capacity last-level caches |
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