Integrated circuit failure analysis using physical ion sputtering
Abstract A method for opening integrated circuits (ICs) from the frontal side for detecting possible defects is presented. This method is based on the application of the physical ion sputtering technique, provides high-precision layer-by-layer removal of the IC material, and makes it possible to ope...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Vyatkin, A. F. [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2011 |
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| Schlagwörter: |
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| Anmerkung: |
© Pleiades Publishing, Ltd. 2011 |
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| Übergeordnetes Werk: |
Enthalten in: Instruments and experimental techniques - SP MAIK Nauka/Interperiodica, 1959, 54(2011), 2 vom: März, Seite 268-272 |
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| Übergeordnetes Werk: |
volume:54 ; year:2011 ; number:2 ; month:03 ; pages:268-272 |
| Links: |
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| DOI / URN: |
10.1134/S0020441211020217 |
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OLC203415102X |
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| 520 | |a Abstract A method for opening integrated circuits (ICs) from the frontal side for detecting possible defects is presented. This method is based on the application of the physical ion sputtering technique, provides high-precision layer-by-layer removal of the IC material, and makes it possible to open and investigate each metallization layer without an interfering effect of neighboring layers. The main principles of using this method, the design of the experimental setup, and the results of applying this method to the analysis of actual ICs are discussed. | ||
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10.1134/S0020441211020217 doi (DE-627)OLC203415102X (DE-He213)S0020441211020217-p DE-627 ger DE-627 rakwb eng 620 VZ 11 ssgn Vyatkin, A. F. verfasserin aut Integrated circuit failure analysis using physical ion sputtering 2011 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Pleiades Publishing, Ltd. 2011 Abstract A method for opening integrated circuits (ICs) from the frontal side for detecting possible defects is presented. This method is based on the application of the physical ion sputtering technique, provides high-precision layer-by-layer removal of the IC material, and makes it possible to open and investigate each metallization layer without an interfering effect of neighboring layers. The main principles of using this method, the design of the experimental setup, and the results of applying this method to the analysis of actual ICs are discussed. Etching Rate Metallization Layer Layer Removal Physical Sputtering Dielectric Insulation Zinenko, V. I. aut Enthalten in Instruments and experimental techniques SP MAIK Nauka/Interperiodica, 1959 54(2011), 2 vom: März, Seite 268-272 (DE-627)129603007 (DE-600)241643-8 (DE-576)015096815 0020-4412 nnns volume:54 year:2011 number:2 month:03 pages:268-272 https://doi.org/10.1134/S0020441211020217 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 AR 54 2011 2 03 268-272 |
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10.1134/S0020441211020217 doi (DE-627)OLC203415102X (DE-He213)S0020441211020217-p DE-627 ger DE-627 rakwb eng 620 VZ 11 ssgn Vyatkin, A. F. verfasserin aut Integrated circuit failure analysis using physical ion sputtering 2011 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Pleiades Publishing, Ltd. 2011 Abstract A method for opening integrated circuits (ICs) from the frontal side for detecting possible defects is presented. This method is based on the application of the physical ion sputtering technique, provides high-precision layer-by-layer removal of the IC material, and makes it possible to open and investigate each metallization layer without an interfering effect of neighboring layers. The main principles of using this method, the design of the experimental setup, and the results of applying this method to the analysis of actual ICs are discussed. Etching Rate Metallization Layer Layer Removal Physical Sputtering Dielectric Insulation Zinenko, V. I. aut Enthalten in Instruments and experimental techniques SP MAIK Nauka/Interperiodica, 1959 54(2011), 2 vom: März, Seite 268-272 (DE-627)129603007 (DE-600)241643-8 (DE-576)015096815 0020-4412 nnns volume:54 year:2011 number:2 month:03 pages:268-272 https://doi.org/10.1134/S0020441211020217 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 AR 54 2011 2 03 268-272 |
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10.1134/S0020441211020217 doi (DE-627)OLC203415102X (DE-He213)S0020441211020217-p DE-627 ger DE-627 rakwb eng 620 VZ 11 ssgn Vyatkin, A. F. verfasserin aut Integrated circuit failure analysis using physical ion sputtering 2011 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Pleiades Publishing, Ltd. 2011 Abstract A method for opening integrated circuits (ICs) from the frontal side for detecting possible defects is presented. This method is based on the application of the physical ion sputtering technique, provides high-precision layer-by-layer removal of the IC material, and makes it possible to open and investigate each metallization layer without an interfering effect of neighboring layers. The main principles of using this method, the design of the experimental setup, and the results of applying this method to the analysis of actual ICs are discussed. Etching Rate Metallization Layer Layer Removal Physical Sputtering Dielectric Insulation Zinenko, V. I. aut Enthalten in Instruments and experimental techniques SP MAIK Nauka/Interperiodica, 1959 54(2011), 2 vom: März, Seite 268-272 (DE-627)129603007 (DE-600)241643-8 (DE-576)015096815 0020-4412 nnns volume:54 year:2011 number:2 month:03 pages:268-272 https://doi.org/10.1134/S0020441211020217 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 AR 54 2011 2 03 268-272 |
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10.1134/S0020441211020217 doi (DE-627)OLC203415102X (DE-He213)S0020441211020217-p DE-627 ger DE-627 rakwb eng 620 VZ 11 ssgn Vyatkin, A. F. verfasserin aut Integrated circuit failure analysis using physical ion sputtering 2011 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Pleiades Publishing, Ltd. 2011 Abstract A method for opening integrated circuits (ICs) from the frontal side for detecting possible defects is presented. This method is based on the application of the physical ion sputtering technique, provides high-precision layer-by-layer removal of the IC material, and makes it possible to open and investigate each metallization layer without an interfering effect of neighboring layers. The main principles of using this method, the design of the experimental setup, and the results of applying this method to the analysis of actual ICs are discussed. Etching Rate Metallization Layer Layer Removal Physical Sputtering Dielectric Insulation Zinenko, V. I. aut Enthalten in Instruments and experimental techniques SP MAIK Nauka/Interperiodica, 1959 54(2011), 2 vom: März, Seite 268-272 (DE-627)129603007 (DE-600)241643-8 (DE-576)015096815 0020-4412 nnns volume:54 year:2011 number:2 month:03 pages:268-272 https://doi.org/10.1134/S0020441211020217 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 AR 54 2011 2 03 268-272 |
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Abstract A method for opening integrated circuits (ICs) from the frontal side for detecting possible defects is presented. This method is based on the application of the physical ion sputtering technique, provides high-precision layer-by-layer removal of the IC material, and makes it possible to open and investigate each metallization layer without an interfering effect of neighboring layers. The main principles of using this method, the design of the experimental setup, and the results of applying this method to the analysis of actual ICs are discussed. © Pleiades Publishing, Ltd. 2011 |
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Abstract A method for opening integrated circuits (ICs) from the frontal side for detecting possible defects is presented. This method is based on the application of the physical ion sputtering technique, provides high-precision layer-by-layer removal of the IC material, and makes it possible to open and investigate each metallization layer without an interfering effect of neighboring layers. The main principles of using this method, the design of the experimental setup, and the results of applying this method to the analysis of actual ICs are discussed. © Pleiades Publishing, Ltd. 2011 |
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Abstract A method for opening integrated circuits (ICs) from the frontal side for detecting possible defects is presented. This method is based on the application of the physical ion sputtering technique, provides high-precision layer-by-layer removal of the IC material, and makes it possible to open and investigate each metallization layer without an interfering effect of neighboring layers. The main principles of using this method, the design of the experimental setup, and the results of applying this method to the analysis of actual ICs are discussed. © Pleiades Publishing, Ltd. 2011 |
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F.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Integrated circuit failure analysis using physical ion sputtering</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2011</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© Pleiades Publishing, Ltd. 2011</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract A method for opening integrated circuits (ICs) from the frontal side for detecting possible defects is presented. This method is based on the application of the physical ion sputtering technique, provides high-precision layer-by-layer removal of the IC material, and makes it possible to open and investigate each metallization layer without an interfering effect of neighboring layers. The main principles of using this method, the design of the experimental setup, and the results of applying this method to the analysis of actual ICs are discussed.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Etching Rate</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Metallization Layer</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Layer Removal</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Physical Sputtering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Dielectric Insulation</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Zinenko, V. I.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Instruments and experimental techniques</subfield><subfield code="d">SP MAIK Nauka/Interperiodica, 1959</subfield><subfield code="g">54(2011), 2 vom: März, Seite 268-272</subfield><subfield code="w">(DE-627)129603007</subfield><subfield code="w">(DE-600)241643-8</subfield><subfield code="w">(DE-576)015096815</subfield><subfield code="x">0020-4412</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:54</subfield><subfield code="g">year:2011</subfield><subfield code="g">number:2</subfield><subfield code="g">month:03</subfield><subfield code="g">pages:268-272</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">https://doi.org/10.1134/S0020441211020217</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-PHY</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">54</subfield><subfield code="j">2011</subfield><subfield code="e">2</subfield><subfield code="c">03</subfield><subfield code="h">268-272</subfield></datafield></record></collection>
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