Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input
Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases...
Ausführliche Beschreibung
Autor*in: |
Yang, Wei-Bin [verfasserIn] |
---|
Format: |
Artikel |
---|---|
Sprache: |
Englisch |
Erschienen: |
2017 |
---|
Schlagwörter: |
Fast-locked digitally controlled low-dropout regulator (FDLDO) |
---|
Anmerkung: |
© Springer Science+Business Media, LLC 2017 |
---|
Übergeordnetes Werk: |
Enthalten in: Circuits, systems and signal processing - Springer US, 1982, 36(2017), 12 vom: 30. Aug., Seite 5041-5061 |
---|---|
Übergeordnetes Werk: |
volume:36 ; year:2017 ; number:12 ; day:30 ; month:08 ; pages:5041-5061 |
Links: |
---|
DOI / URN: |
10.1007/s00034-017-0642-2 |
---|
Katalog-ID: |
OLC2034850726 |
---|
LEADER | 01000caa a22002652 4500 | ||
---|---|---|---|
001 | OLC2034850726 | ||
003 | DE-627 | ||
005 | 20230331224754.0 | ||
007 | tu | ||
008 | 200819s2017 xx ||||| 00| ||eng c | ||
024 | 7 | |a 10.1007/s00034-017-0642-2 |2 doi | |
035 | |a (DE-627)OLC2034850726 | ||
035 | |a (DE-He213)s00034-017-0642-2-p | ||
040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
041 | |a eng | ||
082 | 0 | 4 | |a 600 |q VZ |
100 | 1 | |a Yang, Wei-Bin |e verfasserin |4 aut | |
245 | 1 | 0 | |a Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input |
264 | 1 | |c 2017 | |
336 | |a Text |b txt |2 rdacontent | ||
337 | |a ohne Hilfsmittel zu benutzen |b n |2 rdamedia | ||
338 | |a Band |b nc |2 rdacarrier | ||
500 | |a © Springer Science+Business Media, LLC 2017 | ||
520 | |a Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. | ||
650 | 4 | |a Fast-locked digitally controlled low-dropout regulator (FDLDO) | |
650 | 4 | |a Ultra-low voltage | |
650 | 4 | |a Fast-locked control mechanism | |
650 | 4 | |a Load regulation | |
650 | 4 | |a Line regulation | |
650 | 4 | |a Wearable electronic devices | |
700 | 1 | |a Lin, Yu-Yao |4 aut | |
700 | 1 | |a Lo, Yu-Lung |0 (orcid)0000-0003-1456-7158 |4 aut | |
773 | 0 | 8 | |i Enthalten in |t Circuits, systems and signal processing |d Springer US, 1982 |g 36(2017), 12 vom: 30. Aug., Seite 5041-5061 |w (DE-627)130312134 |w (DE-600)588684-3 |w (DE-576)015889939 |x 0278-081X |7 nnns |
773 | 1 | 8 | |g volume:36 |g year:2017 |g number:12 |g day:30 |g month:08 |g pages:5041-5061 |
856 | 4 | 1 | |u https://doi.org/10.1007/s00034-017-0642-2 |z lizenzpflichtig |3 Volltext |
912 | |a GBV_USEFLAG_A | ||
912 | |a SYSFLAG_A | ||
912 | |a GBV_OLC | ||
912 | |a SSG-OLC-TEC | ||
912 | |a GBV_ILN_70 | ||
912 | |a GBV_ILN_2244 | ||
912 | |a GBV_ILN_4266 | ||
951 | |a AR | ||
952 | |d 36 |j 2017 |e 12 |b 30 |c 08 |h 5041-5061 |
author_variant |
w b y wby y y l yyl y l l yll |
---|---|
matchkey_str |
article:0278081X:2017----::einfatokdiialcnrlelwrpurgltr |
hierarchy_sort_str |
2017 |
publishDate |
2017 |
allfields |
10.1007/s00034-017-0642-2 doi (DE-627)OLC2034850726 (DE-He213)s00034-017-0642-2-p DE-627 ger DE-627 rakwb eng 600 VZ Yang, Wei-Bin verfasserin aut Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2017 Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. Fast-locked digitally controlled low-dropout regulator (FDLDO) Ultra-low voltage Fast-locked control mechanism Load regulation Line regulation Wearable electronic devices Lin, Yu-Yao aut Lo, Yu-Lung (orcid)0000-0003-1456-7158 aut Enthalten in Circuits, systems and signal processing Springer US, 1982 36(2017), 12 vom: 30. Aug., Seite 5041-5061 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:36 year:2017 number:12 day:30 month:08 pages:5041-5061 https://doi.org/10.1007/s00034-017-0642-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2244 GBV_ILN_4266 AR 36 2017 12 30 08 5041-5061 |
spelling |
10.1007/s00034-017-0642-2 doi (DE-627)OLC2034850726 (DE-He213)s00034-017-0642-2-p DE-627 ger DE-627 rakwb eng 600 VZ Yang, Wei-Bin verfasserin aut Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2017 Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. Fast-locked digitally controlled low-dropout regulator (FDLDO) Ultra-low voltage Fast-locked control mechanism Load regulation Line regulation Wearable electronic devices Lin, Yu-Yao aut Lo, Yu-Lung (orcid)0000-0003-1456-7158 aut Enthalten in Circuits, systems and signal processing Springer US, 1982 36(2017), 12 vom: 30. Aug., Seite 5041-5061 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:36 year:2017 number:12 day:30 month:08 pages:5041-5061 https://doi.org/10.1007/s00034-017-0642-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2244 GBV_ILN_4266 AR 36 2017 12 30 08 5041-5061 |
allfields_unstemmed |
10.1007/s00034-017-0642-2 doi (DE-627)OLC2034850726 (DE-He213)s00034-017-0642-2-p DE-627 ger DE-627 rakwb eng 600 VZ Yang, Wei-Bin verfasserin aut Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2017 Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. Fast-locked digitally controlled low-dropout regulator (FDLDO) Ultra-low voltage Fast-locked control mechanism Load regulation Line regulation Wearable electronic devices Lin, Yu-Yao aut Lo, Yu-Lung (orcid)0000-0003-1456-7158 aut Enthalten in Circuits, systems and signal processing Springer US, 1982 36(2017), 12 vom: 30. Aug., Seite 5041-5061 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:36 year:2017 number:12 day:30 month:08 pages:5041-5061 https://doi.org/10.1007/s00034-017-0642-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2244 GBV_ILN_4266 AR 36 2017 12 30 08 5041-5061 |
allfieldsGer |
10.1007/s00034-017-0642-2 doi (DE-627)OLC2034850726 (DE-He213)s00034-017-0642-2-p DE-627 ger DE-627 rakwb eng 600 VZ Yang, Wei-Bin verfasserin aut Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2017 Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. Fast-locked digitally controlled low-dropout regulator (FDLDO) Ultra-low voltage Fast-locked control mechanism Load regulation Line regulation Wearable electronic devices Lin, Yu-Yao aut Lo, Yu-Lung (orcid)0000-0003-1456-7158 aut Enthalten in Circuits, systems and signal processing Springer US, 1982 36(2017), 12 vom: 30. Aug., Seite 5041-5061 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:36 year:2017 number:12 day:30 month:08 pages:5041-5061 https://doi.org/10.1007/s00034-017-0642-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2244 GBV_ILN_4266 AR 36 2017 12 30 08 5041-5061 |
allfieldsSound |
10.1007/s00034-017-0642-2 doi (DE-627)OLC2034850726 (DE-He213)s00034-017-0642-2-p DE-627 ger DE-627 rakwb eng 600 VZ Yang, Wei-Bin verfasserin aut Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2017 Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. Fast-locked digitally controlled low-dropout regulator (FDLDO) Ultra-low voltage Fast-locked control mechanism Load regulation Line regulation Wearable electronic devices Lin, Yu-Yao aut Lo, Yu-Lung (orcid)0000-0003-1456-7158 aut Enthalten in Circuits, systems and signal processing Springer US, 1982 36(2017), 12 vom: 30. Aug., Seite 5041-5061 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:36 year:2017 number:12 day:30 month:08 pages:5041-5061 https://doi.org/10.1007/s00034-017-0642-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2244 GBV_ILN_4266 AR 36 2017 12 30 08 5041-5061 |
language |
English |
source |
Enthalten in Circuits, systems and signal processing 36(2017), 12 vom: 30. Aug., Seite 5041-5061 volume:36 year:2017 number:12 day:30 month:08 pages:5041-5061 |
sourceStr |
Enthalten in Circuits, systems and signal processing 36(2017), 12 vom: 30. Aug., Seite 5041-5061 volume:36 year:2017 number:12 day:30 month:08 pages:5041-5061 |
format_phy_str_mv |
Article |
institution |
findex.gbv.de |
topic_facet |
Fast-locked digitally controlled low-dropout regulator (FDLDO) Ultra-low voltage Fast-locked control mechanism Load regulation Line regulation Wearable electronic devices |
dewey-raw |
600 |
isfreeaccess_bool |
false |
container_title |
Circuits, systems and signal processing |
authorswithroles_txt_mv |
Yang, Wei-Bin @@aut@@ Lin, Yu-Yao @@aut@@ Lo, Yu-Lung @@aut@@ |
publishDateDaySort_date |
2017-08-30T00:00:00Z |
hierarchy_top_id |
130312134 |
dewey-sort |
3600 |
id |
OLC2034850726 |
language_de |
englisch |
fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">OLC2034850726</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230331224754.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">200819s2017 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s00034-017-0642-2</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC2034850726</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-He213)s00034-017-0642-2-p</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">600</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Yang, Wei-Bin</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2017</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© Springer Science+Business Media, LLC 2017</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fast-locked digitally controlled low-dropout regulator (FDLDO)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Ultra-low voltage</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fast-locked control mechanism</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Load regulation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Line regulation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Wearable electronic devices</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Lin, Yu-Yao</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Lo, Yu-Lung</subfield><subfield code="0">(orcid)0000-0003-1456-7158</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Circuits, systems and signal processing</subfield><subfield code="d">Springer US, 1982</subfield><subfield code="g">36(2017), 12 vom: 30. Aug., Seite 5041-5061</subfield><subfield code="w">(DE-627)130312134</subfield><subfield code="w">(DE-600)588684-3</subfield><subfield code="w">(DE-576)015889939</subfield><subfield code="x">0278-081X</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:36</subfield><subfield code="g">year:2017</subfield><subfield code="g">number:12</subfield><subfield code="g">day:30</subfield><subfield code="g">month:08</subfield><subfield code="g">pages:5041-5061</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">https://doi.org/10.1007/s00034-017-0642-2</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2244</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4266</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">36</subfield><subfield code="j">2017</subfield><subfield code="e">12</subfield><subfield code="b">30</subfield><subfield code="c">08</subfield><subfield code="h">5041-5061</subfield></datafield></record></collection>
|
author |
Yang, Wei-Bin |
spellingShingle |
Yang, Wei-Bin ddc 600 misc Fast-locked digitally controlled low-dropout regulator (FDLDO) misc Ultra-low voltage misc Fast-locked control mechanism misc Load regulation misc Line regulation misc Wearable electronic devices Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input |
authorStr |
Yang, Wei-Bin |
ppnlink_with_tag_str_mv |
@@773@@(DE-627)130312134 |
format |
Article |
dewey-ones |
600 - Technology |
delete_txt_mv |
keep |
author_role |
aut aut aut |
collection |
OLC |
remote_str |
false |
illustrated |
Not Illustrated |
issn |
0278-081X |
topic_title |
600 VZ Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input Fast-locked digitally controlled low-dropout regulator (FDLDO) Ultra-low voltage Fast-locked control mechanism Load regulation Line regulation Wearable electronic devices |
topic |
ddc 600 misc Fast-locked digitally controlled low-dropout regulator (FDLDO) misc Ultra-low voltage misc Fast-locked control mechanism misc Load regulation misc Line regulation misc Wearable electronic devices |
topic_unstemmed |
ddc 600 misc Fast-locked digitally controlled low-dropout regulator (FDLDO) misc Ultra-low voltage misc Fast-locked control mechanism misc Load regulation misc Line regulation misc Wearable electronic devices |
topic_browse |
ddc 600 misc Fast-locked digitally controlled low-dropout regulator (FDLDO) misc Ultra-low voltage misc Fast-locked control mechanism misc Load regulation misc Line regulation misc Wearable electronic devices |
format_facet |
Aufsätze Gedruckte Aufsätze |
format_main_str_mv |
Text Zeitschrift/Artikel |
carriertype_str_mv |
nc |
hierarchy_parent_title |
Circuits, systems and signal processing |
hierarchy_parent_id |
130312134 |
dewey-tens |
600 - Technology |
hierarchy_top_title |
Circuits, systems and signal processing |
isfreeaccess_txt |
false |
familylinks_str_mv |
(DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 |
title |
Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input |
ctrlnum |
(DE-627)OLC2034850726 (DE-He213)s00034-017-0642-2-p |
title_full |
Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input |
author_sort |
Yang, Wei-Bin |
journal |
Circuits, systems and signal processing |
journalStr |
Circuits, systems and signal processing |
lang_code |
eng |
isOA_bool |
false |
dewey-hundreds |
600 - Technology |
recordtype |
marc |
publishDateSort |
2017 |
contenttype_str_mv |
txt |
container_start_page |
5041 |
author_browse |
Yang, Wei-Bin Lin, Yu-Yao Lo, Yu-Lung |
container_volume |
36 |
class |
600 VZ |
format_se |
Aufsätze |
author-letter |
Yang, Wei-Bin |
doi_str_mv |
10.1007/s00034-017-0642-2 |
normlink |
(ORCID)0000-0003-1456-7158 |
normlink_prefix_str_mv |
(orcid)0000-0003-1456-7158 |
dewey-full |
600 |
title_sort |
design of fast-locked digitally controlled low-dropout regulator for ultra-low voltage input |
title_auth |
Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input |
abstract |
Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. © Springer Science+Business Media, LLC 2017 |
abstractGer |
Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. © Springer Science+Business Media, LLC 2017 |
abstract_unstemmed |
Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. © Springer Science+Business Media, LLC 2017 |
collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2244 GBV_ILN_4266 |
container_issue |
12 |
title_short |
Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input |
url |
https://doi.org/10.1007/s00034-017-0642-2 |
remote_bool |
false |
author2 |
Lin, Yu-Yao Lo, Yu-Lung |
author2Str |
Lin, Yu-Yao Lo, Yu-Lung |
ppnlink |
130312134 |
mediatype_str_mv |
n |
isOA_txt |
false |
hochschulschrift_bool |
false |
doi_str |
10.1007/s00034-017-0642-2 |
up_date |
2024-07-03T22:42:41.282Z |
_version_ |
1803599543043883008 |
fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">OLC2034850726</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230331224754.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">200819s2017 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s00034-017-0642-2</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC2034850726</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-He213)s00034-017-0642-2-p</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">600</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Yang, Wei-Bin</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2017</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© Springer Science+Business Media, LLC 2017</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fast-locked digitally controlled low-dropout regulator (FDLDO)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Ultra-low voltage</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fast-locked control mechanism</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Load regulation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Line regulation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Wearable electronic devices</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Lin, Yu-Yao</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Lo, Yu-Lung</subfield><subfield code="0">(orcid)0000-0003-1456-7158</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Circuits, systems and signal processing</subfield><subfield code="d">Springer US, 1982</subfield><subfield code="g">36(2017), 12 vom: 30. Aug., Seite 5041-5061</subfield><subfield code="w">(DE-627)130312134</subfield><subfield code="w">(DE-600)588684-3</subfield><subfield code="w">(DE-576)015889939</subfield><subfield code="x">0278-081X</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:36</subfield><subfield code="g">year:2017</subfield><subfield code="g">number:12</subfield><subfield code="g">day:30</subfield><subfield code="g">month:08</subfield><subfield code="g">pages:5041-5061</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">https://doi.org/10.1007/s00034-017-0642-2</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-TEC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2244</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4266</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">36</subfield><subfield code="j">2017</subfield><subfield code="e">12</subfield><subfield code="b">30</subfield><subfield code="c">08</subfield><subfield code="h">5041-5061</subfield></datafield></record></collection>
|
score |
7.401719 |