Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input
Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Yang, Wei-Bin [verfasserIn] |
|---|
| Format: |
Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
2017 |
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| Schlagwörter: |
Fast-locked digitally controlled low-dropout regulator (FDLDO) |
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| Anmerkung: |
© Springer Science+Business Media, LLC 2017 |
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| Übergeordnetes Werk: |
Enthalten in: Circuits, systems and signal processing - Springer US, 1982, 36(2017), 12 vom: 30. Aug., Seite 5041-5061 |
|---|---|
| Übergeordnetes Werk: |
volume:36 ; year:2017 ; number:12 ; day:30 ; month:08 ; pages:5041-5061 |
| Links: |
|---|
| DOI / URN: |
10.1007/s00034-017-0642-2 |
|---|
| Katalog-ID: |
OLC2034850726 |
|---|
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| 520 | |a Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. | ||
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| 650 | 4 | |a Fast-locked control mechanism | |
| 650 | 4 | |a Load regulation | |
| 650 | 4 | |a Line regulation | |
| 650 | 4 | |a Wearable electronic devices | |
| 700 | 1 | |a Lin, Yu-Yao |4 aut | |
| 700 | 1 | |a Lo, Yu-Lung |0 (orcid)0000-0003-1456-7158 |4 aut | |
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10.1007/s00034-017-0642-2 doi (DE-627)OLC2034850726 (DE-He213)s00034-017-0642-2-p DE-627 ger DE-627 rakwb eng 600 VZ Yang, Wei-Bin verfasserin aut Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2017 Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. Fast-locked digitally controlled low-dropout regulator (FDLDO) Ultra-low voltage Fast-locked control mechanism Load regulation Line regulation Wearable electronic devices Lin, Yu-Yao aut Lo, Yu-Lung (orcid)0000-0003-1456-7158 aut Enthalten in Circuits, systems and signal processing Springer US, 1982 36(2017), 12 vom: 30. Aug., Seite 5041-5061 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:36 year:2017 number:12 day:30 month:08 pages:5041-5061 https://doi.org/10.1007/s00034-017-0642-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2244 GBV_ILN_4266 AR 36 2017 12 30 08 5041-5061 |
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10.1007/s00034-017-0642-2 doi (DE-627)OLC2034850726 (DE-He213)s00034-017-0642-2-p DE-627 ger DE-627 rakwb eng 600 VZ Yang, Wei-Bin verfasserin aut Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2017 Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. Fast-locked digitally controlled low-dropout regulator (FDLDO) Ultra-low voltage Fast-locked control mechanism Load regulation Line regulation Wearable electronic devices Lin, Yu-Yao aut Lo, Yu-Lung (orcid)0000-0003-1456-7158 aut Enthalten in Circuits, systems and signal processing Springer US, 1982 36(2017), 12 vom: 30. Aug., Seite 5041-5061 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:36 year:2017 number:12 day:30 month:08 pages:5041-5061 https://doi.org/10.1007/s00034-017-0642-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2244 GBV_ILN_4266 AR 36 2017 12 30 08 5041-5061 |
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10.1007/s00034-017-0642-2 doi (DE-627)OLC2034850726 (DE-He213)s00034-017-0642-2-p DE-627 ger DE-627 rakwb eng 600 VZ Yang, Wei-Bin verfasserin aut Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2017 Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. Fast-locked digitally controlled low-dropout regulator (FDLDO) Ultra-low voltage Fast-locked control mechanism Load regulation Line regulation Wearable electronic devices Lin, Yu-Yao aut Lo, Yu-Lung (orcid)0000-0003-1456-7158 aut Enthalten in Circuits, systems and signal processing Springer US, 1982 36(2017), 12 vom: 30. Aug., Seite 5041-5061 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:36 year:2017 number:12 day:30 month:08 pages:5041-5061 https://doi.org/10.1007/s00034-017-0642-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2244 GBV_ILN_4266 AR 36 2017 12 30 08 5041-5061 |
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10.1007/s00034-017-0642-2 doi (DE-627)OLC2034850726 (DE-He213)s00034-017-0642-2-p DE-627 ger DE-627 rakwb eng 600 VZ Yang, Wei-Bin verfasserin aut Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2017 Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. Fast-locked digitally controlled low-dropout regulator (FDLDO) Ultra-low voltage Fast-locked control mechanism Load regulation Line regulation Wearable electronic devices Lin, Yu-Yao aut Lo, Yu-Lung (orcid)0000-0003-1456-7158 aut Enthalten in Circuits, systems and signal processing Springer US, 1982 36(2017), 12 vom: 30. Aug., Seite 5041-5061 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:36 year:2017 number:12 day:30 month:08 pages:5041-5061 https://doi.org/10.1007/s00034-017-0642-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2244 GBV_ILN_4266 AR 36 2017 12 30 08 5041-5061 |
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10.1007/s00034-017-0642-2 doi (DE-627)OLC2034850726 (DE-He213)s00034-017-0642-2-p DE-627 ger DE-627 rakwb eng 600 VZ Yang, Wei-Bin verfasserin aut Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input 2017 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2017 Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. Fast-locked digitally controlled low-dropout regulator (FDLDO) Ultra-low voltage Fast-locked control mechanism Load regulation Line regulation Wearable electronic devices Lin, Yu-Yao aut Lo, Yu-Lung (orcid)0000-0003-1456-7158 aut Enthalten in Circuits, systems and signal processing Springer US, 1982 36(2017), 12 vom: 30. Aug., Seite 5041-5061 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:36 year:2017 number:12 day:30 month:08 pages:5041-5061 https://doi.org/10.1007/s00034-017-0642-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_70 GBV_ILN_2244 GBV_ILN_4266 AR 36 2017 12 30 08 5041-5061 |
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Circuits, systems and signal processing |
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eng |
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600 - Technology |
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2017 |
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Yang, Wei-Bin Lin, Yu-Yao Lo, Yu-Lung |
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36 |
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Yang, Wei-Bin |
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10.1007/s00034-017-0642-2 |
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600 |
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design of fast-locked digitally controlled low-dropout regulator for ultra-low voltage input |
| title_auth |
Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input |
| abstract |
Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. © Springer Science+Business Media, LLC 2017 |
| abstractGer |
Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. © Springer Science+Business Media, LLC 2017 |
| abstract_unstemmed |
Abstract This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 $$\mu \hbox {A}$$ for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 $$\mu \hbox {s}$$. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage. © Springer Science+Business Media, LLC 2017 |
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| title_short |
Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input |
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https://doi.org/10.1007/s00034-017-0642-2 |
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Lin, Yu-Yao Lo, Yu-Lung |
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2024-07-03T22:42:41.282Z |
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