A novel CMOS process compatible high performance parallel-stacked RF spiral inductor
Abstract In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q fa...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Jair, D. K. [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2009 |
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| Schlagwörter: |
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| Anmerkung: |
© Springer-Verlag 2009 |
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| Übergeordnetes Werk: |
Enthalten in: Microsystem technologies - Springer-Verlag, 1994, 16(2009), 7 vom: 15. Dez., Seite 1175-1179 |
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| Übergeordnetes Werk: |
volume:16 ; year:2009 ; number:7 ; day:15 ; month:12 ; pages:1175-1179 |
| Links: |
|---|
| DOI / URN: |
10.1007/s00542-009-0975-2 |
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OLC2034928253 |
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| 520 | |a Abstract In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications. | ||
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10.1007/s00542-009-0975-2 doi (DE-627)OLC2034928253 (DE-He213)s00542-009-0975-2-p DE-627 ger DE-627 rakwb eng 620 VZ 510 VZ Jair, D. K. verfasserin aut A novel CMOS process compatible high performance parallel-stacked RF spiral inductor 2009 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer-Verlag 2009 Abstract In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications. CMOS Process Chip Size Electroless Copper Spiral Inductor Metal Width Hsieh, Ming Chun aut Lin, C. S. aut Enthalten in Microsystem technologies Springer-Verlag, 1994 16(2009), 7 vom: 15. Dez., Seite 1175-1179 (DE-627)182644278 (DE-600)1223008-X (DE-576)045302146 0946-7076 nnns volume:16 year:2009 number:7 day:15 month:12 pages:1175-1179 https://doi.org/10.1007/s00542-009-0975-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT SSG-OPC-MAT GBV_ILN_40 GBV_ILN_70 GBV_ILN_95 GBV_ILN_267 GBV_ILN_2018 GBV_ILN_2020 GBV_ILN_2048 GBV_ILN_4036 GBV_ILN_4116 GBV_ILN_4277 AR 16 2009 7 15 12 1175-1179 |
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10.1007/s00542-009-0975-2 doi (DE-627)OLC2034928253 (DE-He213)s00542-009-0975-2-p DE-627 ger DE-627 rakwb eng 620 VZ 510 VZ Jair, D. K. verfasserin aut A novel CMOS process compatible high performance parallel-stacked RF spiral inductor 2009 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer-Verlag 2009 Abstract In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications. CMOS Process Chip Size Electroless Copper Spiral Inductor Metal Width Hsieh, Ming Chun aut Lin, C. S. aut Enthalten in Microsystem technologies Springer-Verlag, 1994 16(2009), 7 vom: 15. Dez., Seite 1175-1179 (DE-627)182644278 (DE-600)1223008-X (DE-576)045302146 0946-7076 nnns volume:16 year:2009 number:7 day:15 month:12 pages:1175-1179 https://doi.org/10.1007/s00542-009-0975-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT SSG-OPC-MAT GBV_ILN_40 GBV_ILN_70 GBV_ILN_95 GBV_ILN_267 GBV_ILN_2018 GBV_ILN_2020 GBV_ILN_2048 GBV_ILN_4036 GBV_ILN_4116 GBV_ILN_4277 AR 16 2009 7 15 12 1175-1179 |
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10.1007/s00542-009-0975-2 doi (DE-627)OLC2034928253 (DE-He213)s00542-009-0975-2-p DE-627 ger DE-627 rakwb eng 620 VZ 510 VZ Jair, D. K. verfasserin aut A novel CMOS process compatible high performance parallel-stacked RF spiral inductor 2009 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer-Verlag 2009 Abstract In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications. CMOS Process Chip Size Electroless Copper Spiral Inductor Metal Width Hsieh, Ming Chun aut Lin, C. S. aut Enthalten in Microsystem technologies Springer-Verlag, 1994 16(2009), 7 vom: 15. Dez., Seite 1175-1179 (DE-627)182644278 (DE-600)1223008-X (DE-576)045302146 0946-7076 nnns volume:16 year:2009 number:7 day:15 month:12 pages:1175-1179 https://doi.org/10.1007/s00542-009-0975-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT SSG-OPC-MAT GBV_ILN_40 GBV_ILN_70 GBV_ILN_95 GBV_ILN_267 GBV_ILN_2018 GBV_ILN_2020 GBV_ILN_2048 GBV_ILN_4036 GBV_ILN_4116 GBV_ILN_4277 AR 16 2009 7 15 12 1175-1179 |
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10.1007/s00542-009-0975-2 doi (DE-627)OLC2034928253 (DE-He213)s00542-009-0975-2-p DE-627 ger DE-627 rakwb eng 620 VZ 510 VZ Jair, D. K. verfasserin aut A novel CMOS process compatible high performance parallel-stacked RF spiral inductor 2009 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer-Verlag 2009 Abstract In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications. CMOS Process Chip Size Electroless Copper Spiral Inductor Metal Width Hsieh, Ming Chun aut Lin, C. S. aut Enthalten in Microsystem technologies Springer-Verlag, 1994 16(2009), 7 vom: 15. Dez., Seite 1175-1179 (DE-627)182644278 (DE-600)1223008-X (DE-576)045302146 0946-7076 nnns volume:16 year:2009 number:7 day:15 month:12 pages:1175-1179 https://doi.org/10.1007/s00542-009-0975-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT SSG-OPC-MAT GBV_ILN_40 GBV_ILN_70 GBV_ILN_95 GBV_ILN_267 GBV_ILN_2018 GBV_ILN_2020 GBV_ILN_2048 GBV_ILN_4036 GBV_ILN_4116 GBV_ILN_4277 AR 16 2009 7 15 12 1175-1179 |
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10.1007/s00542-009-0975-2 doi (DE-627)OLC2034928253 (DE-He213)s00542-009-0975-2-p DE-627 ger DE-627 rakwb eng 620 VZ 510 VZ Jair, D. K. verfasserin aut A novel CMOS process compatible high performance parallel-stacked RF spiral inductor 2009 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer-Verlag 2009 Abstract In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications. CMOS Process Chip Size Electroless Copper Spiral Inductor Metal Width Hsieh, Ming Chun aut Lin, C. S. aut Enthalten in Microsystem technologies Springer-Verlag, 1994 16(2009), 7 vom: 15. Dez., Seite 1175-1179 (DE-627)182644278 (DE-600)1223008-X (DE-576)045302146 0946-7076 nnns volume:16 year:2009 number:7 day:15 month:12 pages:1175-1179 https://doi.org/10.1007/s00542-009-0975-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT SSG-OPC-MAT GBV_ILN_40 GBV_ILN_70 GBV_ILN_95 GBV_ILN_267 GBV_ILN_2018 GBV_ILN_2020 GBV_ILN_2048 GBV_ILN_4036 GBV_ILN_4116 GBV_ILN_4277 AR 16 2009 7 15 12 1175-1179 |
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a novel cmos process compatible high performance parallel-stacked rf spiral inductor |
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A novel CMOS process compatible high performance parallel-stacked RF spiral inductor |
| abstract |
Abstract In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications. © Springer-Verlag 2009 |
| abstractGer |
Abstract In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications. © Springer-Verlag 2009 |
| abstract_unstemmed |
Abstract In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications. © Springer-Verlag 2009 |
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A novel CMOS process compatible high performance parallel-stacked RF spiral inductor |
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https://doi.org/10.1007/s00542-009-0975-2 |
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Hsieh, Ming Chun Lin, C. S. |
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| up_date |
2024-07-03T23:03:16.022Z |
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