Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package
Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Jee, Y. K. [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2009 |
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| Schlagwörter: |
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| Anmerkung: |
© TMS 2009 |
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| Übergeordnetes Werk: |
Enthalten in: Journal of electronic materials - Springer US, 1972, 38(2009), 5 vom: 13. Jan., Seite 685-690 |
|---|---|
| Übergeordnetes Werk: |
volume:38 ; year:2009 ; number:5 ; day:13 ; month:01 ; pages:685-690 |
| Links: |
|---|
| DOI / URN: |
10.1007/s11664-008-0646-6 |
|---|
| Katalog-ID: |
OLC2042308455 |
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| 520 | |a Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias. | ||
| 650 | 4 | |a Chip-stack package | |
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| 650 | 4 | |a through-silicon via | |
| 650 | 4 | |a Zn via | |
| 650 | 4 | |a Sn-Zn via | |
| 700 | 1 | |a Yu, J. |4 aut | |
| 700 | 1 | |a Park, K. W. |4 aut | |
| 700 | 1 | |a Oh, T. S. |4 aut | |
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10.1007/s11664-008-0646-6 doi (DE-627)OLC2042308455 (DE-He213)s11664-008-0646-6-p DE-627 ger DE-627 rakwb eng 670 VZ Jee, Y. K. verfasserin aut Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package 2009 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © TMS 2009 Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias. Chip-stack package system-in-package through-silicon via Zn via Sn-Zn via Yu, J. aut Park, K. W. aut Oh, T. S. aut Enthalten in Journal of electronic materials Springer US, 1972 38(2009), 5 vom: 13. Jan., Seite 685-690 (DE-627)129398233 (DE-600)186069-0 (DE-576)014781387 0361-5235 nnns volume:38 year:2009 number:5 day:13 month:01 pages:685-690 https://doi.org/10.1007/s11664-008-0646-6 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_2006 GBV_ILN_2010 GBV_ILN_2020 GBV_ILN_2021 AR 38 2009 5 13 01 685-690 |
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10.1007/s11664-008-0646-6 doi (DE-627)OLC2042308455 (DE-He213)s11664-008-0646-6-p DE-627 ger DE-627 rakwb eng 670 VZ Jee, Y. K. verfasserin aut Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package 2009 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © TMS 2009 Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias. Chip-stack package system-in-package through-silicon via Zn via Sn-Zn via Yu, J. aut Park, K. W. aut Oh, T. S. aut Enthalten in Journal of electronic materials Springer US, 1972 38(2009), 5 vom: 13. Jan., Seite 685-690 (DE-627)129398233 (DE-600)186069-0 (DE-576)014781387 0361-5235 nnns volume:38 year:2009 number:5 day:13 month:01 pages:685-690 https://doi.org/10.1007/s11664-008-0646-6 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_2006 GBV_ILN_2010 GBV_ILN_2020 GBV_ILN_2021 AR 38 2009 5 13 01 685-690 |
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10.1007/s11664-008-0646-6 doi (DE-627)OLC2042308455 (DE-He213)s11664-008-0646-6-p DE-627 ger DE-627 rakwb eng 670 VZ Jee, Y. K. verfasserin aut Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package 2009 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © TMS 2009 Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias. Chip-stack package system-in-package through-silicon via Zn via Sn-Zn via Yu, J. aut Park, K. W. aut Oh, T. S. aut Enthalten in Journal of electronic materials Springer US, 1972 38(2009), 5 vom: 13. Jan., Seite 685-690 (DE-627)129398233 (DE-600)186069-0 (DE-576)014781387 0361-5235 nnns volume:38 year:2009 number:5 day:13 month:01 pages:685-690 https://doi.org/10.1007/s11664-008-0646-6 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_2006 GBV_ILN_2010 GBV_ILN_2020 GBV_ILN_2021 AR 38 2009 5 13 01 685-690 |
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10.1007/s11664-008-0646-6 doi (DE-627)OLC2042308455 (DE-He213)s11664-008-0646-6-p DE-627 ger DE-627 rakwb eng 670 VZ Jee, Y. K. verfasserin aut Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package 2009 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © TMS 2009 Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias. Chip-stack package system-in-package through-silicon via Zn via Sn-Zn via Yu, J. aut Park, K. W. aut Oh, T. S. aut Enthalten in Journal of electronic materials Springer US, 1972 38(2009), 5 vom: 13. Jan., Seite 685-690 (DE-627)129398233 (DE-600)186069-0 (DE-576)014781387 0361-5235 nnns volume:38 year:2009 number:5 day:13 month:01 pages:685-690 https://doi.org/10.1007/s11664-008-0646-6 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_2006 GBV_ILN_2010 GBV_ILN_2020 GBV_ILN_2021 AR 38 2009 5 13 01 685-690 |
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10.1007/s11664-008-0646-6 doi (DE-627)OLC2042308455 (DE-He213)s11664-008-0646-6-p DE-627 ger DE-627 rakwb eng 670 VZ Jee, Y. K. verfasserin aut Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package 2009 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © TMS 2009 Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias. Chip-stack package system-in-package through-silicon via Zn via Sn-Zn via Yu, J. aut Park, K. W. aut Oh, T. S. aut Enthalten in Journal of electronic materials Springer US, 1972 38(2009), 5 vom: 13. Jan., Seite 685-690 (DE-627)129398233 (DE-600)186069-0 (DE-576)014781387 0361-5235 nnns volume:38 year:2009 number:5 day:13 month:01 pages:685-690 https://doi.org/10.1007/s11664-008-0646-6 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-PHY GBV_ILN_70 GBV_ILN_2004 GBV_ILN_2006 GBV_ILN_2010 GBV_ILN_2020 GBV_ILN_2021 AR 38 2009 5 13 01 685-690 |
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Jee, Y. K. |
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670 |
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zinc and tin-zinc via-filling for the formation of through-silicon vias in a system-in-package |
| title_auth |
Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package |
| abstract |
Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias. © TMS 2009 |
| abstractGer |
Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias. © TMS 2009 |
| abstract_unstemmed |
Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias. © TMS 2009 |
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5 |
| title_short |
Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package |
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