Probabilistic Alias Analysis of Executable Code
Abstract In this paper we present a method for flow-sensitive, context-insensitive probabilistic alias analysis at the assembly level. A memory disambiguation algorithm is also developed for revealing the probability of two registers holding the same memory location. The alias analysis and memory di...
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Gespeichert in:
| Autor*in: |
Lu, Yu-Min [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2010 |
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| Schlagwörter: |
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| Anmerkung: |
© Springer Science+Business Media, LLC 2010 |
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| Übergeordnetes Werk: |
Enthalten in: International journal of parallel programming - Springer US, 1986, 39(2010), 6 vom: 27. Nov., Seite 663-693 |
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| Übergeordnetes Werk: |
volume:39 ; year:2010 ; number:6 ; day:27 ; month:11 ; pages:663-693 |
| Links: |
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| DOI / URN: |
10.1007/s10766-010-0157-y |
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| 520 | |a Abstract In this paper we present a method for flow-sensitive, context-insensitive probabilistic alias analysis at the assembly level. A memory disambiguation algorithm is also developed for revealing the probability of two registers holding the same memory location. The alias analysis and memory disambiguation algorithms are implemented based on the Diablo post-link optimizer. Experimental results show that the technique can estimate the probabilities that registers refer to the same memory address in benchmark programs with an overall average error of about 6.8%. The post-link optimizer can leverage the obtained quantitative information to facilitate aggressive analyses and optimizations. | ||
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10.1007/s10766-010-0157-y doi (DE-627)OLC2044604159 (DE-He213)s10766-010-0157-y-p DE-627 ger DE-627 rakwb eng 070 004 VZ Lu, Yu-Min verfasserin aut Probabilistic Alias Analysis of Executable Code 2010 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2010 Abstract In this paper we present a method for flow-sensitive, context-insensitive probabilistic alias analysis at the assembly level. A memory disambiguation algorithm is also developed for revealing the probability of two registers holding the same memory location. The alias analysis and memory disambiguation algorithms are implemented based on the Diablo post-link optimizer. Experimental results show that the technique can estimate the probabilities that registers refer to the same memory address in benchmark programs with an overall average error of about 6.8%. The post-link optimizer can leverage the obtained quantitative information to facilitate aggressive analyses and optimizations. Alias analysis Compiler Post-link optimizer Optimization Chen, Peng-Sheng aut Enthalten in International journal of parallel programming Springer US, 1986 39(2010), 6 vom: 27. Nov., Seite 663-693 (DE-627)129622028 (DE-600)246656-9 (DE-576)015131793 0885-7458 nnns volume:39 year:2010 number:6 day:27 month:11 pages:663-693 https://doi.org/10.1007/s10766-010-0157-y lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT SSG-OPC-BBI GBV_ILN_22 GBV_ILN_31 GBV_ILN_40 GBV_ILN_70 GBV_ILN_4317 GBV_ILN_4318 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4700 AR 39 2010 6 27 11 663-693 |
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10.1007/s10766-010-0157-y doi (DE-627)OLC2044604159 (DE-He213)s10766-010-0157-y-p DE-627 ger DE-627 rakwb eng 070 004 VZ Lu, Yu-Min verfasserin aut Probabilistic Alias Analysis of Executable Code 2010 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2010 Abstract In this paper we present a method for flow-sensitive, context-insensitive probabilistic alias analysis at the assembly level. A memory disambiguation algorithm is also developed for revealing the probability of two registers holding the same memory location. The alias analysis and memory disambiguation algorithms are implemented based on the Diablo post-link optimizer. Experimental results show that the technique can estimate the probabilities that registers refer to the same memory address in benchmark programs with an overall average error of about 6.8%. The post-link optimizer can leverage the obtained quantitative information to facilitate aggressive analyses and optimizations. Alias analysis Compiler Post-link optimizer Optimization Chen, Peng-Sheng aut Enthalten in International journal of parallel programming Springer US, 1986 39(2010), 6 vom: 27. Nov., Seite 663-693 (DE-627)129622028 (DE-600)246656-9 (DE-576)015131793 0885-7458 nnns volume:39 year:2010 number:6 day:27 month:11 pages:663-693 https://doi.org/10.1007/s10766-010-0157-y lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT SSG-OPC-BBI GBV_ILN_22 GBV_ILN_31 GBV_ILN_40 GBV_ILN_70 GBV_ILN_4317 GBV_ILN_4318 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4700 AR 39 2010 6 27 11 663-693 |
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10.1007/s10766-010-0157-y doi (DE-627)OLC2044604159 (DE-He213)s10766-010-0157-y-p DE-627 ger DE-627 rakwb eng 070 004 VZ Lu, Yu-Min verfasserin aut Probabilistic Alias Analysis of Executable Code 2010 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2010 Abstract In this paper we present a method for flow-sensitive, context-insensitive probabilistic alias analysis at the assembly level. A memory disambiguation algorithm is also developed for revealing the probability of two registers holding the same memory location. The alias analysis and memory disambiguation algorithms are implemented based on the Diablo post-link optimizer. Experimental results show that the technique can estimate the probabilities that registers refer to the same memory address in benchmark programs with an overall average error of about 6.8%. The post-link optimizer can leverage the obtained quantitative information to facilitate aggressive analyses and optimizations. Alias analysis Compiler Post-link optimizer Optimization Chen, Peng-Sheng aut Enthalten in International journal of parallel programming Springer US, 1986 39(2010), 6 vom: 27. Nov., Seite 663-693 (DE-627)129622028 (DE-600)246656-9 (DE-576)015131793 0885-7458 nnns volume:39 year:2010 number:6 day:27 month:11 pages:663-693 https://doi.org/10.1007/s10766-010-0157-y lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT SSG-OPC-BBI GBV_ILN_22 GBV_ILN_31 GBV_ILN_40 GBV_ILN_70 GBV_ILN_4317 GBV_ILN_4318 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4700 AR 39 2010 6 27 11 663-693 |
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10.1007/s10766-010-0157-y doi (DE-627)OLC2044604159 (DE-He213)s10766-010-0157-y-p DE-627 ger DE-627 rakwb eng 070 004 VZ Lu, Yu-Min verfasserin aut Probabilistic Alias Analysis of Executable Code 2010 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2010 Abstract In this paper we present a method for flow-sensitive, context-insensitive probabilistic alias analysis at the assembly level. A memory disambiguation algorithm is also developed for revealing the probability of two registers holding the same memory location. The alias analysis and memory disambiguation algorithms are implemented based on the Diablo post-link optimizer. Experimental results show that the technique can estimate the probabilities that registers refer to the same memory address in benchmark programs with an overall average error of about 6.8%. The post-link optimizer can leverage the obtained quantitative information to facilitate aggressive analyses and optimizations. Alias analysis Compiler Post-link optimizer Optimization Chen, Peng-Sheng aut Enthalten in International journal of parallel programming Springer US, 1986 39(2010), 6 vom: 27. Nov., Seite 663-693 (DE-627)129622028 (DE-600)246656-9 (DE-576)015131793 0885-7458 nnns volume:39 year:2010 number:6 day:27 month:11 pages:663-693 https://doi.org/10.1007/s10766-010-0157-y lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT SSG-OPC-BBI GBV_ILN_22 GBV_ILN_31 GBV_ILN_40 GBV_ILN_70 GBV_ILN_4317 GBV_ILN_4318 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4700 AR 39 2010 6 27 11 663-693 |
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Abstract In this paper we present a method for flow-sensitive, context-insensitive probabilistic alias analysis at the assembly level. A memory disambiguation algorithm is also developed for revealing the probability of two registers holding the same memory location. The alias analysis and memory disambiguation algorithms are implemented based on the Diablo post-link optimizer. Experimental results show that the technique can estimate the probabilities that registers refer to the same memory address in benchmark programs with an overall average error of about 6.8%. The post-link optimizer can leverage the obtained quantitative information to facilitate aggressive analyses and optimizations. © Springer Science+Business Media, LLC 2010 |
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Abstract In this paper we present a method for flow-sensitive, context-insensitive probabilistic alias analysis at the assembly level. A memory disambiguation algorithm is also developed for revealing the probability of two registers holding the same memory location. The alias analysis and memory disambiguation algorithms are implemented based on the Diablo post-link optimizer. Experimental results show that the technique can estimate the probabilities that registers refer to the same memory address in benchmark programs with an overall average error of about 6.8%. The post-link optimizer can leverage the obtained quantitative information to facilitate aggressive analyses and optimizations. © Springer Science+Business Media, LLC 2010 |
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Abstract In this paper we present a method for flow-sensitive, context-insensitive probabilistic alias analysis at the assembly level. A memory disambiguation algorithm is also developed for revealing the probability of two registers holding the same memory location. The alias analysis and memory disambiguation algorithms are implemented based on the Diablo post-link optimizer. Experimental results show that the technique can estimate the probabilities that registers refer to the same memory address in benchmark programs with an overall average error of about 6.8%. The post-link optimizer can leverage the obtained quantitative information to facilitate aggressive analyses and optimizations. © Springer Science+Business Media, LLC 2010 |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">OLC2044604159</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230503080917.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">200820s2010 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s10766-010-0157-y</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC2044604159</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-He213)s10766-010-0157-y-p</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">070</subfield><subfield code="a">004</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Lu, Yu-Min</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Probabilistic Alias Analysis of Executable Code</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2010</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© Springer Science+Business Media, LLC 2010</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract In this paper we present a method for flow-sensitive, context-insensitive probabilistic alias analysis at the assembly level. A memory disambiguation algorithm is also developed for revealing the probability of two registers holding the same memory location. The alias analysis and memory disambiguation algorithms are implemented based on the Diablo post-link optimizer. Experimental results show that the technique can estimate the probabilities that registers refer to the same memory address in benchmark programs with an overall average error of about 6.8%. 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