Removal of Conflicts in Hardware Transactional Memory Systems
Abstract This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing,...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Waliullah, M. M. [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2012 |
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| Schlagwörter: |
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| Anmerkung: |
© Springer Science+Business Media, LLC 2012 |
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| Übergeordnetes Werk: |
Enthalten in: International journal of parallel programming - Springer US, 1986, 42(2012), 1 vom: 10. Aug., Seite 198-218 |
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| Übergeordnetes Werk: |
volume:42 ; year:2012 ; number:1 ; day:10 ; month:08 ; pages:198-218 |
| Links: |
|---|
| DOI / URN: |
10.1007/s10766-012-0210-0 |
|---|
| Katalog-ID: |
OLC2044604787 |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | OLC2044604787 | ||
| 003 | DE-627 | ||
| 005 | 20230503080936.0 | ||
| 007 | tu | ||
| 008 | 200820s2012 xx ||||| 00| ||eng c | ||
| 024 | 7 | |a 10.1007/s10766-012-0210-0 |2 doi | |
| 035 | |a (DE-627)OLC2044604787 | ||
| 035 | |a (DE-He213)s10766-012-0210-0-p | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 082 | 0 | 4 | |a 070 |a 004 |q VZ |
| 100 | 1 | |a Waliullah, M. M. |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a Removal of Conflicts in Hardware Transactional Memory Systems |
| 264 | 1 | |c 2012 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a ohne Hilfsmittel zu benutzen |b n |2 rdamedia | ||
| 338 | |a Band |b nc |2 rdacarrier | ||
| 500 | |a © Springer Science+Business Media, LLC 2012 | ||
| 520 | |a Abstract This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance and energy consumption are improved substantially. | ||
| 650 | 4 | |a Transactional memory | |
| 650 | 4 | |a Contamination misses | |
| 650 | 4 | |a Intermediate checkpointing | |
| 650 | 4 | |a Manycore | |
| 700 | 1 | |a Stenstrom, Per |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t International journal of parallel programming |d Springer US, 1986 |g 42(2012), 1 vom: 10. Aug., Seite 198-218 |w (DE-627)129622028 |w (DE-600)246656-9 |w (DE-576)015131793 |x 0885-7458 |7 nnns |
| 773 | 1 | 8 | |g volume:42 |g year:2012 |g number:1 |g day:10 |g month:08 |g pages:198-218 |
| 856 | 4 | 1 | |u https://doi.org/10.1007/s10766-012-0210-0 |z lizenzpflichtig |3 Volltext |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_OLC | ||
| 912 | |a SSG-OLC-MAT | ||
| 912 | |a SSG-OPC-BBI | ||
| 912 | |a GBV_ILN_22 | ||
| 912 | |a GBV_ILN_70 | ||
| 912 | |a GBV_ILN_4318 | ||
| 912 | |a GBV_ILN_4323 | ||
| 912 | |a GBV_ILN_4700 | ||
| 951 | |a AR | ||
| 952 | |d 42 |j 2012 |e 1 |b 10 |c 08 |h 198-218 | ||
| author_variant |
m m w mm mmw p s ps |
|---|---|
| matchkey_str |
article:08857458:2012----::eoaocnlcsnadaernato |
| hierarchy_sort_str |
2012 |
| publishDate |
2012 |
| allfields |
10.1007/s10766-012-0210-0 doi (DE-627)OLC2044604787 (DE-He213)s10766-012-0210-0-p DE-627 ger DE-627 rakwb eng 070 004 VZ Waliullah, M. M. verfasserin aut Removal of Conflicts in Hardware Transactional Memory Systems 2012 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2012 Abstract This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance and energy consumption are improved substantially. Transactional memory Contamination misses Intermediate checkpointing Manycore Stenstrom, Per aut Enthalten in International journal of parallel programming Springer US, 1986 42(2012), 1 vom: 10. Aug., Seite 198-218 (DE-627)129622028 (DE-600)246656-9 (DE-576)015131793 0885-7458 nnns volume:42 year:2012 number:1 day:10 month:08 pages:198-218 https://doi.org/10.1007/s10766-012-0210-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT SSG-OPC-BBI GBV_ILN_22 GBV_ILN_70 GBV_ILN_4318 GBV_ILN_4323 GBV_ILN_4700 AR 42 2012 1 10 08 198-218 |
| spelling |
10.1007/s10766-012-0210-0 doi (DE-627)OLC2044604787 (DE-He213)s10766-012-0210-0-p DE-627 ger DE-627 rakwb eng 070 004 VZ Waliullah, M. M. verfasserin aut Removal of Conflicts in Hardware Transactional Memory Systems 2012 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2012 Abstract This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance and energy consumption are improved substantially. Transactional memory Contamination misses Intermediate checkpointing Manycore Stenstrom, Per aut Enthalten in International journal of parallel programming Springer US, 1986 42(2012), 1 vom: 10. Aug., Seite 198-218 (DE-627)129622028 (DE-600)246656-9 (DE-576)015131793 0885-7458 nnns volume:42 year:2012 number:1 day:10 month:08 pages:198-218 https://doi.org/10.1007/s10766-012-0210-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT SSG-OPC-BBI GBV_ILN_22 GBV_ILN_70 GBV_ILN_4318 GBV_ILN_4323 GBV_ILN_4700 AR 42 2012 1 10 08 198-218 |
| allfields_unstemmed |
10.1007/s10766-012-0210-0 doi (DE-627)OLC2044604787 (DE-He213)s10766-012-0210-0-p DE-627 ger DE-627 rakwb eng 070 004 VZ Waliullah, M. M. verfasserin aut Removal of Conflicts in Hardware Transactional Memory Systems 2012 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2012 Abstract This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance and energy consumption are improved substantially. Transactional memory Contamination misses Intermediate checkpointing Manycore Stenstrom, Per aut Enthalten in International journal of parallel programming Springer US, 1986 42(2012), 1 vom: 10. Aug., Seite 198-218 (DE-627)129622028 (DE-600)246656-9 (DE-576)015131793 0885-7458 nnns volume:42 year:2012 number:1 day:10 month:08 pages:198-218 https://doi.org/10.1007/s10766-012-0210-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT SSG-OPC-BBI GBV_ILN_22 GBV_ILN_70 GBV_ILN_4318 GBV_ILN_4323 GBV_ILN_4700 AR 42 2012 1 10 08 198-218 |
| allfieldsGer |
10.1007/s10766-012-0210-0 doi (DE-627)OLC2044604787 (DE-He213)s10766-012-0210-0-p DE-627 ger DE-627 rakwb eng 070 004 VZ Waliullah, M. M. verfasserin aut Removal of Conflicts in Hardware Transactional Memory Systems 2012 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2012 Abstract This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance and energy consumption are improved substantially. Transactional memory Contamination misses Intermediate checkpointing Manycore Stenstrom, Per aut Enthalten in International journal of parallel programming Springer US, 1986 42(2012), 1 vom: 10. Aug., Seite 198-218 (DE-627)129622028 (DE-600)246656-9 (DE-576)015131793 0885-7458 nnns volume:42 year:2012 number:1 day:10 month:08 pages:198-218 https://doi.org/10.1007/s10766-012-0210-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT SSG-OPC-BBI GBV_ILN_22 GBV_ILN_70 GBV_ILN_4318 GBV_ILN_4323 GBV_ILN_4700 AR 42 2012 1 10 08 198-218 |
| allfieldsSound |
10.1007/s10766-012-0210-0 doi (DE-627)OLC2044604787 (DE-He213)s10766-012-0210-0-p DE-627 ger DE-627 rakwb eng 070 004 VZ Waliullah, M. M. verfasserin aut Removal of Conflicts in Hardware Transactional Memory Systems 2012 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC 2012 Abstract This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance and energy consumption are improved substantially. Transactional memory Contamination misses Intermediate checkpointing Manycore Stenstrom, Per aut Enthalten in International journal of parallel programming Springer US, 1986 42(2012), 1 vom: 10. Aug., Seite 198-218 (DE-627)129622028 (DE-600)246656-9 (DE-576)015131793 0885-7458 nnns volume:42 year:2012 number:1 day:10 month:08 pages:198-218 https://doi.org/10.1007/s10766-012-0210-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT SSG-OPC-BBI GBV_ILN_22 GBV_ILN_70 GBV_ILN_4318 GBV_ILN_4323 GBV_ILN_4700 AR 42 2012 1 10 08 198-218 |
| language |
English |
| source |
Enthalten in International journal of parallel programming 42(2012), 1 vom: 10. Aug., Seite 198-218 volume:42 year:2012 number:1 day:10 month:08 pages:198-218 |
| sourceStr |
Enthalten in International journal of parallel programming 42(2012), 1 vom: 10. Aug., Seite 198-218 volume:42 year:2012 number:1 day:10 month:08 pages:198-218 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Transactional memory Contamination misses Intermediate checkpointing Manycore |
| dewey-raw |
070 |
| isfreeaccess_bool |
false |
| container_title |
International journal of parallel programming |
| authorswithroles_txt_mv |
Waliullah, M. M. @@aut@@ Stenstrom, Per @@aut@@ |
| publishDateDaySort_date |
2012-08-10T00:00:00Z |
| hierarchy_top_id |
129622028 |
| dewey-sort |
270 |
| id |
OLC2044604787 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">OLC2044604787</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230503080936.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">200820s2012 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s10766-012-0210-0</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC2044604787</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-He213)s10766-012-0210-0-p</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">070</subfield><subfield code="a">004</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Waliullah, M. M.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Removal of Conflicts in Hardware Transactional Memory Systems</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2012</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© Springer Science+Business Media, LLC 2012</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance and energy consumption are improved substantially.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Transactional memory</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Contamination misses</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Intermediate checkpointing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Manycore</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Stenstrom, Per</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">International journal of parallel programming</subfield><subfield code="d">Springer US, 1986</subfield><subfield code="g">42(2012), 1 vom: 10. Aug., Seite 198-218</subfield><subfield code="w">(DE-627)129622028</subfield><subfield code="w">(DE-600)246656-9</subfield><subfield code="w">(DE-576)015131793</subfield><subfield code="x">0885-7458</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:42</subfield><subfield code="g">year:2012</subfield><subfield code="g">number:1</subfield><subfield code="g">day:10</subfield><subfield code="g">month:08</subfield><subfield code="g">pages:198-218</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">https://doi.org/10.1007/s10766-012-0210-0</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-MAT</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OPC-BBI</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_22</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4318</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4323</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4700</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">42</subfield><subfield code="j">2012</subfield><subfield code="e">1</subfield><subfield code="b">10</subfield><subfield code="c">08</subfield><subfield code="h">198-218</subfield></datafield></record></collection>
|
| author |
Waliullah, M. M. |
| spellingShingle |
Waliullah, M. M. ddc 070 misc Transactional memory misc Contamination misses misc Intermediate checkpointing misc Manycore Removal of Conflicts in Hardware Transactional Memory Systems |
| authorStr |
Waliullah, M. M. |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)129622028 |
| format |
Article |
| dewey-ones |
070 - News media, journalism & publishing 004 - Data processing & computer science |
| delete_txt_mv |
keep |
| author_role |
aut aut |
| collection |
OLC |
| remote_str |
false |
| illustrated |
Not Illustrated |
| issn |
0885-7458 |
| topic_title |
070 004 VZ Removal of Conflicts in Hardware Transactional Memory Systems Transactional memory Contamination misses Intermediate checkpointing Manycore |
| topic |
ddc 070 misc Transactional memory misc Contamination misses misc Intermediate checkpointing misc Manycore |
| topic_unstemmed |
ddc 070 misc Transactional memory misc Contamination misses misc Intermediate checkpointing misc Manycore |
| topic_browse |
ddc 070 misc Transactional memory misc Contamination misses misc Intermediate checkpointing misc Manycore |
| format_facet |
Aufsätze Gedruckte Aufsätze |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
nc |
| hierarchy_parent_title |
International journal of parallel programming |
| hierarchy_parent_id |
129622028 |
| dewey-tens |
070 - News media, journalism & publishing 000 - Computer science, knowledge & systems |
| hierarchy_top_title |
International journal of parallel programming |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)129622028 (DE-600)246656-9 (DE-576)015131793 |
| title |
Removal of Conflicts in Hardware Transactional Memory Systems |
| ctrlnum |
(DE-627)OLC2044604787 (DE-He213)s10766-012-0210-0-p |
| title_full |
Removal of Conflicts in Hardware Transactional Memory Systems |
| author_sort |
Waliullah, M. M. |
| journal |
International journal of parallel programming |
| journalStr |
International journal of parallel programming |
| lang_code |
eng |
| isOA_bool |
false |
| dewey-hundreds |
000 - Computer science, information & general works |
| recordtype |
marc |
| publishDateSort |
2012 |
| contenttype_str_mv |
txt |
| container_start_page |
198 |
| author_browse |
Waliullah, M. M. Stenstrom, Per |
| container_volume |
42 |
| class |
070 004 VZ |
| format_se |
Aufsätze |
| author-letter |
Waliullah, M. M. |
| doi_str_mv |
10.1007/s10766-012-0210-0 |
| dewey-full |
070 004 |
| title_sort |
removal of conflicts in hardware transactional memory systems |
| title_auth |
Removal of Conflicts in Hardware Transactional Memory Systems |
| abstract |
Abstract This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance and energy consumption are improved substantially. © Springer Science+Business Media, LLC 2012 |
| abstractGer |
Abstract This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance and energy consumption are improved substantially. © Springer Science+Business Media, LLC 2012 |
| abstract_unstemmed |
Abstract This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance and energy consumption are improved substantially. © Springer Science+Business Media, LLC 2012 |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-MAT SSG-OPC-BBI GBV_ILN_22 GBV_ILN_70 GBV_ILN_4318 GBV_ILN_4323 GBV_ILN_4700 |
| container_issue |
1 |
| title_short |
Removal of Conflicts in Hardware Transactional Memory Systems |
| url |
https://doi.org/10.1007/s10766-012-0210-0 |
| remote_bool |
false |
| author2 |
Stenstrom, Per |
| author2Str |
Stenstrom, Per |
| ppnlink |
129622028 |
| mediatype_str_mv |
n |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| doi_str |
10.1007/s10766-012-0210-0 |
| up_date |
2024-07-04T00:07:55.780Z |
| _version_ |
1803604905984786432 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">OLC2044604787</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230503080936.0</controlfield><controlfield tag="007">tu</controlfield><controlfield tag="008">200820s2012 xx ||||| 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s10766-012-0210-0</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)OLC2044604787</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-He213)s10766-012-0210-0-p</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">070</subfield><subfield code="a">004</subfield><subfield code="q">VZ</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Waliullah, M. M.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Removal of Conflicts in Hardware Transactional Memory Systems</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2012</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">ohne Hilfsmittel zu benutzen</subfield><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Band</subfield><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© Springer Science+Business Media, LLC 2012</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This paper analyzes the sources of performance losses in hardware transactional memory and investigates techniques to reduce the losses. It dissects the root causes of data conflicts in hardware transactional memory systems (HTM) into four classes of conflicts: true sharing, false sharing, silent store, and write-write conflicts. These conflicts can cause performance and energy losses due to aborts and extra communication. To quantify losses, the paper proposes the 5C cache-miss classification model that extends the well-established 4C model with a new class of cache misses known as contamination misses. The paper also contributes with two techniques for removal of data conflicts: One for removal of false sharing conflicts and another for removal of silent store conflicts. In addition, it revisits and adapts a technique that is able to reduce losses due to both true and false conflicts. All of the proposed techniques can be accommodated in a lazy versioning and lazy conflict resolution HTM built on top of a MESI cache-coherence infrastructure with quite modest extensions. Their ability to reduce performance is quantitatively established, individually as well as in combination. Performance and energy consumption are improved substantially.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Transactional memory</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Contamination misses</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Intermediate checkpointing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Manycore</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Stenstrom, Per</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">International journal of parallel programming</subfield><subfield code="d">Springer US, 1986</subfield><subfield code="g">42(2012), 1 vom: 10. Aug., Seite 198-218</subfield><subfield code="w">(DE-627)129622028</subfield><subfield code="w">(DE-600)246656-9</subfield><subfield code="w">(DE-576)015131793</subfield><subfield code="x">0885-7458</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:42</subfield><subfield code="g">year:2012</subfield><subfield code="g">number:1</subfield><subfield code="g">day:10</subfield><subfield code="g">month:08</subfield><subfield code="g">pages:198-218</subfield></datafield><datafield tag="856" ind1="4" ind2="1"><subfield code="u">https://doi.org/10.1007/s10766-012-0210-0</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_OLC</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OLC-MAT</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SSG-OPC-BBI</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_22</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4318</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4323</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4700</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">42</subfield><subfield code="j">2012</subfield><subfield code="e">1</subfield><subfield code="b">10</subfield><subfield code="c">08</subfield><subfield code="h">198-218</subfield></datafield></record></collection>
|
| score |
7.3988447 |