A Systolic Design Methodology with Application to Full-Search Block-Matching Architectures
Abstract We present a systematic methodology to support the design tradeoffs of array processors in several emerging issues, such as (1) high performance and high flexibility, (2) low cost, low power, (3) efficient memory usage, and (4) system-on-a-chip or the ease of system integration. This method...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Chen, Yen-Kuang [verfasserIn] |
|---|
| Format: |
Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
1998 |
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| Schlagwörter: |
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| Anmerkung: |
© Kluwer Academic Publishers 1998 |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Kluwer Academic Publishers, 1989, 19(1998), 1 vom: 01. Mai, Seite 51-77 |
|---|---|
| Übergeordnetes Werk: |
volume:19 ; year:1998 ; number:1 ; day:01 ; month:05 ; pages:51-77 |
| Links: |
|---|
| DOI / URN: |
10.1023/A:1008012332212 |
|---|
| Katalog-ID: |
OLC2062082878 |
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10.1023/A:1008012332212 doi (DE-627)OLC2062082878 (DE-He213)A:1008012332212-p DE-627 ger DE-627 rakwb eng 620 VZ Chen, Yen-Kuang verfasserin aut A Systolic Design Methodology with Application to Full-Search Block-Matching Architectures 1998 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Kluwer Academic Publishers 1998 Abstract We present a systematic methodology to support the design tradeoffs of array processors in several emerging issues, such as (1) high performance and high flexibility, (2) low cost, low power, (3) efficient memory usage, and (4) system-on-a-chip or the ease of system integration. This methodology is algebraic based, so it can cope with high-dimensional data dependence. The methodology consists of some transformation rules of data dependency graphs for facilitating flexible array designs. For example, two common partitioning approaches, LPGS and LSGP, could be unified under the methodology. It supports the design of high-speed and massively parallel processor arrays with efficient memory usage. More specifically, it leads to a novel systolic cache architecture comprising of shift registers only (cache without tags). To demonstrate how the methodology works, we have presented several systolic design examples based on the block-matching motion estimation algorithm (BMA). By multiprojecting a 4D DG of the BMA to 2D mesh, we can reconstruct several existing array processors. By multiprojecting a 6D DG of the BMA, a novel 2D systolic array can be derived that features significantly improved rates in data reusability (96%) and processor utilization (99%). Systolic Array Search Window Current Block Array Processor VLSI Signal Processing Kung, S.Y. aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Kluwer Academic Publishers, 1989 19(1998), 1 vom: 01. Mai, Seite 51-77 (DE-627)130761508 (DE-600)1000618-7 (DE-576)02508416X 0922-5773 nnns volume:19 year:1998 number:1 day:01 month:05 pages:51-77 https://doi.org/10.1023/A:1008012332212 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC SSG-OLC-MAT GBV_ILN_70 GBV_ILN_2006 GBV_ILN_2020 GBV_ILN_2244 GBV_ILN_4318 GBV_ILN_4319 AR 19 1998 1 01 05 51-77 |
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A Systolic Design Methodology with Application to Full-Search Block-Matching Architectures |
| abstract |
Abstract We present a systematic methodology to support the design tradeoffs of array processors in several emerging issues, such as (1) high performance and high flexibility, (2) low cost, low power, (3) efficient memory usage, and (4) system-on-a-chip or the ease of system integration. This methodology is algebraic based, so it can cope with high-dimensional data dependence. The methodology consists of some transformation rules of data dependency graphs for facilitating flexible array designs. For example, two common partitioning approaches, LPGS and LSGP, could be unified under the methodology. It supports the design of high-speed and massively parallel processor arrays with efficient memory usage. More specifically, it leads to a novel systolic cache architecture comprising of shift registers only (cache without tags). To demonstrate how the methodology works, we have presented several systolic design examples based on the block-matching motion estimation algorithm (BMA). By multiprojecting a 4D DG of the BMA to 2D mesh, we can reconstruct several existing array processors. By multiprojecting a 6D DG of the BMA, a novel 2D systolic array can be derived that features significantly improved rates in data reusability (96%) and processor utilization (99%). © Kluwer Academic Publishers 1998 |
| abstractGer |
Abstract We present a systematic methodology to support the design tradeoffs of array processors in several emerging issues, such as (1) high performance and high flexibility, (2) low cost, low power, (3) efficient memory usage, and (4) system-on-a-chip or the ease of system integration. This methodology is algebraic based, so it can cope with high-dimensional data dependence. The methodology consists of some transformation rules of data dependency graphs for facilitating flexible array designs. For example, two common partitioning approaches, LPGS and LSGP, could be unified under the methodology. It supports the design of high-speed and massively parallel processor arrays with efficient memory usage. More specifically, it leads to a novel systolic cache architecture comprising of shift registers only (cache without tags). To demonstrate how the methodology works, we have presented several systolic design examples based on the block-matching motion estimation algorithm (BMA). By multiprojecting a 4D DG of the BMA to 2D mesh, we can reconstruct several existing array processors. By multiprojecting a 6D DG of the BMA, a novel 2D systolic array can be derived that features significantly improved rates in data reusability (96%) and processor utilization (99%). © Kluwer Academic Publishers 1998 |
| abstract_unstemmed |
Abstract We present a systematic methodology to support the design tradeoffs of array processors in several emerging issues, such as (1) high performance and high flexibility, (2) low cost, low power, (3) efficient memory usage, and (4) system-on-a-chip or the ease of system integration. This methodology is algebraic based, so it can cope with high-dimensional data dependence. The methodology consists of some transformation rules of data dependency graphs for facilitating flexible array designs. For example, two common partitioning approaches, LPGS and LSGP, could be unified under the methodology. It supports the design of high-speed and massively parallel processor arrays with efficient memory usage. More specifically, it leads to a novel systolic cache architecture comprising of shift registers only (cache without tags). To demonstrate how the methodology works, we have presented several systolic design examples based on the block-matching motion estimation algorithm (BMA). By multiprojecting a 4D DG of the BMA to 2D mesh, we can reconstruct several existing array processors. By multiprojecting a 6D DG of the BMA, a novel 2D systolic array can be derived that features significantly improved rates in data reusability (96%) and processor utilization (99%). © Kluwer Academic Publishers 1998 |
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| title_short |
A Systolic Design Methodology with Application to Full-Search Block-Matching Architectures |
| url |
https://doi.org/10.1023/A:1008012332212 |
| remote_bool |
false |
| author2 |
Kung, S.Y. |
| author2Str |
Kung, S.Y. |
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| doi_str |
10.1023/A:1008012332212 |
| up_date |
2024-07-03T13:40:26.730Z |
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7.399208 |