Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder
Abstract The delay owing to the generation of odd multiples $$(\pm \,3)$$ in Radix-8 Booth recoding is minimized in this paper using carry resist adder (CRA). CRA is intentionally developed for performing the exact addition of $$\pm \,1$$ and $$\pm \,2$$ without carry propagation. The theoretical de...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Nesam, J. Jean Jenifer [verfasserIn] |
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| Format: |
Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2020 |
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| Schlagwörter: |
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| Anmerkung: |
© Springer Science+Business Media, LLC, part of Springer Nature 2020 |
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| Übergeordnetes Werk: |
Enthalten in: Circuits, systems and signal processing - Springer US, 1982, 40(2020), 4 vom: 06. Okt., Seite 1832-1851 |
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| Übergeordnetes Werk: |
volume:40 ; year:2020 ; number:4 ; day:06 ; month:10 ; pages:1832-1851 |
| Links: |
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| DOI / URN: |
10.1007/s00034-020-01559-8 |
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OLC2124298135 |
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| 520 | |a Abstract The delay owing to the generation of odd multiples $$(\pm \,3)$$ in Radix-8 Booth recoding is minimized in this paper using carry resist adder (CRA). CRA is intentionally developed for performing the exact addition of $$\pm \,1$$ and $$\pm \,2$$ without carry propagation. The theoretical delay analysis proves that the 8-bit CRA reduces 86.26% of delay when compared to the conventional Carry Propagate Addition (CPA) methods. Subsequently, the relative comparisons of CRA with various approximation-based recoding show that the CRA consumes fewer area, power and critical path delay. Further, the $$8\times 8$$ and $$16\times 16$$ signed binary multiplication using CRA-based Radix-8 Booth recoder is developed and synthesized on TSMC 65nm CMOS standard cell library. Also, the trade-off between area, power, delay and accuracy is verified for the proposed design using truncation. Finally, the CRA-based truncated Radix-8 Booth $$8\times 8$$ multiplier is applied to the color space conversion for quantifying its amicability in imaging. The PSNR and MSE are used to evaluate the quality of the resultant image and show better performance than other existing approximated as well as truncated Radix-8 Booth multipliers. | ||
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10.1007/s00034-020-01559-8 doi (DE-627)OLC2124298135 (DE-He213)s00034-020-01559-8-p DE-627 ger DE-627 rakwb eng 600 VZ Nesam, J. Jean Jenifer verfasserin aut Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder 2020 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC, part of Springer Nature 2020 Abstract The delay owing to the generation of odd multiples $$(\pm \,3)$$ in Radix-8 Booth recoding is minimized in this paper using carry resist adder (CRA). CRA is intentionally developed for performing the exact addition of $$\pm \,1$$ and $$\pm \,2$$ without carry propagation. The theoretical delay analysis proves that the 8-bit CRA reduces 86.26% of delay when compared to the conventional Carry Propagate Addition (CPA) methods. Subsequently, the relative comparisons of CRA with various approximation-based recoding show that the CRA consumes fewer area, power and critical path delay. Further, the $$8\times 8$$ and $$16\times 16$$ signed binary multiplication using CRA-based Radix-8 Booth recoder is developed and synthesized on TSMC 65nm CMOS standard cell library. Also, the trade-off between area, power, delay and accuracy is verified for the proposed design using truncation. Finally, the CRA-based truncated Radix-8 Booth $$8\times 8$$ multiplier is applied to the color space conversion for quantifying its amicability in imaging. The PSNR and MSE are used to evaluate the quality of the resultant image and show better performance than other existing approximated as well as truncated Radix-8 Booth multipliers. Radix-8 Booth Carry resist adder (CRA) Exact Booth recoding Minimized delay adder Truncated multiplier Ganesh, S. Sankar aut Enthalten in Circuits, systems and signal processing Springer US, 1982 40(2020), 4 vom: 06. Okt., Seite 1832-1851 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:40 year:2020 number:4 day:06 month:10 pages:1832-1851 https://doi.org/10.1007/s00034-020-01559-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_2244 AR 40 2020 4 06 10 1832-1851 |
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10.1007/s00034-020-01559-8 doi (DE-627)OLC2124298135 (DE-He213)s00034-020-01559-8-p DE-627 ger DE-627 rakwb eng 600 VZ Nesam, J. Jean Jenifer verfasserin aut Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder 2020 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC, part of Springer Nature 2020 Abstract The delay owing to the generation of odd multiples $$(\pm \,3)$$ in Radix-8 Booth recoding is minimized in this paper using carry resist adder (CRA). CRA is intentionally developed for performing the exact addition of $$\pm \,1$$ and $$\pm \,2$$ without carry propagation. The theoretical delay analysis proves that the 8-bit CRA reduces 86.26% of delay when compared to the conventional Carry Propagate Addition (CPA) methods. Subsequently, the relative comparisons of CRA with various approximation-based recoding show that the CRA consumes fewer area, power and critical path delay. Further, the $$8\times 8$$ and $$16\times 16$$ signed binary multiplication using CRA-based Radix-8 Booth recoder is developed and synthesized on TSMC 65nm CMOS standard cell library. Also, the trade-off between area, power, delay and accuracy is verified for the proposed design using truncation. Finally, the CRA-based truncated Radix-8 Booth $$8\times 8$$ multiplier is applied to the color space conversion for quantifying its amicability in imaging. The PSNR and MSE are used to evaluate the quality of the resultant image and show better performance than other existing approximated as well as truncated Radix-8 Booth multipliers. Radix-8 Booth Carry resist adder (CRA) Exact Booth recoding Minimized delay adder Truncated multiplier Ganesh, S. Sankar aut Enthalten in Circuits, systems and signal processing Springer US, 1982 40(2020), 4 vom: 06. Okt., Seite 1832-1851 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:40 year:2020 number:4 day:06 month:10 pages:1832-1851 https://doi.org/10.1007/s00034-020-01559-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_2244 AR 40 2020 4 06 10 1832-1851 |
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10.1007/s00034-020-01559-8 doi (DE-627)OLC2124298135 (DE-He213)s00034-020-01559-8-p DE-627 ger DE-627 rakwb eng 600 VZ Nesam, J. Jean Jenifer verfasserin aut Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder 2020 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC, part of Springer Nature 2020 Abstract The delay owing to the generation of odd multiples $$(\pm \,3)$$ in Radix-8 Booth recoding is minimized in this paper using carry resist adder (CRA). CRA is intentionally developed for performing the exact addition of $$\pm \,1$$ and $$\pm \,2$$ without carry propagation. The theoretical delay analysis proves that the 8-bit CRA reduces 86.26% of delay when compared to the conventional Carry Propagate Addition (CPA) methods. Subsequently, the relative comparisons of CRA with various approximation-based recoding show that the CRA consumes fewer area, power and critical path delay. Further, the $$8\times 8$$ and $$16\times 16$$ signed binary multiplication using CRA-based Radix-8 Booth recoder is developed and synthesized on TSMC 65nm CMOS standard cell library. Also, the trade-off between area, power, delay and accuracy is verified for the proposed design using truncation. Finally, the CRA-based truncated Radix-8 Booth $$8\times 8$$ multiplier is applied to the color space conversion for quantifying its amicability in imaging. The PSNR and MSE are used to evaluate the quality of the resultant image and show better performance than other existing approximated as well as truncated Radix-8 Booth multipliers. Radix-8 Booth Carry resist adder (CRA) Exact Booth recoding Minimized delay adder Truncated multiplier Ganesh, S. Sankar aut Enthalten in Circuits, systems and signal processing Springer US, 1982 40(2020), 4 vom: 06. Okt., Seite 1832-1851 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:40 year:2020 number:4 day:06 month:10 pages:1832-1851 https://doi.org/10.1007/s00034-020-01559-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_2244 AR 40 2020 4 06 10 1832-1851 |
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10.1007/s00034-020-01559-8 doi (DE-627)OLC2124298135 (DE-He213)s00034-020-01559-8-p DE-627 ger DE-627 rakwb eng 600 VZ Nesam, J. Jean Jenifer verfasserin aut Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder 2020 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC, part of Springer Nature 2020 Abstract The delay owing to the generation of odd multiples $$(\pm \,3)$$ in Radix-8 Booth recoding is minimized in this paper using carry resist adder (CRA). CRA is intentionally developed for performing the exact addition of $$\pm \,1$$ and $$\pm \,2$$ without carry propagation. The theoretical delay analysis proves that the 8-bit CRA reduces 86.26% of delay when compared to the conventional Carry Propagate Addition (CPA) methods. Subsequently, the relative comparisons of CRA with various approximation-based recoding show that the CRA consumes fewer area, power and critical path delay. Further, the $$8\times 8$$ and $$16\times 16$$ signed binary multiplication using CRA-based Radix-8 Booth recoder is developed and synthesized on TSMC 65nm CMOS standard cell library. Also, the trade-off between area, power, delay and accuracy is verified for the proposed design using truncation. Finally, the CRA-based truncated Radix-8 Booth $$8\times 8$$ multiplier is applied to the color space conversion for quantifying its amicability in imaging. The PSNR and MSE are used to evaluate the quality of the resultant image and show better performance than other existing approximated as well as truncated Radix-8 Booth multipliers. Radix-8 Booth Carry resist adder (CRA) Exact Booth recoding Minimized delay adder Truncated multiplier Ganesh, S. Sankar aut Enthalten in Circuits, systems and signal processing Springer US, 1982 40(2020), 4 vom: 06. Okt., Seite 1832-1851 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:40 year:2020 number:4 day:06 month:10 pages:1832-1851 https://doi.org/10.1007/s00034-020-01559-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_2244 AR 40 2020 4 06 10 1832-1851 |
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10.1007/s00034-020-01559-8 doi (DE-627)OLC2124298135 (DE-He213)s00034-020-01559-8-p DE-627 ger DE-627 rakwb eng 600 VZ Nesam, J. Jean Jenifer verfasserin aut Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder 2020 Text txt rdacontent ohne Hilfsmittel zu benutzen n rdamedia Band nc rdacarrier © Springer Science+Business Media, LLC, part of Springer Nature 2020 Abstract The delay owing to the generation of odd multiples $$(\pm \,3)$$ in Radix-8 Booth recoding is minimized in this paper using carry resist adder (CRA). CRA is intentionally developed for performing the exact addition of $$\pm \,1$$ and $$\pm \,2$$ without carry propagation. The theoretical delay analysis proves that the 8-bit CRA reduces 86.26% of delay when compared to the conventional Carry Propagate Addition (CPA) methods. Subsequently, the relative comparisons of CRA with various approximation-based recoding show that the CRA consumes fewer area, power and critical path delay. Further, the $$8\times 8$$ and $$16\times 16$$ signed binary multiplication using CRA-based Radix-8 Booth recoder is developed and synthesized on TSMC 65nm CMOS standard cell library. Also, the trade-off between area, power, delay and accuracy is verified for the proposed design using truncation. Finally, the CRA-based truncated Radix-8 Booth $$8\times 8$$ multiplier is applied to the color space conversion for quantifying its amicability in imaging. The PSNR and MSE are used to evaluate the quality of the resultant image and show better performance than other existing approximated as well as truncated Radix-8 Booth multipliers. Radix-8 Booth Carry resist adder (CRA) Exact Booth recoding Minimized delay adder Truncated multiplier Ganesh, S. Sankar aut Enthalten in Circuits, systems and signal processing Springer US, 1982 40(2020), 4 vom: 06. Okt., Seite 1832-1851 (DE-627)130312134 (DE-600)588684-3 (DE-576)015889939 0278-081X nnns volume:40 year:2020 number:4 day:06 month:10 pages:1832-1851 https://doi.org/10.1007/s00034-020-01559-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_OLC SSG-OLC-TEC GBV_ILN_2244 AR 40 2020 4 06 10 1832-1851 |
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Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder |
| abstract |
Abstract The delay owing to the generation of odd multiples $$(\pm \,3)$$ in Radix-8 Booth recoding is minimized in this paper using carry resist adder (CRA). CRA is intentionally developed for performing the exact addition of $$\pm \,1$$ and $$\pm \,2$$ without carry propagation. The theoretical delay analysis proves that the 8-bit CRA reduces 86.26% of delay when compared to the conventional Carry Propagate Addition (CPA) methods. Subsequently, the relative comparisons of CRA with various approximation-based recoding show that the CRA consumes fewer area, power and critical path delay. Further, the $$8\times 8$$ and $$16\times 16$$ signed binary multiplication using CRA-based Radix-8 Booth recoder is developed and synthesized on TSMC 65nm CMOS standard cell library. Also, the trade-off between area, power, delay and accuracy is verified for the proposed design using truncation. Finally, the CRA-based truncated Radix-8 Booth $$8\times 8$$ multiplier is applied to the color space conversion for quantifying its amicability in imaging. The PSNR and MSE are used to evaluate the quality of the resultant image and show better performance than other existing approximated as well as truncated Radix-8 Booth multipliers. © Springer Science+Business Media, LLC, part of Springer Nature 2020 |
| abstractGer |
Abstract The delay owing to the generation of odd multiples $$(\pm \,3)$$ in Radix-8 Booth recoding is minimized in this paper using carry resist adder (CRA). CRA is intentionally developed for performing the exact addition of $$\pm \,1$$ and $$\pm \,2$$ without carry propagation. The theoretical delay analysis proves that the 8-bit CRA reduces 86.26% of delay when compared to the conventional Carry Propagate Addition (CPA) methods. Subsequently, the relative comparisons of CRA with various approximation-based recoding show that the CRA consumes fewer area, power and critical path delay. Further, the $$8\times 8$$ and $$16\times 16$$ signed binary multiplication using CRA-based Radix-8 Booth recoder is developed and synthesized on TSMC 65nm CMOS standard cell library. Also, the trade-off between area, power, delay and accuracy is verified for the proposed design using truncation. Finally, the CRA-based truncated Radix-8 Booth $$8\times 8$$ multiplier is applied to the color space conversion for quantifying its amicability in imaging. The PSNR and MSE are used to evaluate the quality of the resultant image and show better performance than other existing approximated as well as truncated Radix-8 Booth multipliers. © Springer Science+Business Media, LLC, part of Springer Nature 2020 |
| abstract_unstemmed |
Abstract The delay owing to the generation of odd multiples $$(\pm \,3)$$ in Radix-8 Booth recoding is minimized in this paper using carry resist adder (CRA). CRA is intentionally developed for performing the exact addition of $$\pm \,1$$ and $$\pm \,2$$ without carry propagation. The theoretical delay analysis proves that the 8-bit CRA reduces 86.26% of delay when compared to the conventional Carry Propagate Addition (CPA) methods. Subsequently, the relative comparisons of CRA with various approximation-based recoding show that the CRA consumes fewer area, power and critical path delay. Further, the $$8\times 8$$ and $$16\times 16$$ signed binary multiplication using CRA-based Radix-8 Booth recoder is developed and synthesized on TSMC 65nm CMOS standard cell library. Also, the trade-off between area, power, delay and accuracy is verified for the proposed design using truncation. Finally, the CRA-based truncated Radix-8 Booth $$8\times 8$$ multiplier is applied to the color space conversion for quantifying its amicability in imaging. The PSNR and MSE are used to evaluate the quality of the resultant image and show better performance than other existing approximated as well as truncated Radix-8 Booth multipliers. © Springer Science+Business Media, LLC, part of Springer Nature 2020 |
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| title_short |
Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder |
| url |
https://doi.org/10.1007/s00034-020-01559-8 |
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| author2 |
Ganesh, S. Sankar |
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| doi_str |
10.1007/s00034-020-01559-8 |
| up_date |
2024-07-03T22:57:22.264Z |
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7.399579 |