Phase Interpolator with Improved Linearity
Abstract An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with p...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Souliotis, George [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2015 |
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| Schlagwörter: |
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| Anmerkung: |
© Springer Science+Business Media New York 2015 |
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| Übergeordnetes Werk: |
Enthalten in: Circuits, systems and signal processing - Boston, Mass. : Birkhäuser, 1982, 35(2015), 2 vom: 29. Mai, Seite 367-383 |
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| Übergeordnetes Werk: |
volume:35 ; year:2015 ; number:2 ; day:29 ; month:05 ; pages:367-383 |
| Links: |
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| DOI / URN: |
10.1007/s00034-015-0082-9 |
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| Katalog-ID: |
SPR000540064 |
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| 520 | |a Abstract An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with post-layout simulations using a well-established CMOS 65 nm technology and transistors with standard threshold voltages. The clock frequency is at 2.5 GHz and the core voltage supply at 1.2 V. Its low phase noise makes the circuit suitable for high-speed systems where low jitter performance is required. | ||
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| 650 | 4 | |a Clock and data recovery |7 (dpeaa)DE-He213 | |
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| 700 | 1 | |a Plessas, Fotis |4 aut | |
| 700 | 1 | |a Terzopoulos, Nikolaos |4 aut | |
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10.1007/s00034-015-0082-9 doi (DE-627)SPR000540064 (SPR)s00034-015-0082-9-e DE-627 ger DE-627 rakwb eng Souliotis, George verfasserin aut Phase Interpolator with Improved Linearity 2015 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Springer Science+Business Media New York 2015 Abstract An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with post-layout simulations using a well-established CMOS 65 nm technology and transistors with standard threshold voltages. The clock frequency is at 2.5 GHz and the core voltage supply at 1.2 V. Its low phase noise makes the circuit suitable for high-speed systems where low jitter performance is required. Phase interpolator (dpeaa)DE-He213 Clock and data recovery (dpeaa)DE-He213 SerDes (dpeaa)DE-He213 Laoudias, Costas aut Plessas, Fotis aut Terzopoulos, Nikolaos aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 35(2015), 2 vom: 29. Mai, Seite 367-383 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:35 year:2015 number:2 day:29 month:05 pages:367-383 https://dx.doi.org/10.1007/s00034-015-0082-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 35 2015 2 29 05 367-383 |
| spelling |
10.1007/s00034-015-0082-9 doi (DE-627)SPR000540064 (SPR)s00034-015-0082-9-e DE-627 ger DE-627 rakwb eng Souliotis, George verfasserin aut Phase Interpolator with Improved Linearity 2015 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Springer Science+Business Media New York 2015 Abstract An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with post-layout simulations using a well-established CMOS 65 nm technology and transistors with standard threshold voltages. The clock frequency is at 2.5 GHz and the core voltage supply at 1.2 V. Its low phase noise makes the circuit suitable for high-speed systems where low jitter performance is required. Phase interpolator (dpeaa)DE-He213 Clock and data recovery (dpeaa)DE-He213 SerDes (dpeaa)DE-He213 Laoudias, Costas aut Plessas, Fotis aut Terzopoulos, Nikolaos aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 35(2015), 2 vom: 29. Mai, Seite 367-383 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:35 year:2015 number:2 day:29 month:05 pages:367-383 https://dx.doi.org/10.1007/s00034-015-0082-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 35 2015 2 29 05 367-383 |
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10.1007/s00034-015-0082-9 doi (DE-627)SPR000540064 (SPR)s00034-015-0082-9-e DE-627 ger DE-627 rakwb eng Souliotis, George verfasserin aut Phase Interpolator with Improved Linearity 2015 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Springer Science+Business Media New York 2015 Abstract An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with post-layout simulations using a well-established CMOS 65 nm technology and transistors with standard threshold voltages. The clock frequency is at 2.5 GHz and the core voltage supply at 1.2 V. Its low phase noise makes the circuit suitable for high-speed systems where low jitter performance is required. Phase interpolator (dpeaa)DE-He213 Clock and data recovery (dpeaa)DE-He213 SerDes (dpeaa)DE-He213 Laoudias, Costas aut Plessas, Fotis aut Terzopoulos, Nikolaos aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 35(2015), 2 vom: 29. Mai, Seite 367-383 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:35 year:2015 number:2 day:29 month:05 pages:367-383 https://dx.doi.org/10.1007/s00034-015-0082-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 35 2015 2 29 05 367-383 |
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10.1007/s00034-015-0082-9 doi (DE-627)SPR000540064 (SPR)s00034-015-0082-9-e DE-627 ger DE-627 rakwb eng Souliotis, George verfasserin aut Phase Interpolator with Improved Linearity 2015 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Springer Science+Business Media New York 2015 Abstract An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with post-layout simulations using a well-established CMOS 65 nm technology and transistors with standard threshold voltages. The clock frequency is at 2.5 GHz and the core voltage supply at 1.2 V. Its low phase noise makes the circuit suitable for high-speed systems where low jitter performance is required. Phase interpolator (dpeaa)DE-He213 Clock and data recovery (dpeaa)DE-He213 SerDes (dpeaa)DE-He213 Laoudias, Costas aut Plessas, Fotis aut Terzopoulos, Nikolaos aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 35(2015), 2 vom: 29. Mai, Seite 367-383 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:35 year:2015 number:2 day:29 month:05 pages:367-383 https://dx.doi.org/10.1007/s00034-015-0082-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 35 2015 2 29 05 367-383 |
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10.1007/s00034-015-0082-9 doi (DE-627)SPR000540064 (SPR)s00034-015-0082-9-e DE-627 ger DE-627 rakwb eng Souliotis, George verfasserin aut Phase Interpolator with Improved Linearity 2015 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Springer Science+Business Media New York 2015 Abstract An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with post-layout simulations using a well-established CMOS 65 nm technology and transistors with standard threshold voltages. The clock frequency is at 2.5 GHz and the core voltage supply at 1.2 V. Its low phase noise makes the circuit suitable for high-speed systems where low jitter performance is required. Phase interpolator (dpeaa)DE-He213 Clock and data recovery (dpeaa)DE-He213 SerDes (dpeaa)DE-He213 Laoudias, Costas aut Plessas, Fotis aut Terzopoulos, Nikolaos aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 35(2015), 2 vom: 29. Mai, Seite 367-383 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:35 year:2015 number:2 day:29 month:05 pages:367-383 https://dx.doi.org/10.1007/s00034-015-0082-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 35 2015 2 29 05 367-383 |
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Enthalten in Circuits, systems and signal processing 35(2015), 2 vom: 29. Mai, Seite 367-383 volume:35 year:2015 number:2 day:29 month:05 pages:367-383 |
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Souliotis, George @@aut@@ Laoudias, Costas @@aut@@ Plessas, Fotis @@aut@@ Terzopoulos, Nikolaos @@aut@@ |
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Phase Interpolator with Improved Linearity |
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Abstract An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with post-layout simulations using a well-established CMOS 65 nm technology and transistors with standard threshold voltages. The clock frequency is at 2.5 GHz and the core voltage supply at 1.2 V. Its low phase noise makes the circuit suitable for high-speed systems where low jitter performance is required. © Springer Science+Business Media New York 2015 |
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Abstract An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with post-layout simulations using a well-established CMOS 65 nm technology and transistors with standard threshold voltages. The clock frequency is at 2.5 GHz and the core voltage supply at 1.2 V. Its low phase noise makes the circuit suitable for high-speed systems where low jitter performance is required. © Springer Science+Business Media New York 2015 |
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Abstract An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with post-layout simulations using a well-established CMOS 65 nm technology and transistors with standard threshold voltages. The clock frequency is at 2.5 GHz and the core voltage supply at 1.2 V. Its low phase noise makes the circuit suitable for high-speed systems where low jitter performance is required. © Springer Science+Business Media New York 2015 |
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