VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach
Abstract The paper focuses on the VLSI-based digital design and implementation of reversible image watermarking (RIW) architecture using difference expansion (DE). Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware desig...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Das, Subhajit [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2017 |
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| Schlagwörter: |
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| Anmerkung: |
© Springer Science+Business Media, LLC 2017 |
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| Übergeordnetes Werk: |
Enthalten in: Circuits, systems and signal processing - Boston, Mass. : Birkhäuser, 1982, 37(2017), 4 vom: 21. Juli, Seite 1575-1593 |
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| Übergeordnetes Werk: |
volume:37 ; year:2017 ; number:4 ; day:21 ; month:07 ; pages:1575-1593 |
| Links: |
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| DOI / URN: |
10.1007/s00034-017-0609-3 |
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| Katalog-ID: |
SPR000569100 |
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| 100 | 1 | |a Das, Subhajit |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach |
| 264 | 1 | |c 2017 | |
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| 520 | |a Abstract The paper focuses on the VLSI-based digital design and implementation of reversible image watermarking (RIW) architecture using difference expansion (DE). Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware design. Moreover, its high performance gain in terms of payload capacity and the visual quality of the watermarked images would make this hardware architecture useful for real-time application on security purpose of medical and military images. High-level synthesis approach with resource-constraint design makes the architecture novel that needs only single adder, subtractor, multiplier, and divider along with 20 registers and 14 multiplexers for embedding. The number of resource required is same for watermark decoding with a modified schedule, which is the specialty of this design. The results obtained after implementation of the architecture on Xilinx Virtex-7 Field Programmable Gate Array (FPGA), Zynq-7000 programmable System-on-Chip (SoC) show the viability of low cost, high speed and real-time use. To process an image block %$(8 \times 8)%$, the latency is 226.733 ns for 150 MHz clock with throughput 35.284 Mbps and the critical path for single cycle is 5.674 ns. The obtained structural similarity (SSIM) performance quality metric of the RIW algorithm from MATLAB simulation is compared with the SSIM obtained from hardware, and excellent agreements between them are observed. | ||
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| 650 | 4 | |a Reversible image watermarking |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Digital architecture |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a VLSI |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Difference expansion |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Maity, Reshmi |4 aut | |
| 700 | 1 | |a Maity, N. P. |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t Circuits, systems and signal processing |d Boston, Mass. : Birkhäuser, 1982 |g 37(2017), 4 vom: 21. Juli, Seite 1575-1593 |w (DE-627)351975470 |w (DE-600)2085136-4 |x 1531-5878 |7 nnns |
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10.1007/s00034-017-0609-3 doi (DE-627)SPR000569100 (SPR)s00034-017-0609-3-e DE-627 ger DE-627 rakwb eng Das, Subhajit verfasserin aut VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach 2017 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Springer Science+Business Media, LLC 2017 Abstract The paper focuses on the VLSI-based digital design and implementation of reversible image watermarking (RIW) architecture using difference expansion (DE). Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware design. Moreover, its high performance gain in terms of payload capacity and the visual quality of the watermarked images would make this hardware architecture useful for real-time application on security purpose of medical and military images. High-level synthesis approach with resource-constraint design makes the architecture novel that needs only single adder, subtractor, multiplier, and divider along with 20 registers and 14 multiplexers for embedding. The number of resource required is same for watermark decoding with a modified schedule, which is the specialty of this design. The results obtained after implementation of the architecture on Xilinx Virtex-7 Field Programmable Gate Array (FPGA), Zynq-7000 programmable System-on-Chip (SoC) show the viability of low cost, high speed and real-time use. To process an image block %$(8 \times 8)%$, the latency is 226.733 ns for 150 MHz clock with throughput 35.284 Mbps and the critical path for single cycle is 5.674 ns. The obtained structural similarity (SSIM) performance quality metric of the RIW algorithm from MATLAB simulation is compared with the SSIM obtained from hardware, and excellent agreements between them are observed. FPGA (dpeaa)DE-He213 SoC (dpeaa)DE-He213 Reversible image watermarking (dpeaa)DE-He213 Digital architecture (dpeaa)DE-He213 VLSI (dpeaa)DE-He213 Difference expansion (dpeaa)DE-He213 Maity, Reshmi aut Maity, N. P. aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 37(2017), 4 vom: 21. Juli, Seite 1575-1593 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:37 year:2017 number:4 day:21 month:07 pages:1575-1593 https://dx.doi.org/10.1007/s00034-017-0609-3 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 37 2017 4 21 07 1575-1593 |
| spelling |
10.1007/s00034-017-0609-3 doi (DE-627)SPR000569100 (SPR)s00034-017-0609-3-e DE-627 ger DE-627 rakwb eng Das, Subhajit verfasserin aut VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach 2017 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Springer Science+Business Media, LLC 2017 Abstract The paper focuses on the VLSI-based digital design and implementation of reversible image watermarking (RIW) architecture using difference expansion (DE). Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware design. Moreover, its high performance gain in terms of payload capacity and the visual quality of the watermarked images would make this hardware architecture useful for real-time application on security purpose of medical and military images. High-level synthesis approach with resource-constraint design makes the architecture novel that needs only single adder, subtractor, multiplier, and divider along with 20 registers and 14 multiplexers for embedding. The number of resource required is same for watermark decoding with a modified schedule, which is the specialty of this design. The results obtained after implementation of the architecture on Xilinx Virtex-7 Field Programmable Gate Array (FPGA), Zynq-7000 programmable System-on-Chip (SoC) show the viability of low cost, high speed and real-time use. To process an image block %$(8 \times 8)%$, the latency is 226.733 ns for 150 MHz clock with throughput 35.284 Mbps and the critical path for single cycle is 5.674 ns. The obtained structural similarity (SSIM) performance quality metric of the RIW algorithm from MATLAB simulation is compared with the SSIM obtained from hardware, and excellent agreements between them are observed. FPGA (dpeaa)DE-He213 SoC (dpeaa)DE-He213 Reversible image watermarking (dpeaa)DE-He213 Digital architecture (dpeaa)DE-He213 VLSI (dpeaa)DE-He213 Difference expansion (dpeaa)DE-He213 Maity, Reshmi aut Maity, N. P. aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 37(2017), 4 vom: 21. Juli, Seite 1575-1593 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:37 year:2017 number:4 day:21 month:07 pages:1575-1593 https://dx.doi.org/10.1007/s00034-017-0609-3 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 37 2017 4 21 07 1575-1593 |
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10.1007/s00034-017-0609-3 doi (DE-627)SPR000569100 (SPR)s00034-017-0609-3-e DE-627 ger DE-627 rakwb eng Das, Subhajit verfasserin aut VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach 2017 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Springer Science+Business Media, LLC 2017 Abstract The paper focuses on the VLSI-based digital design and implementation of reversible image watermarking (RIW) architecture using difference expansion (DE). Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware design. Moreover, its high performance gain in terms of payload capacity and the visual quality of the watermarked images would make this hardware architecture useful for real-time application on security purpose of medical and military images. High-level synthesis approach with resource-constraint design makes the architecture novel that needs only single adder, subtractor, multiplier, and divider along with 20 registers and 14 multiplexers for embedding. The number of resource required is same for watermark decoding with a modified schedule, which is the specialty of this design. The results obtained after implementation of the architecture on Xilinx Virtex-7 Field Programmable Gate Array (FPGA), Zynq-7000 programmable System-on-Chip (SoC) show the viability of low cost, high speed and real-time use. To process an image block %$(8 \times 8)%$, the latency is 226.733 ns for 150 MHz clock with throughput 35.284 Mbps and the critical path for single cycle is 5.674 ns. The obtained structural similarity (SSIM) performance quality metric of the RIW algorithm from MATLAB simulation is compared with the SSIM obtained from hardware, and excellent agreements between them are observed. FPGA (dpeaa)DE-He213 SoC (dpeaa)DE-He213 Reversible image watermarking (dpeaa)DE-He213 Digital architecture (dpeaa)DE-He213 VLSI (dpeaa)DE-He213 Difference expansion (dpeaa)DE-He213 Maity, Reshmi aut Maity, N. P. aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 37(2017), 4 vom: 21. Juli, Seite 1575-1593 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:37 year:2017 number:4 day:21 month:07 pages:1575-1593 https://dx.doi.org/10.1007/s00034-017-0609-3 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 37 2017 4 21 07 1575-1593 |
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10.1007/s00034-017-0609-3 doi (DE-627)SPR000569100 (SPR)s00034-017-0609-3-e DE-627 ger DE-627 rakwb eng Das, Subhajit verfasserin aut VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach 2017 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Springer Science+Business Media, LLC 2017 Abstract The paper focuses on the VLSI-based digital design and implementation of reversible image watermarking (RIW) architecture using difference expansion (DE). Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware design. Moreover, its high performance gain in terms of payload capacity and the visual quality of the watermarked images would make this hardware architecture useful for real-time application on security purpose of medical and military images. High-level synthesis approach with resource-constraint design makes the architecture novel that needs only single adder, subtractor, multiplier, and divider along with 20 registers and 14 multiplexers for embedding. The number of resource required is same for watermark decoding with a modified schedule, which is the specialty of this design. The results obtained after implementation of the architecture on Xilinx Virtex-7 Field Programmable Gate Array (FPGA), Zynq-7000 programmable System-on-Chip (SoC) show the viability of low cost, high speed and real-time use. To process an image block %$(8 \times 8)%$, the latency is 226.733 ns for 150 MHz clock with throughput 35.284 Mbps and the critical path for single cycle is 5.674 ns. The obtained structural similarity (SSIM) performance quality metric of the RIW algorithm from MATLAB simulation is compared with the SSIM obtained from hardware, and excellent agreements between them are observed. FPGA (dpeaa)DE-He213 SoC (dpeaa)DE-He213 Reversible image watermarking (dpeaa)DE-He213 Digital architecture (dpeaa)DE-He213 VLSI (dpeaa)DE-He213 Difference expansion (dpeaa)DE-He213 Maity, Reshmi aut Maity, N. P. aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 37(2017), 4 vom: 21. Juli, Seite 1575-1593 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:37 year:2017 number:4 day:21 month:07 pages:1575-1593 https://dx.doi.org/10.1007/s00034-017-0609-3 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 37 2017 4 21 07 1575-1593 |
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10.1007/s00034-017-0609-3 doi (DE-627)SPR000569100 (SPR)s00034-017-0609-3-e DE-627 ger DE-627 rakwb eng Das, Subhajit verfasserin aut VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach 2017 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Springer Science+Business Media, LLC 2017 Abstract The paper focuses on the VLSI-based digital design and implementation of reversible image watermarking (RIW) architecture using difference expansion (DE). Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware design. Moreover, its high performance gain in terms of payload capacity and the visual quality of the watermarked images would make this hardware architecture useful for real-time application on security purpose of medical and military images. High-level synthesis approach with resource-constraint design makes the architecture novel that needs only single adder, subtractor, multiplier, and divider along with 20 registers and 14 multiplexers for embedding. The number of resource required is same for watermark decoding with a modified schedule, which is the specialty of this design. The results obtained after implementation of the architecture on Xilinx Virtex-7 Field Programmable Gate Array (FPGA), Zynq-7000 programmable System-on-Chip (SoC) show the viability of low cost, high speed and real-time use. To process an image block %$(8 \times 8)%$, the latency is 226.733 ns for 150 MHz clock with throughput 35.284 Mbps and the critical path for single cycle is 5.674 ns. The obtained structural similarity (SSIM) performance quality metric of the RIW algorithm from MATLAB simulation is compared with the SSIM obtained from hardware, and excellent agreements between them are observed. FPGA (dpeaa)DE-He213 SoC (dpeaa)DE-He213 Reversible image watermarking (dpeaa)DE-He213 Digital architecture (dpeaa)DE-He213 VLSI (dpeaa)DE-He213 Difference expansion (dpeaa)DE-He213 Maity, Reshmi aut Maity, N. P. aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 37(2017), 4 vom: 21. Juli, Seite 1575-1593 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:37 year:2017 number:4 day:21 month:07 pages:1575-1593 https://dx.doi.org/10.1007/s00034-017-0609-3 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 37 2017 4 21 07 1575-1593 |
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Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware design. Moreover, its high performance gain in terms of payload capacity and the visual quality of the watermarked images would make this hardware architecture useful for real-time application on security purpose of medical and military images. High-level synthesis approach with resource-constraint design makes the architecture novel that needs only single adder, subtractor, multiplier, and divider along with 20 registers and 14 multiplexers for embedding. The number of resource required is same for watermark decoding with a modified schedule, which is the specialty of this design. The results obtained after implementation of the architecture on Xilinx Virtex-7 Field Programmable Gate Array (FPGA), Zynq-7000 programmable System-on-Chip (SoC) show the viability of low cost, high speed and real-time use. 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Das, Subhajit |
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Das, Subhajit misc FPGA misc SoC misc Reversible image watermarking misc Digital architecture misc VLSI misc Difference expansion VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach |
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VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach FPGA (dpeaa)DE-He213 SoC (dpeaa)DE-He213 Reversible image watermarking (dpeaa)DE-He213 Digital architecture (dpeaa)DE-He213 VLSI (dpeaa)DE-He213 Difference expansion (dpeaa)DE-He213 |
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VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach |
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vlsi-based pipeline architecture for reversible image watermarking by difference expansion with high-level synthesis approach |
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VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach |
| abstract |
Abstract The paper focuses on the VLSI-based digital design and implementation of reversible image watermarking (RIW) architecture using difference expansion (DE). Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware design. Moreover, its high performance gain in terms of payload capacity and the visual quality of the watermarked images would make this hardware architecture useful for real-time application on security purpose of medical and military images. High-level synthesis approach with resource-constraint design makes the architecture novel that needs only single adder, subtractor, multiplier, and divider along with 20 registers and 14 multiplexers for embedding. The number of resource required is same for watermark decoding with a modified schedule, which is the specialty of this design. The results obtained after implementation of the architecture on Xilinx Virtex-7 Field Programmable Gate Array (FPGA), Zynq-7000 programmable System-on-Chip (SoC) show the viability of low cost, high speed and real-time use. To process an image block %$(8 \times 8)%$, the latency is 226.733 ns for 150 MHz clock with throughput 35.284 Mbps and the critical path for single cycle is 5.674 ns. The obtained structural similarity (SSIM) performance quality metric of the RIW algorithm from MATLAB simulation is compared with the SSIM obtained from hardware, and excellent agreements between them are observed. © Springer Science+Business Media, LLC 2017 |
| abstractGer |
Abstract The paper focuses on the VLSI-based digital design and implementation of reversible image watermarking (RIW) architecture using difference expansion (DE). Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware design. Moreover, its high performance gain in terms of payload capacity and the visual quality of the watermarked images would make this hardware architecture useful for real-time application on security purpose of medical and military images. High-level synthesis approach with resource-constraint design makes the architecture novel that needs only single adder, subtractor, multiplier, and divider along with 20 registers and 14 multiplexers for embedding. The number of resource required is same for watermark decoding with a modified schedule, which is the specialty of this design. The results obtained after implementation of the architecture on Xilinx Virtex-7 Field Programmable Gate Array (FPGA), Zynq-7000 programmable System-on-Chip (SoC) show the viability of low cost, high speed and real-time use. To process an image block %$(8 \times 8)%$, the latency is 226.733 ns for 150 MHz clock with throughput 35.284 Mbps and the critical path for single cycle is 5.674 ns. The obtained structural similarity (SSIM) performance quality metric of the RIW algorithm from MATLAB simulation is compared with the SSIM obtained from hardware, and excellent agreements between them are observed. © Springer Science+Business Media, LLC 2017 |
| abstract_unstemmed |
Abstract The paper focuses on the VLSI-based digital design and implementation of reversible image watermarking (RIW) architecture using difference expansion (DE). Mathematical simplicity of using a set of linear transformations leads to the choice of DE-based technique for developing hardware design. Moreover, its high performance gain in terms of payload capacity and the visual quality of the watermarked images would make this hardware architecture useful for real-time application on security purpose of medical and military images. High-level synthesis approach with resource-constraint design makes the architecture novel that needs only single adder, subtractor, multiplier, and divider along with 20 registers and 14 multiplexers for embedding. The number of resource required is same for watermark decoding with a modified schedule, which is the specialty of this design. The results obtained after implementation of the architecture on Xilinx Virtex-7 Field Programmable Gate Array (FPGA), Zynq-7000 programmable System-on-Chip (SoC) show the viability of low cost, high speed and real-time use. To process an image block %$(8 \times 8)%$, the latency is 226.733 ns for 150 MHz clock with throughput 35.284 Mbps and the critical path for single cycle is 5.674 ns. The obtained structural similarity (SSIM) performance quality metric of the RIW algorithm from MATLAB simulation is compared with the SSIM obtained from hardware, and excellent agreements between them are observed. © Springer Science+Business Media, LLC 2017 |
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VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach |
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https://dx.doi.org/10.1007/s00034-017-0609-3 |
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Maity, Reshmi Maity, N. P. |
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10.1007/s00034-017-0609-3 |
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| score |
7.4014044 |