Optimal wire ordering and spacing in low power semiconductor design
Abstract A key issue for high integration circuit design in the semiconductor industry are power constraints that stem from the need for heat removal and reliability or battery lifetime limitations. As the power consumption depends heavily on the capacitances between adjacent wires, determining the...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Gritzmann, Peter [verfasserIn] Ritter, Michael [verfasserIn] Zuber, Paul [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2008 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Mathematical programming - Berlin : Springer, 1971, 121(2008), 2 vom: 03. Juni, Seite 201-220 |
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| Übergeordnetes Werk: |
volume:121 ; year:2008 ; number:2 ; day:03 ; month:06 ; pages:201-220 |
| Links: |
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| DOI / URN: |
10.1007/s10107-008-0231-z |
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| Katalog-ID: |
SPR008783071 |
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| 245 | 1 | 0 | |a Optimal wire ordering and spacing in low power semiconductor design |
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| 520 | |a Abstract A key issue for high integration circuit design in the semiconductor industry are power constraints that stem from the need for heat removal and reliability or battery lifetime limitations. As the power consumption depends heavily on the capacitances between adjacent wires, determining the optimal ordering and spacing of parallel wires is an important issue in the design of low power chips. As it turns out, optimal wire spacing is a convex optimization problem, whereas the optimal wire ordering is combinatorial in nature, containing (a special class of) the Minimum Hamilton Path problem. While the latter is %${\mathcal{NP}}%$-hard in general, the present paper provides an %${\mathcal{O}{(N \log N)}}%$ algorithm that solves the coupled ordering and spacing problem for N parallel wires to optimality. | ||
| 650 | 4 | |a Optimal wire placement |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Convex programming |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Combinatorial optimization |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Hamilton path |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Ritter, Michael |e verfasserin |4 aut | |
| 700 | 1 | |a Zuber, Paul |e verfasserin |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t Mathematical programming |d Berlin : Springer, 1971 |g 121(2008), 2 vom: 03. Juni, Seite 201-220 |w (DE-627)25491179X |w (DE-600)1463397-8 |x 1436-4646 |7 nnns |
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10.1007/s10107-008-0231-z doi (DE-627)SPR008783071 (SPR)s10107-008-0231-z-e DE-627 ger DE-627 rakwb eng 510 ASE 31.80 bkl Gritzmann, Peter verfasserin aut Optimal wire ordering and spacing in low power semiconductor design 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A key issue for high integration circuit design in the semiconductor industry are power constraints that stem from the need for heat removal and reliability or battery lifetime limitations. As the power consumption depends heavily on the capacitances between adjacent wires, determining the optimal ordering and spacing of parallel wires is an important issue in the design of low power chips. As it turns out, optimal wire spacing is a convex optimization problem, whereas the optimal wire ordering is combinatorial in nature, containing (a special class of) the Minimum Hamilton Path problem. While the latter is %${\mathcal{NP}}%$-hard in general, the present paper provides an %${\mathcal{O}{(N \log N)}}%$ algorithm that solves the coupled ordering and spacing problem for N parallel wires to optimality. Optimal wire placement (dpeaa)DE-He213 Convex programming (dpeaa)DE-He213 Combinatorial optimization (dpeaa)DE-He213 Hamilton path (dpeaa)DE-He213 Ritter, Michael verfasserin aut Zuber, Paul verfasserin aut Enthalten in Mathematical programming Berlin : Springer, 1971 121(2008), 2 vom: 03. Juni, Seite 201-220 (DE-627)25491179X (DE-600)1463397-8 1436-4646 nnns volume:121 year:2008 number:2 day:03 month:06 pages:201-220 https://dx.doi.org/10.1007/s10107-008-0231-z lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OPC-MAT SSG-OPC-ASE GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_206 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4277 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 31.80 ASE AR 121 2008 2 03 06 201-220 |
| spelling |
10.1007/s10107-008-0231-z doi (DE-627)SPR008783071 (SPR)s10107-008-0231-z-e DE-627 ger DE-627 rakwb eng 510 ASE 31.80 bkl Gritzmann, Peter verfasserin aut Optimal wire ordering and spacing in low power semiconductor design 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A key issue for high integration circuit design in the semiconductor industry are power constraints that stem from the need for heat removal and reliability or battery lifetime limitations. As the power consumption depends heavily on the capacitances between adjacent wires, determining the optimal ordering and spacing of parallel wires is an important issue in the design of low power chips. As it turns out, optimal wire spacing is a convex optimization problem, whereas the optimal wire ordering is combinatorial in nature, containing (a special class of) the Minimum Hamilton Path problem. While the latter is %${\mathcal{NP}}%$-hard in general, the present paper provides an %${\mathcal{O}{(N \log N)}}%$ algorithm that solves the coupled ordering and spacing problem for N parallel wires to optimality. Optimal wire placement (dpeaa)DE-He213 Convex programming (dpeaa)DE-He213 Combinatorial optimization (dpeaa)DE-He213 Hamilton path (dpeaa)DE-He213 Ritter, Michael verfasserin aut Zuber, Paul verfasserin aut Enthalten in Mathematical programming Berlin : Springer, 1971 121(2008), 2 vom: 03. Juni, Seite 201-220 (DE-627)25491179X (DE-600)1463397-8 1436-4646 nnns volume:121 year:2008 number:2 day:03 month:06 pages:201-220 https://dx.doi.org/10.1007/s10107-008-0231-z lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OPC-MAT SSG-OPC-ASE GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_206 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4277 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 31.80 ASE AR 121 2008 2 03 06 201-220 |
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10.1007/s10107-008-0231-z doi (DE-627)SPR008783071 (SPR)s10107-008-0231-z-e DE-627 ger DE-627 rakwb eng 510 ASE 31.80 bkl Gritzmann, Peter verfasserin aut Optimal wire ordering and spacing in low power semiconductor design 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A key issue for high integration circuit design in the semiconductor industry are power constraints that stem from the need for heat removal and reliability or battery lifetime limitations. As the power consumption depends heavily on the capacitances between adjacent wires, determining the optimal ordering and spacing of parallel wires is an important issue in the design of low power chips. As it turns out, optimal wire spacing is a convex optimization problem, whereas the optimal wire ordering is combinatorial in nature, containing (a special class of) the Minimum Hamilton Path problem. While the latter is %${\mathcal{NP}}%$-hard in general, the present paper provides an %${\mathcal{O}{(N \log N)}}%$ algorithm that solves the coupled ordering and spacing problem for N parallel wires to optimality. Optimal wire placement (dpeaa)DE-He213 Convex programming (dpeaa)DE-He213 Combinatorial optimization (dpeaa)DE-He213 Hamilton path (dpeaa)DE-He213 Ritter, Michael verfasserin aut Zuber, Paul verfasserin aut Enthalten in Mathematical programming Berlin : Springer, 1971 121(2008), 2 vom: 03. Juni, Seite 201-220 (DE-627)25491179X (DE-600)1463397-8 1436-4646 nnns volume:121 year:2008 number:2 day:03 month:06 pages:201-220 https://dx.doi.org/10.1007/s10107-008-0231-z lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OPC-MAT SSG-OPC-ASE GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_206 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4277 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 31.80 ASE AR 121 2008 2 03 06 201-220 |
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10.1007/s10107-008-0231-z doi (DE-627)SPR008783071 (SPR)s10107-008-0231-z-e DE-627 ger DE-627 rakwb eng 510 ASE 31.80 bkl Gritzmann, Peter verfasserin aut Optimal wire ordering and spacing in low power semiconductor design 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A key issue for high integration circuit design in the semiconductor industry are power constraints that stem from the need for heat removal and reliability or battery lifetime limitations. As the power consumption depends heavily on the capacitances between adjacent wires, determining the optimal ordering and spacing of parallel wires is an important issue in the design of low power chips. As it turns out, optimal wire spacing is a convex optimization problem, whereas the optimal wire ordering is combinatorial in nature, containing (a special class of) the Minimum Hamilton Path problem. While the latter is %${\mathcal{NP}}%$-hard in general, the present paper provides an %${\mathcal{O}{(N \log N)}}%$ algorithm that solves the coupled ordering and spacing problem for N parallel wires to optimality. Optimal wire placement (dpeaa)DE-He213 Convex programming (dpeaa)DE-He213 Combinatorial optimization (dpeaa)DE-He213 Hamilton path (dpeaa)DE-He213 Ritter, Michael verfasserin aut Zuber, Paul verfasserin aut Enthalten in Mathematical programming Berlin : Springer, 1971 121(2008), 2 vom: 03. Juni, Seite 201-220 (DE-627)25491179X (DE-600)1463397-8 1436-4646 nnns volume:121 year:2008 number:2 day:03 month:06 pages:201-220 https://dx.doi.org/10.1007/s10107-008-0231-z lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OPC-MAT SSG-OPC-ASE GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_206 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4277 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 31.80 ASE AR 121 2008 2 03 06 201-220 |
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10.1007/s10107-008-0231-z doi (DE-627)SPR008783071 (SPR)s10107-008-0231-z-e DE-627 ger DE-627 rakwb eng 510 ASE 31.80 bkl Gritzmann, Peter verfasserin aut Optimal wire ordering and spacing in low power semiconductor design 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A key issue for high integration circuit design in the semiconductor industry are power constraints that stem from the need for heat removal and reliability or battery lifetime limitations. As the power consumption depends heavily on the capacitances between adjacent wires, determining the optimal ordering and spacing of parallel wires is an important issue in the design of low power chips. As it turns out, optimal wire spacing is a convex optimization problem, whereas the optimal wire ordering is combinatorial in nature, containing (a special class of) the Minimum Hamilton Path problem. While the latter is %${\mathcal{NP}}%$-hard in general, the present paper provides an %${\mathcal{O}{(N \log N)}}%$ algorithm that solves the coupled ordering and spacing problem for N parallel wires to optimality. Optimal wire placement (dpeaa)DE-He213 Convex programming (dpeaa)DE-He213 Combinatorial optimization (dpeaa)DE-He213 Hamilton path (dpeaa)DE-He213 Ritter, Michael verfasserin aut Zuber, Paul verfasserin aut Enthalten in Mathematical programming Berlin : Springer, 1971 121(2008), 2 vom: 03. Juni, Seite 201-220 (DE-627)25491179X (DE-600)1463397-8 1436-4646 nnns volume:121 year:2008 number:2 day:03 month:06 pages:201-220 https://dx.doi.org/10.1007/s10107-008-0231-z lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OPC-MAT SSG-OPC-ASE GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_206 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4277 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 31.80 ASE AR 121 2008 2 03 06 201-220 |
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Enthalten in Mathematical programming 121(2008), 2 vom: 03. Juni, Seite 201-220 volume:121 year:2008 number:2 day:03 month:06 pages:201-220 |
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Enthalten in Mathematical programming 121(2008), 2 vom: 03. Juni, Seite 201-220 volume:121 year:2008 number:2 day:03 month:06 pages:201-220 |
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Optimal wire placement Convex programming Combinatorial optimization Hamilton path |
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Gritzmann, Peter @@aut@@ Ritter, Michael @@aut@@ Zuber, Paul @@aut@@ |
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Gritzmann, Peter |
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Gritzmann, Peter ddc 510 bkl 31.80 misc Optimal wire placement misc Convex programming misc Combinatorial optimization misc Hamilton path Optimal wire ordering and spacing in low power semiconductor design |
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510 ASE 31.80 bkl Optimal wire ordering and spacing in low power semiconductor design Optimal wire placement (dpeaa)DE-He213 Convex programming (dpeaa)DE-He213 Combinatorial optimization (dpeaa)DE-He213 Hamilton path (dpeaa)DE-He213 |
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ddc 510 bkl 31.80 misc Optimal wire placement misc Convex programming misc Combinatorial optimization misc Hamilton path |
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Optimal wire ordering and spacing in low power semiconductor design |
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optimal wire ordering and spacing in low power semiconductor design |
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Optimal wire ordering and spacing in low power semiconductor design |
| abstract |
Abstract A key issue for high integration circuit design in the semiconductor industry are power constraints that stem from the need for heat removal and reliability or battery lifetime limitations. As the power consumption depends heavily on the capacitances between adjacent wires, determining the optimal ordering and spacing of parallel wires is an important issue in the design of low power chips. As it turns out, optimal wire spacing is a convex optimization problem, whereas the optimal wire ordering is combinatorial in nature, containing (a special class of) the Minimum Hamilton Path problem. While the latter is %${\mathcal{NP}}%$-hard in general, the present paper provides an %${\mathcal{O}{(N \log N)}}%$ algorithm that solves the coupled ordering and spacing problem for N parallel wires to optimality. |
| abstractGer |
Abstract A key issue for high integration circuit design in the semiconductor industry are power constraints that stem from the need for heat removal and reliability or battery lifetime limitations. As the power consumption depends heavily on the capacitances between adjacent wires, determining the optimal ordering and spacing of parallel wires is an important issue in the design of low power chips. As it turns out, optimal wire spacing is a convex optimization problem, whereas the optimal wire ordering is combinatorial in nature, containing (a special class of) the Minimum Hamilton Path problem. While the latter is %${\mathcal{NP}}%$-hard in general, the present paper provides an %${\mathcal{O}{(N \log N)}}%$ algorithm that solves the coupled ordering and spacing problem for N parallel wires to optimality. |
| abstract_unstemmed |
Abstract A key issue for high integration circuit design in the semiconductor industry are power constraints that stem from the need for heat removal and reliability or battery lifetime limitations. As the power consumption depends heavily on the capacitances between adjacent wires, determining the optimal ordering and spacing of parallel wires is an important issue in the design of low power chips. As it turns out, optimal wire spacing is a convex optimization problem, whereas the optimal wire ordering is combinatorial in nature, containing (a special class of) the Minimum Hamilton Path problem. While the latter is %${\mathcal{NP}}%$-hard in general, the present paper provides an %${\mathcal{O}{(N \log N)}}%$ algorithm that solves the coupled ordering and spacing problem for N parallel wires to optimality. |
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Optimal wire ordering and spacing in low power semiconductor design |
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https://dx.doi.org/10.1007/s10107-008-0231-z |
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Ritter, Michael Zuber, Paul |
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Ritter, Michael Zuber, Paul |
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| doi_str |
10.1007/s10107-008-0231-z |
| up_date |
2024-07-03T23:08:35.625Z |
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| score |
7.402173 |