A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications
Abstract In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four t...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Tsai, Meng-Ting [verfasserIn] Yang, Ching-Yuan [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2009 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Analog integrated circuits and signal processing - Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991, 64(2009), 1 vom: 12. Aug., Seite 69-79 |
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| Übergeordnetes Werk: |
volume:64 ; year:2009 ; number:1 ; day:12 ; month:08 ; pages:69-79 |
| Links: |
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| DOI / URN: |
10.1007/s10470-009-9355-1 |
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| Katalog-ID: |
SPR010310924 |
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| 100 | 1 | |a Tsai, Meng-Ting |e verfasserin |4 aut | |
| 245 | 1 | 2 | |a A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications |
| 264 | 1 | |c 2009 | |
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| 520 | |a Abstract In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four times of the reference period. In addition, a current-enhanced circuit applied to the PLL can make settling behavior faster. The synthesizer is implemented in a 0.13-μm CMOS process, which provides the range from 4.6 GHz to 5.4 GHz with the phase noise of −106 dBc/Hz at 1-MHz offset. Combining the fast-locking techniques, the lock time of the synthesizer can be less than 13.2 μs and consume 39 mW from a 1.2-V power supply. | ||
| 650 | 4 | |a Frequency synthesizer |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Phase-locked loop |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Time-to-voltage converter |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Fast locking |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Voltage-controlled oscillator |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Phase alignment |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Yang, Ching-Yuan |e verfasserin |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t Analog integrated circuits and signal processing |d Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 |g 64(2009), 1 vom: 12. Aug., Seite 69-79 |w (DE-627)271348925 |w (DE-600)1479772-0 |x 1573-1979 |7 nnns |
| 773 | 1 | 8 | |g volume:64 |g year:2009 |g number:1 |g day:12 |g month:08 |g pages:69-79 |
| 856 | 4 | 0 | |u https://dx.doi.org/10.1007/s10470-009-9355-1 |z lizenzpflichtig |3 Volltext |
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| 912 | |a GBV_ILN_73 | ||
| 912 | |a GBV_ILN_74 | ||
| 912 | |a GBV_ILN_90 | ||
| 912 | |a GBV_ILN_95 | ||
| 912 | |a GBV_ILN_100 | ||
| 912 | |a GBV_ILN_101 | ||
| 912 | |a GBV_ILN_105 | ||
| 912 | |a GBV_ILN_110 | ||
| 912 | |a GBV_ILN_120 | ||
| 912 | |a GBV_ILN_138 | ||
| 912 | |a GBV_ILN_150 | ||
| 912 | |a GBV_ILN_151 | ||
| 912 | |a GBV_ILN_152 | ||
| 912 | |a GBV_ILN_161 | ||
| 912 | |a GBV_ILN_170 | ||
| 912 | |a GBV_ILN_171 | ||
| 912 | |a GBV_ILN_187 | ||
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| 912 | |a GBV_ILN_224 | ||
| 912 | |a GBV_ILN_230 | ||
| 912 | |a GBV_ILN_250 | ||
| 912 | |a GBV_ILN_281 | ||
| 912 | |a GBV_ILN_285 | ||
| 912 | |a GBV_ILN_293 | ||
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| 912 | |a GBV_ILN_602 | ||
| 912 | |a GBV_ILN_636 | ||
| 912 | |a GBV_ILN_702 | ||
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| 912 | |a GBV_ILN_2010 | ||
| 912 | |a GBV_ILN_2011 | ||
| 912 | |a GBV_ILN_2014 | ||
| 912 | |a GBV_ILN_2015 | ||
| 912 | |a GBV_ILN_2020 | ||
| 912 | |a GBV_ILN_2021 | ||
| 912 | |a GBV_ILN_2025 | ||
| 912 | |a GBV_ILN_2026 | ||
| 912 | |a GBV_ILN_2027 | ||
| 912 | |a GBV_ILN_2031 | ||
| 912 | |a GBV_ILN_2034 | ||
| 912 | |a GBV_ILN_2037 | ||
| 912 | |a GBV_ILN_2038 | ||
| 912 | |a GBV_ILN_2039 | ||
| 912 | |a GBV_ILN_2044 | ||
| 912 | |a GBV_ILN_2048 | ||
| 912 | |a GBV_ILN_2049 | ||
| 912 | |a GBV_ILN_2050 | ||
| 912 | |a GBV_ILN_2055 | ||
| 912 | |a GBV_ILN_2057 | ||
| 912 | |a GBV_ILN_2059 | ||
| 912 | |a GBV_ILN_2061 | ||
| 912 | |a GBV_ILN_2064 | ||
| 912 | |a GBV_ILN_2065 | ||
| 912 | |a GBV_ILN_2068 | ||
| 912 | |a GBV_ILN_2070 | ||
| 912 | |a GBV_ILN_2086 | ||
| 912 | |a GBV_ILN_2088 | ||
| 912 | |a GBV_ILN_2093 | ||
| 912 | |a GBV_ILN_2106 | ||
| 912 | |a GBV_ILN_2107 | ||
| 912 | |a GBV_ILN_2108 | ||
| 912 | |a GBV_ILN_2110 | ||
| 912 | |a GBV_ILN_2111 | ||
| 912 | |a GBV_ILN_2112 | ||
| 912 | |a GBV_ILN_2113 | ||
| 912 | |a GBV_ILN_2116 | ||
| 912 | |a GBV_ILN_2118 | ||
| 912 | |a GBV_ILN_2119 | ||
| 912 | |a GBV_ILN_2122 | ||
| 912 | |a GBV_ILN_2129 | ||
| 912 | |a GBV_ILN_2143 | ||
| 912 | |a GBV_ILN_2144 | ||
| 912 | |a GBV_ILN_2147 | ||
| 912 | |a GBV_ILN_2148 | ||
| 912 | |a GBV_ILN_2152 | ||
| 912 | |a GBV_ILN_2153 | ||
| 912 | |a GBV_ILN_2188 | ||
| 912 | |a GBV_ILN_2190 | ||
| 912 | |a GBV_ILN_2232 | ||
| 912 | |a GBV_ILN_2336 | ||
| 912 | |a GBV_ILN_2446 | ||
| 912 | |a GBV_ILN_2470 | ||
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| 912 | |a GBV_ILN_4012 | ||
| 912 | |a GBV_ILN_4035 | ||
| 912 | |a GBV_ILN_4037 | ||
| 912 | |a GBV_ILN_4046 | ||
| 912 | |a GBV_ILN_4112 | ||
| 912 | |a GBV_ILN_4125 | ||
| 912 | |a GBV_ILN_4126 | ||
| 912 | |a GBV_ILN_4242 | ||
| 912 | |a GBV_ILN_4246 | ||
| 912 | |a GBV_ILN_4249 | ||
| 912 | |a GBV_ILN_4251 | ||
| 912 | |a GBV_ILN_4305 | ||
| 912 | |a GBV_ILN_4306 | ||
| 912 | |a GBV_ILN_4307 | ||
| 912 | |a GBV_ILN_4313 | ||
| 912 | |a GBV_ILN_4322 | ||
| 912 | |a GBV_ILN_4323 | ||
| 912 | |a GBV_ILN_4324 | ||
| 912 | |a GBV_ILN_4325 | ||
| 912 | |a GBV_ILN_4326 | ||
| 912 | |a GBV_ILN_4333 | ||
| 912 | |a GBV_ILN_4334 | ||
| 912 | |a GBV_ILN_4335 | ||
| 912 | |a GBV_ILN_4336 | ||
| 912 | |a GBV_ILN_4338 | ||
| 912 | |a GBV_ILN_4393 | ||
| 912 | |a GBV_ILN_4700 | ||
| 936 | b | k | |a 53.55 |q ASE |
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| 952 | |d 64 |j 2009 |e 1 |b 12 |c 08 |h 69-79 | ||
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| allfields |
10.1007/s10470-009-9355-1 doi (DE-627)SPR010310924 (SPR)s10470-009-9355-1-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Tsai, Meng-Ting verfasserin aut A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications 2009 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four times of the reference period. In addition, a current-enhanced circuit applied to the PLL can make settling behavior faster. The synthesizer is implemented in a 0.13-μm CMOS process, which provides the range from 4.6 GHz to 5.4 GHz with the phase noise of −106 dBc/Hz at 1-MHz offset. Combining the fast-locking techniques, the lock time of the synthesizer can be less than 13.2 μs and consume 39 mW from a 1.2-V power supply. Frequency synthesizer (dpeaa)DE-He213 Phase-locked loop (dpeaa)DE-He213 Time-to-voltage converter (dpeaa)DE-He213 Fast locking (dpeaa)DE-He213 Voltage-controlled oscillator (dpeaa)DE-He213 Phase alignment (dpeaa)DE-He213 Yang, Ching-Yuan verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 64(2009), 1 vom: 12. Aug., Seite 69-79 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:64 year:2009 number:1 day:12 month:08 pages:69-79 https://dx.doi.org/10.1007/s10470-009-9355-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 64 2009 1 12 08 69-79 |
| spelling |
10.1007/s10470-009-9355-1 doi (DE-627)SPR010310924 (SPR)s10470-009-9355-1-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Tsai, Meng-Ting verfasserin aut A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications 2009 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four times of the reference period. In addition, a current-enhanced circuit applied to the PLL can make settling behavior faster. The synthesizer is implemented in a 0.13-μm CMOS process, which provides the range from 4.6 GHz to 5.4 GHz with the phase noise of −106 dBc/Hz at 1-MHz offset. Combining the fast-locking techniques, the lock time of the synthesizer can be less than 13.2 μs and consume 39 mW from a 1.2-V power supply. Frequency synthesizer (dpeaa)DE-He213 Phase-locked loop (dpeaa)DE-He213 Time-to-voltage converter (dpeaa)DE-He213 Fast locking (dpeaa)DE-He213 Voltage-controlled oscillator (dpeaa)DE-He213 Phase alignment (dpeaa)DE-He213 Yang, Ching-Yuan verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 64(2009), 1 vom: 12. Aug., Seite 69-79 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:64 year:2009 number:1 day:12 month:08 pages:69-79 https://dx.doi.org/10.1007/s10470-009-9355-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 64 2009 1 12 08 69-79 |
| allfields_unstemmed |
10.1007/s10470-009-9355-1 doi (DE-627)SPR010310924 (SPR)s10470-009-9355-1-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Tsai, Meng-Ting verfasserin aut A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications 2009 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four times of the reference period. In addition, a current-enhanced circuit applied to the PLL can make settling behavior faster. The synthesizer is implemented in a 0.13-μm CMOS process, which provides the range from 4.6 GHz to 5.4 GHz with the phase noise of −106 dBc/Hz at 1-MHz offset. Combining the fast-locking techniques, the lock time of the synthesizer can be less than 13.2 μs and consume 39 mW from a 1.2-V power supply. Frequency synthesizer (dpeaa)DE-He213 Phase-locked loop (dpeaa)DE-He213 Time-to-voltage converter (dpeaa)DE-He213 Fast locking (dpeaa)DE-He213 Voltage-controlled oscillator (dpeaa)DE-He213 Phase alignment (dpeaa)DE-He213 Yang, Ching-Yuan verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 64(2009), 1 vom: 12. Aug., Seite 69-79 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:64 year:2009 number:1 day:12 month:08 pages:69-79 https://dx.doi.org/10.1007/s10470-009-9355-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 64 2009 1 12 08 69-79 |
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10.1007/s10470-009-9355-1 doi (DE-627)SPR010310924 (SPR)s10470-009-9355-1-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Tsai, Meng-Ting verfasserin aut A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications 2009 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four times of the reference period. In addition, a current-enhanced circuit applied to the PLL can make settling behavior faster. The synthesizer is implemented in a 0.13-μm CMOS process, which provides the range from 4.6 GHz to 5.4 GHz with the phase noise of −106 dBc/Hz at 1-MHz offset. Combining the fast-locking techniques, the lock time of the synthesizer can be less than 13.2 μs and consume 39 mW from a 1.2-V power supply. Frequency synthesizer (dpeaa)DE-He213 Phase-locked loop (dpeaa)DE-He213 Time-to-voltage converter (dpeaa)DE-He213 Fast locking (dpeaa)DE-He213 Voltage-controlled oscillator (dpeaa)DE-He213 Phase alignment (dpeaa)DE-He213 Yang, Ching-Yuan verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 64(2009), 1 vom: 12. Aug., Seite 69-79 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:64 year:2009 number:1 day:12 month:08 pages:69-79 https://dx.doi.org/10.1007/s10470-009-9355-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 64 2009 1 12 08 69-79 |
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10.1007/s10470-009-9355-1 doi (DE-627)SPR010310924 (SPR)s10470-009-9355-1-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Tsai, Meng-Ting verfasserin aut A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications 2009 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four times of the reference period. In addition, a current-enhanced circuit applied to the PLL can make settling behavior faster. The synthesizer is implemented in a 0.13-μm CMOS process, which provides the range from 4.6 GHz to 5.4 GHz with the phase noise of −106 dBc/Hz at 1-MHz offset. Combining the fast-locking techniques, the lock time of the synthesizer can be less than 13.2 μs and consume 39 mW from a 1.2-V power supply. Frequency synthesizer (dpeaa)DE-He213 Phase-locked loop (dpeaa)DE-He213 Time-to-voltage converter (dpeaa)DE-He213 Fast locking (dpeaa)DE-He213 Voltage-controlled oscillator (dpeaa)DE-He213 Phase alignment (dpeaa)DE-He213 Yang, Ching-Yuan verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 64(2009), 1 vom: 12. Aug., Seite 69-79 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:64 year:2009 number:1 day:12 month:08 pages:69-79 https://dx.doi.org/10.1007/s10470-009-9355-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 64 2009 1 12 08 69-79 |
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English |
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Enthalten in Analog integrated circuits and signal processing 64(2009), 1 vom: 12. Aug., Seite 69-79 volume:64 year:2009 number:1 day:12 month:08 pages:69-79 |
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Enthalten in Analog integrated circuits and signal processing 64(2009), 1 vom: 12. Aug., Seite 69-79 volume:64 year:2009 number:1 day:12 month:08 pages:69-79 |
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findex.gbv.de |
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Frequency synthesizer Phase-locked loop Time-to-voltage converter Fast locking Voltage-controlled oscillator Phase alignment |
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Analog integrated circuits and signal processing |
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Tsai, Meng-Ting @@aut@@ Yang, Ching-Yuan @@aut@@ |
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2009-08-12T00:00:00Z |
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14 |
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|
| author |
Tsai, Meng-Ting |
| spellingShingle |
Tsai, Meng-Ting ddc 004 bkl 53.55 bkl 53.73 misc Frequency synthesizer misc Phase-locked loop misc Time-to-voltage converter misc Fast locking misc Voltage-controlled oscillator misc Phase alignment A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications |
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004 ASE 53.55 bkl 53.73 bkl A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications Frequency synthesizer (dpeaa)DE-He213 Phase-locked loop (dpeaa)DE-He213 Time-to-voltage converter (dpeaa)DE-He213 Fast locking (dpeaa)DE-He213 Voltage-controlled oscillator (dpeaa)DE-He213 Phase alignment (dpeaa)DE-He213 |
| topic |
ddc 004 bkl 53.55 bkl 53.73 misc Frequency synthesizer misc Phase-locked loop misc Time-to-voltage converter misc Fast locking misc Voltage-controlled oscillator misc Phase alignment |
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ddc 004 bkl 53.55 bkl 53.73 misc Frequency synthesizer misc Phase-locked loop misc Time-to-voltage converter misc Fast locking misc Voltage-controlled oscillator misc Phase alignment |
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ddc 004 bkl 53.55 bkl 53.73 misc Frequency synthesizer misc Phase-locked loop misc Time-to-voltage converter misc Fast locking misc Voltage-controlled oscillator misc Phase alignment |
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000 - Computer science, knowledge & systems |
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A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications |
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A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications |
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Tsai, Meng-Ting |
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Analog integrated circuits and signal processing |
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Analog integrated circuits and signal processing |
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2009 |
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Tsai, Meng-Ting Yang, Ching-Yuan |
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Elektronische Aufsätze |
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Tsai, Meng-Ting |
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10.1007/s10470-009-9355-1 |
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verfasserin |
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fast-locking agile frequency synthesizer for mimo dual-mode wifi/wimax applications |
| title_auth |
A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications |
| abstract |
Abstract In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four times of the reference period. In addition, a current-enhanced circuit applied to the PLL can make settling behavior faster. The synthesizer is implemented in a 0.13-μm CMOS process, which provides the range from 4.6 GHz to 5.4 GHz with the phase noise of −106 dBc/Hz at 1-MHz offset. Combining the fast-locking techniques, the lock time of the synthesizer can be less than 13.2 μs and consume 39 mW from a 1.2-V power supply. |
| abstractGer |
Abstract In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four times of the reference period. In addition, a current-enhanced circuit applied to the PLL can make settling behavior faster. The synthesizer is implemented in a 0.13-μm CMOS process, which provides the range from 4.6 GHz to 5.4 GHz with the phase noise of −106 dBc/Hz at 1-MHz offset. Combining the fast-locking techniques, the lock time of the synthesizer can be less than 13.2 μs and consume 39 mW from a 1.2-V power supply. |
| abstract_unstemmed |
Abstract In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four times of the reference period. In addition, a current-enhanced circuit applied to the PLL can make settling behavior faster. The synthesizer is implemented in a 0.13-μm CMOS process, which provides the range from 4.6 GHz to 5.4 GHz with the phase noise of −106 dBc/Hz at 1-MHz offset. Combining the fast-locking techniques, the lock time of the synthesizer can be less than 13.2 μs and consume 39 mW from a 1.2-V power supply. |
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| title_short |
A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications |
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https://dx.doi.org/10.1007/s10470-009-9355-1 |
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| author2 |
Yang, Ching-Yuan |
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Yang, Ching-Yuan |
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| doi_str |
10.1007/s10470-009-9355-1 |
| up_date |
2024-07-03T15:18:02.930Z |
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| score |
7.3994665 |