1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector
Abstract A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according t...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Wu, Jianhui [verfasserIn] Gu, Junhui [verfasserIn] Du, Zhengchang [verfasserIn] |
|---|
| Format: |
E-Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
2011 |
|---|
| Schlagwörter: |
|---|
| Übergeordnetes Werk: |
Enthalten in: Analog integrated circuits and signal processing - Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991, 71(2011), 3 vom: 20. Juli, Seite 531-538 |
|---|---|
| Übergeordnetes Werk: |
volume:71 ; year:2011 ; number:3 ; day:20 ; month:07 ; pages:531-538 |
| Links: |
|---|
| DOI / URN: |
10.1007/s10470-011-9699-1 |
|---|
| Katalog-ID: |
SPR010314423 |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | SPR010314423 | ||
| 003 | DE-627 | ||
| 005 | 20220110220006.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 201005s2011 xx |||||o 00| ||eng c | ||
| 024 | 7 | |a 10.1007/s10470-011-9699-1 |2 doi | |
| 035 | |a (DE-627)SPR010314423 | ||
| 035 | |a (SPR)s10470-011-9699-1-e | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 082 | 0 | 4 | |a 004 |q ASE |
| 084 | |a 53.55 |2 bkl | ||
| 084 | |a 53.73 |2 bkl | ||
| 100 | 1 | |a Wu, Jianhui |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a 1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector |
| 264 | 1 | |c 2011 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a Computermedien |b c |2 rdamedia | ||
| 338 | |a Online-Ressource |b cr |2 rdacarrier | ||
| 520 | |a Abstract A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 μm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz–3.5 GHz, and the duty cycle range of the input signal is from 0.1–99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz. | ||
| 650 | 4 | |a Duty cycle corrector |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Duty cycle detector |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Continuous-time integrator |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Scale down |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Gu, Junhui |e verfasserin |4 aut | |
| 700 | 1 | |a Du, Zhengchang |e verfasserin |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t Analog integrated circuits and signal processing |d Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 |g 71(2011), 3 vom: 20. Juli, Seite 531-538 |w (DE-627)271348925 |w (DE-600)1479772-0 |x 1573-1979 |7 nnns |
| 773 | 1 | 8 | |g volume:71 |g year:2011 |g number:3 |g day:20 |g month:07 |g pages:531-538 |
| 856 | 4 | 0 | |u https://dx.doi.org/10.1007/s10470-011-9699-1 |z lizenzpflichtig |3 Volltext |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_SPRINGER | ||
| 912 | |a GBV_ILN_11 | ||
| 912 | |a GBV_ILN_20 | ||
| 912 | |a GBV_ILN_22 | ||
| 912 | |a GBV_ILN_23 | ||
| 912 | |a GBV_ILN_24 | ||
| 912 | |a GBV_ILN_31 | ||
| 912 | |a GBV_ILN_32 | ||
| 912 | |a GBV_ILN_39 | ||
| 912 | |a GBV_ILN_40 | ||
| 912 | |a GBV_ILN_60 | ||
| 912 | |a GBV_ILN_62 | ||
| 912 | |a GBV_ILN_63 | ||
| 912 | |a GBV_ILN_69 | ||
| 912 | |a GBV_ILN_70 | ||
| 912 | |a GBV_ILN_73 | ||
| 912 | |a GBV_ILN_74 | ||
| 912 | |a GBV_ILN_90 | ||
| 912 | |a GBV_ILN_95 | ||
| 912 | |a GBV_ILN_100 | ||
| 912 | |a GBV_ILN_101 | ||
| 912 | |a GBV_ILN_105 | ||
| 912 | |a GBV_ILN_110 | ||
| 912 | |a GBV_ILN_120 | ||
| 912 | |a GBV_ILN_138 | ||
| 912 | |a GBV_ILN_150 | ||
| 912 | |a GBV_ILN_151 | ||
| 912 | |a GBV_ILN_152 | ||
| 912 | |a GBV_ILN_161 | ||
| 912 | |a GBV_ILN_170 | ||
| 912 | |a GBV_ILN_171 | ||
| 912 | |a GBV_ILN_187 | ||
| 912 | |a GBV_ILN_213 | ||
| 912 | |a GBV_ILN_224 | ||
| 912 | |a GBV_ILN_230 | ||
| 912 | |a GBV_ILN_250 | ||
| 912 | |a GBV_ILN_281 | ||
| 912 | |a GBV_ILN_285 | ||
| 912 | |a GBV_ILN_293 | ||
| 912 | |a GBV_ILN_370 | ||
| 912 | |a GBV_ILN_602 | ||
| 912 | |a GBV_ILN_636 | ||
| 912 | |a GBV_ILN_702 | ||
| 912 | |a GBV_ILN_2001 | ||
| 912 | |a GBV_ILN_2003 | ||
| 912 | |a GBV_ILN_2004 | ||
| 912 | |a GBV_ILN_2005 | ||
| 912 | |a GBV_ILN_2006 | ||
| 912 | |a GBV_ILN_2007 | ||
| 912 | |a GBV_ILN_2008 | ||
| 912 | |a GBV_ILN_2009 | ||
| 912 | |a GBV_ILN_2010 | ||
| 912 | |a GBV_ILN_2011 | ||
| 912 | |a GBV_ILN_2014 | ||
| 912 | |a GBV_ILN_2015 | ||
| 912 | |a GBV_ILN_2020 | ||
| 912 | |a GBV_ILN_2021 | ||
| 912 | |a GBV_ILN_2025 | ||
| 912 | |a GBV_ILN_2026 | ||
| 912 | |a GBV_ILN_2027 | ||
| 912 | |a GBV_ILN_2031 | ||
| 912 | |a GBV_ILN_2034 | ||
| 912 | |a GBV_ILN_2037 | ||
| 912 | |a GBV_ILN_2038 | ||
| 912 | |a GBV_ILN_2039 | ||
| 912 | |a GBV_ILN_2044 | ||
| 912 | |a GBV_ILN_2048 | ||
| 912 | |a GBV_ILN_2049 | ||
| 912 | |a GBV_ILN_2050 | ||
| 912 | |a GBV_ILN_2055 | ||
| 912 | |a GBV_ILN_2057 | ||
| 912 | |a GBV_ILN_2059 | ||
| 912 | |a GBV_ILN_2061 | ||
| 912 | |a GBV_ILN_2064 | ||
| 912 | |a GBV_ILN_2065 | ||
| 912 | |a GBV_ILN_2068 | ||
| 912 | |a GBV_ILN_2070 | ||
| 912 | |a GBV_ILN_2086 | ||
| 912 | |a GBV_ILN_2088 | ||
| 912 | |a GBV_ILN_2093 | ||
| 912 | |a GBV_ILN_2106 | ||
| 912 | |a GBV_ILN_2107 | ||
| 912 | |a GBV_ILN_2108 | ||
| 912 | |a GBV_ILN_2110 | ||
| 912 | |a GBV_ILN_2111 | ||
| 912 | |a GBV_ILN_2112 | ||
| 912 | |a GBV_ILN_2113 | ||
| 912 | |a GBV_ILN_2116 | ||
| 912 | |a GBV_ILN_2118 | ||
| 912 | |a GBV_ILN_2119 | ||
| 912 | |a GBV_ILN_2122 | ||
| 912 | |a GBV_ILN_2129 | ||
| 912 | |a GBV_ILN_2143 | ||
| 912 | |a GBV_ILN_2144 | ||
| 912 | |a GBV_ILN_2147 | ||
| 912 | |a GBV_ILN_2148 | ||
| 912 | |a GBV_ILN_2152 | ||
| 912 | |a GBV_ILN_2153 | ||
| 912 | |a GBV_ILN_2188 | ||
| 912 | |a GBV_ILN_2190 | ||
| 912 | |a GBV_ILN_2232 | ||
| 912 | |a GBV_ILN_2336 | ||
| 912 | |a GBV_ILN_2446 | ||
| 912 | |a GBV_ILN_2470 | ||
| 912 | |a GBV_ILN_2472 | ||
| 912 | |a GBV_ILN_2507 | ||
| 912 | |a GBV_ILN_2522 | ||
| 912 | |a GBV_ILN_2548 | ||
| 912 | |a GBV_ILN_4012 | ||
| 912 | |a GBV_ILN_4035 | ||
| 912 | |a GBV_ILN_4037 | ||
| 912 | |a GBV_ILN_4046 | ||
| 912 | |a GBV_ILN_4112 | ||
| 912 | |a GBV_ILN_4125 | ||
| 912 | |a GBV_ILN_4126 | ||
| 912 | |a GBV_ILN_4242 | ||
| 912 | |a GBV_ILN_4246 | ||
| 912 | |a GBV_ILN_4249 | ||
| 912 | |a GBV_ILN_4251 | ||
| 912 | |a GBV_ILN_4305 | ||
| 912 | |a GBV_ILN_4306 | ||
| 912 | |a GBV_ILN_4307 | ||
| 912 | |a GBV_ILN_4313 | ||
| 912 | |a GBV_ILN_4322 | ||
| 912 | |a GBV_ILN_4323 | ||
| 912 | |a GBV_ILN_4324 | ||
| 912 | |a GBV_ILN_4325 | ||
| 912 | |a GBV_ILN_4326 | ||
| 912 | |a GBV_ILN_4333 | ||
| 912 | |a GBV_ILN_4334 | ||
| 912 | |a GBV_ILN_4335 | ||
| 912 | |a GBV_ILN_4336 | ||
| 912 | |a GBV_ILN_4338 | ||
| 912 | |a GBV_ILN_4393 | ||
| 912 | |a GBV_ILN_4700 | ||
| 936 | b | k | |a 53.55 |q ASE |
| 936 | b | k | |a 53.73 |q ASE |
| 951 | |a AR | ||
| 952 | |d 71 |j 2011 |e 3 |b 20 |c 07 |h 531-538 | ||
| author_variant |
j w jw j g jg z d zd |
|---|---|
| matchkey_str |
article:15731979:2011----::mz5hwdrnenudt5otudt |
| hierarchy_sort_str |
2011 |
| bklnumber |
53.55 53.73 |
| publishDate |
2011 |
| allfields |
10.1007/s10470-011-9699-1 doi (DE-627)SPR010314423 (SPR)s10470-011-9699-1-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Wu, Jianhui verfasserin aut 1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector 2011 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 μm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz–3.5 GHz, and the duty cycle range of the input signal is from 0.1–99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz. Duty cycle corrector (dpeaa)DE-He213 Duty cycle detector (dpeaa)DE-He213 Continuous-time integrator (dpeaa)DE-He213 Scale down (dpeaa)DE-He213 Gu, Junhui verfasserin aut Du, Zhengchang verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 71(2011), 3 vom: 20. Juli, Seite 531-538 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:71 year:2011 number:3 day:20 month:07 pages:531-538 https://dx.doi.org/10.1007/s10470-011-9699-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 71 2011 3 20 07 531-538 |
| spelling |
10.1007/s10470-011-9699-1 doi (DE-627)SPR010314423 (SPR)s10470-011-9699-1-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Wu, Jianhui verfasserin aut 1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector 2011 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 μm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz–3.5 GHz, and the duty cycle range of the input signal is from 0.1–99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz. Duty cycle corrector (dpeaa)DE-He213 Duty cycle detector (dpeaa)DE-He213 Continuous-time integrator (dpeaa)DE-He213 Scale down (dpeaa)DE-He213 Gu, Junhui verfasserin aut Du, Zhengchang verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 71(2011), 3 vom: 20. Juli, Seite 531-538 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:71 year:2011 number:3 day:20 month:07 pages:531-538 https://dx.doi.org/10.1007/s10470-011-9699-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 71 2011 3 20 07 531-538 |
| allfields_unstemmed |
10.1007/s10470-011-9699-1 doi (DE-627)SPR010314423 (SPR)s10470-011-9699-1-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Wu, Jianhui verfasserin aut 1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector 2011 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 μm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz–3.5 GHz, and the duty cycle range of the input signal is from 0.1–99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz. Duty cycle corrector (dpeaa)DE-He213 Duty cycle detector (dpeaa)DE-He213 Continuous-time integrator (dpeaa)DE-He213 Scale down (dpeaa)DE-He213 Gu, Junhui verfasserin aut Du, Zhengchang verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 71(2011), 3 vom: 20. Juli, Seite 531-538 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:71 year:2011 number:3 day:20 month:07 pages:531-538 https://dx.doi.org/10.1007/s10470-011-9699-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 71 2011 3 20 07 531-538 |
| allfieldsGer |
10.1007/s10470-011-9699-1 doi (DE-627)SPR010314423 (SPR)s10470-011-9699-1-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Wu, Jianhui verfasserin aut 1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector 2011 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 μm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz–3.5 GHz, and the duty cycle range of the input signal is from 0.1–99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz. Duty cycle corrector (dpeaa)DE-He213 Duty cycle detector (dpeaa)DE-He213 Continuous-time integrator (dpeaa)DE-He213 Scale down (dpeaa)DE-He213 Gu, Junhui verfasserin aut Du, Zhengchang verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 71(2011), 3 vom: 20. Juli, Seite 531-538 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:71 year:2011 number:3 day:20 month:07 pages:531-538 https://dx.doi.org/10.1007/s10470-011-9699-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 71 2011 3 20 07 531-538 |
| allfieldsSound |
10.1007/s10470-011-9699-1 doi (DE-627)SPR010314423 (SPR)s10470-011-9699-1-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Wu, Jianhui verfasserin aut 1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector 2011 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 μm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz–3.5 GHz, and the duty cycle range of the input signal is from 0.1–99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz. Duty cycle corrector (dpeaa)DE-He213 Duty cycle detector (dpeaa)DE-He213 Continuous-time integrator (dpeaa)DE-He213 Scale down (dpeaa)DE-He213 Gu, Junhui verfasserin aut Du, Zhengchang verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 71(2011), 3 vom: 20. Juli, Seite 531-538 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:71 year:2011 number:3 day:20 month:07 pages:531-538 https://dx.doi.org/10.1007/s10470-011-9699-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 71 2011 3 20 07 531-538 |
| language |
English |
| source |
Enthalten in Analog integrated circuits and signal processing 71(2011), 3 vom: 20. Juli, Seite 531-538 volume:71 year:2011 number:3 day:20 month:07 pages:531-538 |
| sourceStr |
Enthalten in Analog integrated circuits and signal processing 71(2011), 3 vom: 20. Juli, Seite 531-538 volume:71 year:2011 number:3 day:20 month:07 pages:531-538 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Duty cycle corrector Duty cycle detector Continuous-time integrator Scale down |
| dewey-raw |
004 |
| isfreeaccess_bool |
false |
| container_title |
Analog integrated circuits and signal processing |
| authorswithroles_txt_mv |
Wu, Jianhui @@aut@@ Gu, Junhui @@aut@@ Du, Zhengchang @@aut@@ |
| publishDateDaySort_date |
2011-07-20T00:00:00Z |
| hierarchy_top_id |
271348925 |
| dewey-sort |
14 |
| id |
SPR010314423 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR010314423</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20220110220006.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201005s2011 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s10470-011-9699-1</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR010314423</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s10470-011-9699-1-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">004</subfield><subfield code="q">ASE</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.55</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.73</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Wu, Jianhui</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2011</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 μm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz–3.5 GHz, and the duty cycle range of the input signal is from 0.1–99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Duty cycle corrector</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Duty cycle detector</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Continuous-time integrator</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Scale down</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Gu, Junhui</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Du, Zhengchang</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Analog integrated circuits and signal processing</subfield><subfield code="d">Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991</subfield><subfield code="g">71(2011), 3 vom: 20. Juli, Seite 531-538</subfield><subfield code="w">(DE-627)271348925</subfield><subfield code="w">(DE-600)1479772-0</subfield><subfield code="x">1573-1979</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:71</subfield><subfield code="g">year:2011</subfield><subfield code="g">number:3</subfield><subfield code="g">day:20</subfield><subfield code="g">month:07</subfield><subfield code="g">pages:531-538</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/s10470-011-9699-1</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_11</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_20</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_22</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_23</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_24</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_31</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_32</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_39</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_60</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_62</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_63</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_69</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_73</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_74</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_90</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_95</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_100</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_101</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_105</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_110</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_120</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_138</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_150</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_151</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_152</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_161</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_170</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_171</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_187</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_213</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_224</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_230</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_250</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_281</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_285</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_293</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_370</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_602</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_636</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_702</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2001</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2003</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2007</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2008</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2009</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2010</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2011</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2014</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2015</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2020</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2021</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2025</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2026</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2031</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2034</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2037</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2038</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2039</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2044</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2048</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2049</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2050</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2055</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2057</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2059</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2061</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2064</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2065</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2068</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2070</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2086</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2088</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2093</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2106</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2107</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2108</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2110</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2111</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2112</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2113</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2116</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2118</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2119</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2122</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2129</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2143</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2144</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2147</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2148</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2152</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2153</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2188</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2190</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2232</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2336</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2446</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2470</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2472</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2507</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2522</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2548</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4012</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4035</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4037</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4046</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4112</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4125</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4126</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4242</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4246</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4249</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4251</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4305</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4306</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4307</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4322</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4323</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4324</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4325</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4326</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4333</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4334</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4335</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4336</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4338</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4393</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4700</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">53.55</subfield><subfield code="q">ASE</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">53.73</subfield><subfield code="q">ASE</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">71</subfield><subfield code="j">2011</subfield><subfield code="e">3</subfield><subfield code="b">20</subfield><subfield code="c">07</subfield><subfield code="h">531-538</subfield></datafield></record></collection>
|
| author |
Wu, Jianhui |
| spellingShingle |
Wu, Jianhui ddc 004 bkl 53.55 bkl 53.73 misc Duty cycle corrector misc Duty cycle detector misc Continuous-time integrator misc Scale down 1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector |
| authorStr |
Wu, Jianhui |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)271348925 |
| format |
electronic Article |
| dewey-ones |
004 - Data processing & computer science |
| delete_txt_mv |
keep |
| author_role |
aut aut aut |
| collection |
springer |
| remote_str |
true |
| illustrated |
Not Illustrated |
| issn |
1573-1979 |
| topic_title |
004 ASE 53.55 bkl 53.73 bkl 1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector Duty cycle corrector (dpeaa)DE-He213 Duty cycle detector (dpeaa)DE-He213 Continuous-time integrator (dpeaa)DE-He213 Scale down (dpeaa)DE-He213 |
| topic |
ddc 004 bkl 53.55 bkl 53.73 misc Duty cycle corrector misc Duty cycle detector misc Continuous-time integrator misc Scale down |
| topic_unstemmed |
ddc 004 bkl 53.55 bkl 53.73 misc Duty cycle corrector misc Duty cycle detector misc Continuous-time integrator misc Scale down |
| topic_browse |
ddc 004 bkl 53.55 bkl 53.73 misc Duty cycle corrector misc Duty cycle detector misc Continuous-time integrator misc Scale down |
| format_facet |
Elektronische Aufsätze Aufsätze Elektronische Ressource |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
cr |
| hierarchy_parent_title |
Analog integrated circuits and signal processing |
| hierarchy_parent_id |
271348925 |
| dewey-tens |
000 - Computer science, knowledge & systems |
| hierarchy_top_title |
Analog integrated circuits and signal processing |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)271348925 (DE-600)1479772-0 |
| title |
1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector |
| ctrlnum |
(DE-627)SPR010314423 (SPR)s10470-011-9699-1-e |
| title_full |
1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector |
| author_sort |
Wu, Jianhui |
| journal |
Analog integrated circuits and signal processing |
| journalStr |
Analog integrated circuits and signal processing |
| lang_code |
eng |
| isOA_bool |
false |
| dewey-hundreds |
000 - Computer science, information & general works |
| recordtype |
marc |
| publishDateSort |
2011 |
| contenttype_str_mv |
txt |
| container_start_page |
531 |
| author_browse |
Wu, Jianhui Gu, Junhui Du, Zhengchang |
| container_volume |
71 |
| class |
004 ASE 53.55 bkl 53.73 bkl |
| format_se |
Elektronische Aufsätze |
| author-letter |
Wu, Jianhui |
| doi_str_mv |
10.1007/s10470-011-9699-1 |
| dewey-full |
004 |
| author2-role |
verfasserin |
| title_sort |
1 mhz–3.5 ghz, wide range input duty 50% output duty cycle corrector |
| title_auth |
1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector |
| abstract |
Abstract A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 μm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz–3.5 GHz, and the duty cycle range of the input signal is from 0.1–99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz. |
| abstractGer |
Abstract A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 μm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz–3.5 GHz, and the duty cycle range of the input signal is from 0.1–99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz. |
| abstract_unstemmed |
Abstract A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 μm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz–3.5 GHz, and the duty cycle range of the input signal is from 0.1–99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz. |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 |
| container_issue |
3 |
| title_short |
1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector |
| url |
https://dx.doi.org/10.1007/s10470-011-9699-1 |
| remote_bool |
true |
| author2 |
Gu, Junhui Du, Zhengchang |
| author2Str |
Gu, Junhui Du, Zhengchang |
| ppnlink |
271348925 |
| mediatype_str_mv |
c |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| doi_str |
10.1007/s10470-011-9699-1 |
| up_date |
2024-07-03T15:19:18.383Z |
| _version_ |
1803571647882461185 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR010314423</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20220110220006.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201005s2011 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s10470-011-9699-1</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR010314423</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s10470-011-9699-1-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">004</subfield><subfield code="q">ASE</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.55</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.73</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Wu, Jianhui</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2011</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5 GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1 MHz. The test chip is fabricated using SMIC 0.18 μm CMOS process. The experiment results show that the frequency range of the input signal was 1 MHz–3.5 GHz, and the duty cycle range of the input signal is from 0.1–99.9%. The peak-to-peak jitter and power dissipation are 33.3 ps and 0.6 mW, respectively, at an operating frequency of 2 GHz.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Duty cycle corrector</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Duty cycle detector</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Continuous-time integrator</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Scale down</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Gu, Junhui</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Du, Zhengchang</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Analog integrated circuits and signal processing</subfield><subfield code="d">Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991</subfield><subfield code="g">71(2011), 3 vom: 20. Juli, Seite 531-538</subfield><subfield code="w">(DE-627)271348925</subfield><subfield code="w">(DE-600)1479772-0</subfield><subfield code="x">1573-1979</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:71</subfield><subfield code="g">year:2011</subfield><subfield code="g">number:3</subfield><subfield code="g">day:20</subfield><subfield code="g">month:07</subfield><subfield code="g">pages:531-538</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/s10470-011-9699-1</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_11</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_20</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_22</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_23</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_24</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_31</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_32</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_39</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_60</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_62</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_63</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_69</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_73</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_74</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_90</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_95</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_100</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_101</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_105</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_110</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_120</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_138</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_150</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_151</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_152</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_161</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_170</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_171</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_187</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_213</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_224</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_230</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_250</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_281</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_285</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_293</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_370</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_602</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_636</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_702</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2001</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2003</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2007</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2008</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2009</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2010</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2011</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2014</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2015</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2020</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2021</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2025</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2026</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2031</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2034</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2037</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2038</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2039</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2044</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2048</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2049</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2050</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2055</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2057</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2059</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2061</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2064</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2065</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2068</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2070</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2086</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2088</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2093</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2106</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2107</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2108</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2110</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2111</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2112</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2113</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2116</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2118</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2119</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2122</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2129</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2143</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2144</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2147</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2148</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2152</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2153</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2188</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2190</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2232</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2336</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2446</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2470</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2472</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2507</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2522</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2548</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4012</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4035</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4037</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4046</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4112</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4125</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4126</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4242</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4246</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4249</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4251</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4305</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4306</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4307</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4322</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4323</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4324</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4325</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4326</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4333</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4334</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4335</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4336</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4338</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4393</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4700</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">53.55</subfield><subfield code="q">ASE</subfield></datafield><datafield tag="936" ind1="b" ind2="k"><subfield code="a">53.73</subfield><subfield code="q">ASE</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">71</subfield><subfield code="j">2011</subfield><subfield code="e">3</subfield><subfield code="b">20</subfield><subfield code="c">07</subfield><subfield code="h">531-538</subfield></datafield></record></collection>
|
| score |
7.398798 |