Routing analog ICs using a multi-objective multi-constraint evolutionary approach
Abstract This paper describes a new multi-objective multi-constraint routing approach integrated in LAYGEN II, an analog integrated circuit layout generator based on template descriptions and evolutionary computation techniques. The approach gives special emphasis to the reusability of expert design...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Martins, R. [verfasserIn] Lourenço, N. [verfasserIn] Horta, N. [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2013 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Analog integrated circuits and signal processing - Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991, 78(2013), 1 vom: 12. Juni, Seite 123-135 |
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| Übergeordnetes Werk: |
volume:78 ; year:2013 ; number:1 ; day:12 ; month:06 ; pages:123-135 |
| Links: |
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| DOI / URN: |
10.1007/s10470-013-0088-9 |
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| Katalog-ID: |
SPR010318739 |
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| 520 | |a Abstract This paper describes a new multi-objective multi-constraint routing approach integrated in LAYGEN II, an analog integrated circuit layout generator based on template descriptions and evolutionary computation techniques. The approach gives special emphasis to the reusability of expert design knowledge and to the efficiency on retargeting operations. In order to increase the quality of routing solution, first, the placer processes the floorplan, automatically merging devices. Then, for routing, an optimization kernel is used, which consists of a modified version of the multi-objective evolutionary algorithm, NSGA-II. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic routing generation is detailed, and LAYGEN II is demonstrated for the layout generation of typical analog circuit structures, for the UMC 130 nm design process, and the results are successfully validated using the industrial grade verification $ Calibre^{®} $ tool. | ||
| 650 | 4 | |a Analog integrated circuits |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Layout generation |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Computer aided design |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Electronic design automation |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Evolutionary computation |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Lourenço, N. |e verfasserin |4 aut | |
| 700 | 1 | |a Horta, N. |e verfasserin |4 aut | |
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10.1007/s10470-013-0088-9 doi (DE-627)SPR010318739 (SPR)s10470-013-0088-9-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Martins, R. verfasserin aut Routing analog ICs using a multi-objective multi-constraint evolutionary approach 2013 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new multi-objective multi-constraint routing approach integrated in LAYGEN II, an analog integrated circuit layout generator based on template descriptions and evolutionary computation techniques. The approach gives special emphasis to the reusability of expert design knowledge and to the efficiency on retargeting operations. In order to increase the quality of routing solution, first, the placer processes the floorplan, automatically merging devices. Then, for routing, an optimization kernel is used, which consists of a modified version of the multi-objective evolutionary algorithm, NSGA-II. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic routing generation is detailed, and LAYGEN II is demonstrated for the layout generation of typical analog circuit structures, for the UMC 130 nm design process, and the results are successfully validated using the industrial grade verification $ Calibre^{®} $ tool. Analog integrated circuits (dpeaa)DE-He213 Layout generation (dpeaa)DE-He213 Computer aided design (dpeaa)DE-He213 Electronic design automation (dpeaa)DE-He213 Evolutionary computation (dpeaa)DE-He213 Lourenço, N. verfasserin aut Horta, N. verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 78(2013), 1 vom: 12. Juni, Seite 123-135 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:78 year:2013 number:1 day:12 month:06 pages:123-135 https://dx.doi.org/10.1007/s10470-013-0088-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 78 2013 1 12 06 123-135 |
| spelling |
10.1007/s10470-013-0088-9 doi (DE-627)SPR010318739 (SPR)s10470-013-0088-9-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Martins, R. verfasserin aut Routing analog ICs using a multi-objective multi-constraint evolutionary approach 2013 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new multi-objective multi-constraint routing approach integrated in LAYGEN II, an analog integrated circuit layout generator based on template descriptions and evolutionary computation techniques. The approach gives special emphasis to the reusability of expert design knowledge and to the efficiency on retargeting operations. In order to increase the quality of routing solution, first, the placer processes the floorplan, automatically merging devices. Then, for routing, an optimization kernel is used, which consists of a modified version of the multi-objective evolutionary algorithm, NSGA-II. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic routing generation is detailed, and LAYGEN II is demonstrated for the layout generation of typical analog circuit structures, for the UMC 130 nm design process, and the results are successfully validated using the industrial grade verification $ Calibre^{®} $ tool. Analog integrated circuits (dpeaa)DE-He213 Layout generation (dpeaa)DE-He213 Computer aided design (dpeaa)DE-He213 Electronic design automation (dpeaa)DE-He213 Evolutionary computation (dpeaa)DE-He213 Lourenço, N. verfasserin aut Horta, N. verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 78(2013), 1 vom: 12. Juni, Seite 123-135 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:78 year:2013 number:1 day:12 month:06 pages:123-135 https://dx.doi.org/10.1007/s10470-013-0088-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 78 2013 1 12 06 123-135 |
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10.1007/s10470-013-0088-9 doi (DE-627)SPR010318739 (SPR)s10470-013-0088-9-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Martins, R. verfasserin aut Routing analog ICs using a multi-objective multi-constraint evolutionary approach 2013 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new multi-objective multi-constraint routing approach integrated in LAYGEN II, an analog integrated circuit layout generator based on template descriptions and evolutionary computation techniques. The approach gives special emphasis to the reusability of expert design knowledge and to the efficiency on retargeting operations. In order to increase the quality of routing solution, first, the placer processes the floorplan, automatically merging devices. Then, for routing, an optimization kernel is used, which consists of a modified version of the multi-objective evolutionary algorithm, NSGA-II. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic routing generation is detailed, and LAYGEN II is demonstrated for the layout generation of typical analog circuit structures, for the UMC 130 nm design process, and the results are successfully validated using the industrial grade verification $ Calibre^{®} $ tool. Analog integrated circuits (dpeaa)DE-He213 Layout generation (dpeaa)DE-He213 Computer aided design (dpeaa)DE-He213 Electronic design automation (dpeaa)DE-He213 Evolutionary computation (dpeaa)DE-He213 Lourenço, N. verfasserin aut Horta, N. verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 78(2013), 1 vom: 12. Juni, Seite 123-135 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:78 year:2013 number:1 day:12 month:06 pages:123-135 https://dx.doi.org/10.1007/s10470-013-0088-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 78 2013 1 12 06 123-135 |
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10.1007/s10470-013-0088-9 doi (DE-627)SPR010318739 (SPR)s10470-013-0088-9-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Martins, R. verfasserin aut Routing analog ICs using a multi-objective multi-constraint evolutionary approach 2013 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new multi-objective multi-constraint routing approach integrated in LAYGEN II, an analog integrated circuit layout generator based on template descriptions and evolutionary computation techniques. The approach gives special emphasis to the reusability of expert design knowledge and to the efficiency on retargeting operations. In order to increase the quality of routing solution, first, the placer processes the floorplan, automatically merging devices. Then, for routing, an optimization kernel is used, which consists of a modified version of the multi-objective evolutionary algorithm, NSGA-II. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic routing generation is detailed, and LAYGEN II is demonstrated for the layout generation of typical analog circuit structures, for the UMC 130 nm design process, and the results are successfully validated using the industrial grade verification $ Calibre^{®} $ tool. Analog integrated circuits (dpeaa)DE-He213 Layout generation (dpeaa)DE-He213 Computer aided design (dpeaa)DE-He213 Electronic design automation (dpeaa)DE-He213 Evolutionary computation (dpeaa)DE-He213 Lourenço, N. verfasserin aut Horta, N. verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 78(2013), 1 vom: 12. Juni, Seite 123-135 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:78 year:2013 number:1 day:12 month:06 pages:123-135 https://dx.doi.org/10.1007/s10470-013-0088-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 78 2013 1 12 06 123-135 |
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10.1007/s10470-013-0088-9 doi (DE-627)SPR010318739 (SPR)s10470-013-0088-9-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Martins, R. verfasserin aut Routing analog ICs using a multi-objective multi-constraint evolutionary approach 2013 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new multi-objective multi-constraint routing approach integrated in LAYGEN II, an analog integrated circuit layout generator based on template descriptions and evolutionary computation techniques. The approach gives special emphasis to the reusability of expert design knowledge and to the efficiency on retargeting operations. In order to increase the quality of routing solution, first, the placer processes the floorplan, automatically merging devices. Then, for routing, an optimization kernel is used, which consists of a modified version of the multi-objective evolutionary algorithm, NSGA-II. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic routing generation is detailed, and LAYGEN II is demonstrated for the layout generation of typical analog circuit structures, for the UMC 130 nm design process, and the results are successfully validated using the industrial grade verification $ Calibre^{®} $ tool. Analog integrated circuits (dpeaa)DE-He213 Layout generation (dpeaa)DE-He213 Computer aided design (dpeaa)DE-He213 Electronic design automation (dpeaa)DE-He213 Evolutionary computation (dpeaa)DE-He213 Lourenço, N. verfasserin aut Horta, N. verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 78(2013), 1 vom: 12. Juni, Seite 123-135 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:78 year:2013 number:1 day:12 month:06 pages:123-135 https://dx.doi.org/10.1007/s10470-013-0088-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4012 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 78 2013 1 12 06 123-135 |
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Analog integrated circuits and signal processing |
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Martins, R. @@aut@@ Lourenço, N. @@aut@@ Horta, N. @@aut@@ |
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Martins, R. |
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Martins, R. ddc 004 bkl 53.55 bkl 53.73 misc Analog integrated circuits misc Layout generation misc Computer aided design misc Electronic design automation misc Evolutionary computation Routing analog ICs using a multi-objective multi-constraint evolutionary approach |
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004 ASE 53.55 bkl 53.73 bkl Routing analog ICs using a multi-objective multi-constraint evolutionary approach Analog integrated circuits (dpeaa)DE-He213 Layout generation (dpeaa)DE-He213 Computer aided design (dpeaa)DE-He213 Electronic design automation (dpeaa)DE-He213 Evolutionary computation (dpeaa)DE-He213 |
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ddc 004 bkl 53.55 bkl 53.73 misc Analog integrated circuits misc Layout generation misc Computer aided design misc Electronic design automation misc Evolutionary computation |
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ddc 004 bkl 53.55 bkl 53.73 misc Analog integrated circuits misc Layout generation misc Computer aided design misc Electronic design automation misc Evolutionary computation |
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routing analog ics using a multi-objective multi-constraint evolutionary approach |
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Routing analog ICs using a multi-objective multi-constraint evolutionary approach |
| abstract |
Abstract This paper describes a new multi-objective multi-constraint routing approach integrated in LAYGEN II, an analog integrated circuit layout generator based on template descriptions and evolutionary computation techniques. The approach gives special emphasis to the reusability of expert design knowledge and to the efficiency on retargeting operations. In order to increase the quality of routing solution, first, the placer processes the floorplan, automatically merging devices. Then, for routing, an optimization kernel is used, which consists of a modified version of the multi-objective evolutionary algorithm, NSGA-II. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic routing generation is detailed, and LAYGEN II is demonstrated for the layout generation of typical analog circuit structures, for the UMC 130 nm design process, and the results are successfully validated using the industrial grade verification $ Calibre^{®} $ tool. |
| abstractGer |
Abstract This paper describes a new multi-objective multi-constraint routing approach integrated in LAYGEN II, an analog integrated circuit layout generator based on template descriptions and evolutionary computation techniques. The approach gives special emphasis to the reusability of expert design knowledge and to the efficiency on retargeting operations. In order to increase the quality of routing solution, first, the placer processes the floorplan, automatically merging devices. Then, for routing, an optimization kernel is used, which consists of a modified version of the multi-objective evolutionary algorithm, NSGA-II. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic routing generation is detailed, and LAYGEN II is demonstrated for the layout generation of typical analog circuit structures, for the UMC 130 nm design process, and the results are successfully validated using the industrial grade verification $ Calibre^{®} $ tool. |
| abstract_unstemmed |
Abstract This paper describes a new multi-objective multi-constraint routing approach integrated in LAYGEN II, an analog integrated circuit layout generator based on template descriptions and evolutionary computation techniques. The approach gives special emphasis to the reusability of expert design knowledge and to the efficiency on retargeting operations. In order to increase the quality of routing solution, first, the placer processes the floorplan, automatically merging devices. Then, for routing, an optimization kernel is used, which consists of a modified version of the multi-objective evolutionary algorithm, NSGA-II. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic routing generation is detailed, and LAYGEN II is demonstrated for the layout generation of typical analog circuit structures, for the UMC 130 nm design process, and the results are successfully validated using the industrial grade verification $ Calibre^{®} $ tool. |
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Routing analog ICs using a multi-objective multi-constraint evolutionary approach |
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https://dx.doi.org/10.1007/s10470-013-0088-9 |
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Lourenço, N. Horta, N. |
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Lourenço, N. Horta, N. |
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| doi_str |
10.1007/s10470-013-0088-9 |
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2024-07-03T15:20:52.709Z |
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| score |
7.4014635 |