A CMOS based low power digitally controlled oscillator design with MOS varactor
Abstract With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Dabas, Shweta [verfasserIn] Kumar, Manoj [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2019 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Analog integrated circuits and signal processing - Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991, 100(2019), 3 vom: 19. Juni, Seite 565-575 |
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| Übergeordnetes Werk: |
volume:100 ; year:2019 ; number:3 ; day:19 ; month:06 ; pages:565-575 |
| Links: |
|---|
| DOI / URN: |
10.1007/s10470-019-01476-0 |
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| Katalog-ID: |
SPR010330267 |
|---|
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| 245 | 1 | 2 | |a A CMOS based low power digitally controlled oscillator design with MOS varactor |
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| 520 | |a Abstract With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this paper, a new low power DCO structure is proposed with NMOS transistor as the switching network and utilizing the NMOS varactor as shunt-capacitive loads for the delay cells. The new DCO is capable of producing much higher output frequencies and comprises of components that are fully digital. The proposed DCO structure is designed for three, five and seven stages in CMOS 0.18 µm technology. Variable capacitance is achieved by the use of control word which is applied through NMOS switches conditionally selecting combinations of capacitance and hence determining the delay of the circuit. A 3-stages digitally controlled oscillator shows output frequency variation from 1.986 to 3.526 GHz with a power consumption of 1.484 mW. In the 5-stages DCO, the output frequency varies from 1.154 to 2.210 GHz with a power consumption of 2.762 mW. For 7-stages DCO, the output oscillation frequency is in the range from 0.835 to 1.658 GHz with a power consumption of 4.04 mW. A 3-stages DCO shows a phase noise of − 100.06 dBc/Hz with the offset of 1 MHz with the corresponding figure of merit (FoM) of 165.37 dBc/Hz. Five and seven-stages DCO show phase noise of − 102.08 dBc/Hz and − 105.52 dBc/Hz at 1 MHz respectively. The figure of merit (FoM) for 5 and 7-stages is 160.92 dBc/Hz and 159.07 dBc/Hz respectively. The digital tuning range for 3, 5, and 7-stages DCO is 55.96%, 62.78%, and 66.05% respectively. Further, the results show that the designed DCO has a maximum supply voltage tuning range of 101.45% with the variation of $ V_{DD} $ from 1 to 1.8 V. Comparison with earlier reported circuits has been made based on output frequency, power consumption, and phase noise. | ||
| 650 | 4 | |a ADPLL |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Delay cell |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Digitally controlled oscillators (DCO) |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a NMOS |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Power consumption |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Varactor |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Kumar, Manoj |e verfasserin |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t Analog integrated circuits and signal processing |d Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 |g 100(2019), 3 vom: 19. Juni, Seite 565-575 |w (DE-627)271348925 |w (DE-600)1479772-0 |x 1573-1979 |7 nnns |
| 773 | 1 | 8 | |g volume:100 |g year:2019 |g number:3 |g day:19 |g month:06 |g pages:565-575 |
| 856 | 4 | 0 | |u https://dx.doi.org/10.1007/s10470-019-01476-0 |z lizenzpflichtig |3 Volltext |
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| 912 | |a GBV_ILN_23 | ||
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| 912 | |a GBV_ILN_31 | ||
| 912 | |a GBV_ILN_32 | ||
| 912 | |a GBV_ILN_39 | ||
| 912 | |a GBV_ILN_40 | ||
| 912 | |a GBV_ILN_60 | ||
| 912 | |a GBV_ILN_62 | ||
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| 912 | |a GBV_ILN_69 | ||
| 912 | |a GBV_ILN_70 | ||
| 912 | |a GBV_ILN_73 | ||
| 912 | |a GBV_ILN_74 | ||
| 912 | |a GBV_ILN_90 | ||
| 912 | |a GBV_ILN_95 | ||
| 912 | |a GBV_ILN_100 | ||
| 912 | |a GBV_ILN_101 | ||
| 912 | |a GBV_ILN_105 | ||
| 912 | |a GBV_ILN_110 | ||
| 912 | |a GBV_ILN_120 | ||
| 912 | |a GBV_ILN_138 | ||
| 912 | |a GBV_ILN_150 | ||
| 912 | |a GBV_ILN_151 | ||
| 912 | |a GBV_ILN_152 | ||
| 912 | |a GBV_ILN_161 | ||
| 912 | |a GBV_ILN_170 | ||
| 912 | |a GBV_ILN_171 | ||
| 912 | |a GBV_ILN_187 | ||
| 912 | |a GBV_ILN_213 | ||
| 912 | |a GBV_ILN_224 | ||
| 912 | |a GBV_ILN_230 | ||
| 912 | |a GBV_ILN_250 | ||
| 912 | |a GBV_ILN_281 | ||
| 912 | |a GBV_ILN_285 | ||
| 912 | |a GBV_ILN_293 | ||
| 912 | |a GBV_ILN_370 | ||
| 912 | |a GBV_ILN_602 | ||
| 912 | |a GBV_ILN_636 | ||
| 912 | |a GBV_ILN_702 | ||
| 912 | |a GBV_ILN_2001 | ||
| 912 | |a GBV_ILN_2003 | ||
| 912 | |a GBV_ILN_2004 | ||
| 912 | |a GBV_ILN_2005 | ||
| 912 | |a GBV_ILN_2006 | ||
| 912 | |a GBV_ILN_2007 | ||
| 912 | |a GBV_ILN_2008 | ||
| 912 | |a GBV_ILN_2009 | ||
| 912 | |a GBV_ILN_2010 | ||
| 912 | |a GBV_ILN_2011 | ||
| 912 | |a GBV_ILN_2014 | ||
| 912 | |a GBV_ILN_2015 | ||
| 912 | |a GBV_ILN_2020 | ||
| 912 | |a GBV_ILN_2021 | ||
| 912 | |a GBV_ILN_2025 | ||
| 912 | |a GBV_ILN_2026 | ||
| 912 | |a GBV_ILN_2027 | ||
| 912 | |a GBV_ILN_2031 | ||
| 912 | |a GBV_ILN_2034 | ||
| 912 | |a GBV_ILN_2037 | ||
| 912 | |a GBV_ILN_2038 | ||
| 912 | |a GBV_ILN_2039 | ||
| 912 | |a GBV_ILN_2044 | ||
| 912 | |a GBV_ILN_2048 | ||
| 912 | |a GBV_ILN_2049 | ||
| 912 | |a GBV_ILN_2050 | ||
| 912 | |a GBV_ILN_2055 | ||
| 912 | |a GBV_ILN_2057 | ||
| 912 | |a GBV_ILN_2059 | ||
| 912 | |a GBV_ILN_2061 | ||
| 912 | |a GBV_ILN_2064 | ||
| 912 | |a GBV_ILN_2065 | ||
| 912 | |a GBV_ILN_2068 | ||
| 912 | |a GBV_ILN_2070 | ||
| 912 | |a GBV_ILN_2086 | ||
| 912 | |a GBV_ILN_2088 | ||
| 912 | |a GBV_ILN_2093 | ||
| 912 | |a GBV_ILN_2106 | ||
| 912 | |a GBV_ILN_2107 | ||
| 912 | |a GBV_ILN_2108 | ||
| 912 | |a GBV_ILN_2110 | ||
| 912 | |a GBV_ILN_2111 | ||
| 912 | |a GBV_ILN_2112 | ||
| 912 | |a GBV_ILN_2113 | ||
| 912 | |a GBV_ILN_2116 | ||
| 912 | |a GBV_ILN_2118 | ||
| 912 | |a GBV_ILN_2119 | ||
| 912 | |a GBV_ILN_2122 | ||
| 912 | |a GBV_ILN_2129 | ||
| 912 | |a GBV_ILN_2143 | ||
| 912 | |a GBV_ILN_2144 | ||
| 912 | |a GBV_ILN_2147 | ||
| 912 | |a GBV_ILN_2148 | ||
| 912 | |a GBV_ILN_2152 | ||
| 912 | |a GBV_ILN_2153 | ||
| 912 | |a GBV_ILN_2188 | ||
| 912 | |a GBV_ILN_2190 | ||
| 912 | |a GBV_ILN_2232 | ||
| 912 | |a GBV_ILN_2336 | ||
| 912 | |a GBV_ILN_2446 | ||
| 912 | |a GBV_ILN_2470 | ||
| 912 | |a GBV_ILN_2472 | ||
| 912 | |a GBV_ILN_2507 | ||
| 912 | |a GBV_ILN_2522 | ||
| 912 | |a GBV_ILN_2548 | ||
| 912 | |a GBV_ILN_4035 | ||
| 912 | |a GBV_ILN_4037 | ||
| 912 | |a GBV_ILN_4046 | ||
| 912 | |a GBV_ILN_4112 | ||
| 912 | |a GBV_ILN_4125 | ||
| 912 | |a GBV_ILN_4242 | ||
| 912 | |a GBV_ILN_4246 | ||
| 912 | |a GBV_ILN_4249 | ||
| 912 | |a GBV_ILN_4251 | ||
| 912 | |a GBV_ILN_4305 | ||
| 912 | |a GBV_ILN_4306 | ||
| 912 | |a GBV_ILN_4307 | ||
| 912 | |a GBV_ILN_4313 | ||
| 912 | |a GBV_ILN_4322 | ||
| 912 | |a GBV_ILN_4323 | ||
| 912 | |a GBV_ILN_4324 | ||
| 912 | |a GBV_ILN_4325 | ||
| 912 | |a GBV_ILN_4326 | ||
| 912 | |a GBV_ILN_4333 | ||
| 912 | |a GBV_ILN_4334 | ||
| 912 | |a GBV_ILN_4335 | ||
| 912 | |a GBV_ILN_4336 | ||
| 912 | |a GBV_ILN_4338 | ||
| 912 | |a GBV_ILN_4393 | ||
| 912 | |a GBV_ILN_4700 | ||
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| allfields |
10.1007/s10470-019-01476-0 doi (DE-627)SPR010330267 (SPR)s10470-019-01476-0-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Dabas, Shweta verfasserin aut A CMOS based low power digitally controlled oscillator design with MOS varactor 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this paper, a new low power DCO structure is proposed with NMOS transistor as the switching network and utilizing the NMOS varactor as shunt-capacitive loads for the delay cells. The new DCO is capable of producing much higher output frequencies and comprises of components that are fully digital. The proposed DCO structure is designed for three, five and seven stages in CMOS 0.18 µm technology. Variable capacitance is achieved by the use of control word which is applied through NMOS switches conditionally selecting combinations of capacitance and hence determining the delay of the circuit. A 3-stages digitally controlled oscillator shows output frequency variation from 1.986 to 3.526 GHz with a power consumption of 1.484 mW. In the 5-stages DCO, the output frequency varies from 1.154 to 2.210 GHz with a power consumption of 2.762 mW. For 7-stages DCO, the output oscillation frequency is in the range from 0.835 to 1.658 GHz with a power consumption of 4.04 mW. A 3-stages DCO shows a phase noise of − 100.06 dBc/Hz with the offset of 1 MHz with the corresponding figure of merit (FoM) of 165.37 dBc/Hz. Five and seven-stages DCO show phase noise of − 102.08 dBc/Hz and − 105.52 dBc/Hz at 1 MHz respectively. The figure of merit (FoM) for 5 and 7-stages is 160.92 dBc/Hz and 159.07 dBc/Hz respectively. The digital tuning range for 3, 5, and 7-stages DCO is 55.96%, 62.78%, and 66.05% respectively. Further, the results show that the designed DCO has a maximum supply voltage tuning range of 101.45% with the variation of $ V_{DD} $ from 1 to 1.8 V. Comparison with earlier reported circuits has been made based on output frequency, power consumption, and phase noise. ADPLL (dpeaa)DE-He213 Delay cell (dpeaa)DE-He213 Digitally controlled oscillators (DCO) (dpeaa)DE-He213 NMOS (dpeaa)DE-He213 Power consumption (dpeaa)DE-He213 Varactor (dpeaa)DE-He213 Kumar, Manoj verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 100(2019), 3 vom: 19. Juni, Seite 565-575 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:100 year:2019 number:3 day:19 month:06 pages:565-575 https://dx.doi.org/10.1007/s10470-019-01476-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 100 2019 3 19 06 565-575 |
| spelling |
10.1007/s10470-019-01476-0 doi (DE-627)SPR010330267 (SPR)s10470-019-01476-0-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Dabas, Shweta verfasserin aut A CMOS based low power digitally controlled oscillator design with MOS varactor 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this paper, a new low power DCO structure is proposed with NMOS transistor as the switching network and utilizing the NMOS varactor as shunt-capacitive loads for the delay cells. The new DCO is capable of producing much higher output frequencies and comprises of components that are fully digital. The proposed DCO structure is designed for three, five and seven stages in CMOS 0.18 µm technology. Variable capacitance is achieved by the use of control word which is applied through NMOS switches conditionally selecting combinations of capacitance and hence determining the delay of the circuit. A 3-stages digitally controlled oscillator shows output frequency variation from 1.986 to 3.526 GHz with a power consumption of 1.484 mW. In the 5-stages DCO, the output frequency varies from 1.154 to 2.210 GHz with a power consumption of 2.762 mW. For 7-stages DCO, the output oscillation frequency is in the range from 0.835 to 1.658 GHz with a power consumption of 4.04 mW. A 3-stages DCO shows a phase noise of − 100.06 dBc/Hz with the offset of 1 MHz with the corresponding figure of merit (FoM) of 165.37 dBc/Hz. Five and seven-stages DCO show phase noise of − 102.08 dBc/Hz and − 105.52 dBc/Hz at 1 MHz respectively. The figure of merit (FoM) for 5 and 7-stages is 160.92 dBc/Hz and 159.07 dBc/Hz respectively. The digital tuning range for 3, 5, and 7-stages DCO is 55.96%, 62.78%, and 66.05% respectively. Further, the results show that the designed DCO has a maximum supply voltage tuning range of 101.45% with the variation of $ V_{DD} $ from 1 to 1.8 V. Comparison with earlier reported circuits has been made based on output frequency, power consumption, and phase noise. ADPLL (dpeaa)DE-He213 Delay cell (dpeaa)DE-He213 Digitally controlled oscillators (DCO) (dpeaa)DE-He213 NMOS (dpeaa)DE-He213 Power consumption (dpeaa)DE-He213 Varactor (dpeaa)DE-He213 Kumar, Manoj verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 100(2019), 3 vom: 19. Juni, Seite 565-575 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:100 year:2019 number:3 day:19 month:06 pages:565-575 https://dx.doi.org/10.1007/s10470-019-01476-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 100 2019 3 19 06 565-575 |
| allfields_unstemmed |
10.1007/s10470-019-01476-0 doi (DE-627)SPR010330267 (SPR)s10470-019-01476-0-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Dabas, Shweta verfasserin aut A CMOS based low power digitally controlled oscillator design with MOS varactor 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this paper, a new low power DCO structure is proposed with NMOS transistor as the switching network and utilizing the NMOS varactor as shunt-capacitive loads for the delay cells. The new DCO is capable of producing much higher output frequencies and comprises of components that are fully digital. The proposed DCO structure is designed for three, five and seven stages in CMOS 0.18 µm technology. Variable capacitance is achieved by the use of control word which is applied through NMOS switches conditionally selecting combinations of capacitance and hence determining the delay of the circuit. A 3-stages digitally controlled oscillator shows output frequency variation from 1.986 to 3.526 GHz with a power consumption of 1.484 mW. In the 5-stages DCO, the output frequency varies from 1.154 to 2.210 GHz with a power consumption of 2.762 mW. For 7-stages DCO, the output oscillation frequency is in the range from 0.835 to 1.658 GHz with a power consumption of 4.04 mW. A 3-stages DCO shows a phase noise of − 100.06 dBc/Hz with the offset of 1 MHz with the corresponding figure of merit (FoM) of 165.37 dBc/Hz. Five and seven-stages DCO show phase noise of − 102.08 dBc/Hz and − 105.52 dBc/Hz at 1 MHz respectively. The figure of merit (FoM) for 5 and 7-stages is 160.92 dBc/Hz and 159.07 dBc/Hz respectively. The digital tuning range for 3, 5, and 7-stages DCO is 55.96%, 62.78%, and 66.05% respectively. Further, the results show that the designed DCO has a maximum supply voltage tuning range of 101.45% with the variation of $ V_{DD} $ from 1 to 1.8 V. Comparison with earlier reported circuits has been made based on output frequency, power consumption, and phase noise. ADPLL (dpeaa)DE-He213 Delay cell (dpeaa)DE-He213 Digitally controlled oscillators (DCO) (dpeaa)DE-He213 NMOS (dpeaa)DE-He213 Power consumption (dpeaa)DE-He213 Varactor (dpeaa)DE-He213 Kumar, Manoj verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 100(2019), 3 vom: 19. Juni, Seite 565-575 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:100 year:2019 number:3 day:19 month:06 pages:565-575 https://dx.doi.org/10.1007/s10470-019-01476-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 100 2019 3 19 06 565-575 |
| allfieldsGer |
10.1007/s10470-019-01476-0 doi (DE-627)SPR010330267 (SPR)s10470-019-01476-0-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Dabas, Shweta verfasserin aut A CMOS based low power digitally controlled oscillator design with MOS varactor 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this paper, a new low power DCO structure is proposed with NMOS transistor as the switching network and utilizing the NMOS varactor as shunt-capacitive loads for the delay cells. The new DCO is capable of producing much higher output frequencies and comprises of components that are fully digital. The proposed DCO structure is designed for three, five and seven stages in CMOS 0.18 µm technology. Variable capacitance is achieved by the use of control word which is applied through NMOS switches conditionally selecting combinations of capacitance and hence determining the delay of the circuit. A 3-stages digitally controlled oscillator shows output frequency variation from 1.986 to 3.526 GHz with a power consumption of 1.484 mW. In the 5-stages DCO, the output frequency varies from 1.154 to 2.210 GHz with a power consumption of 2.762 mW. For 7-stages DCO, the output oscillation frequency is in the range from 0.835 to 1.658 GHz with a power consumption of 4.04 mW. A 3-stages DCO shows a phase noise of − 100.06 dBc/Hz with the offset of 1 MHz with the corresponding figure of merit (FoM) of 165.37 dBc/Hz. Five and seven-stages DCO show phase noise of − 102.08 dBc/Hz and − 105.52 dBc/Hz at 1 MHz respectively. The figure of merit (FoM) for 5 and 7-stages is 160.92 dBc/Hz and 159.07 dBc/Hz respectively. The digital tuning range for 3, 5, and 7-stages DCO is 55.96%, 62.78%, and 66.05% respectively. Further, the results show that the designed DCO has a maximum supply voltage tuning range of 101.45% with the variation of $ V_{DD} $ from 1 to 1.8 V. Comparison with earlier reported circuits has been made based on output frequency, power consumption, and phase noise. ADPLL (dpeaa)DE-He213 Delay cell (dpeaa)DE-He213 Digitally controlled oscillators (DCO) (dpeaa)DE-He213 NMOS (dpeaa)DE-He213 Power consumption (dpeaa)DE-He213 Varactor (dpeaa)DE-He213 Kumar, Manoj verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 100(2019), 3 vom: 19. Juni, Seite 565-575 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:100 year:2019 number:3 day:19 month:06 pages:565-575 https://dx.doi.org/10.1007/s10470-019-01476-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 100 2019 3 19 06 565-575 |
| allfieldsSound |
10.1007/s10470-019-01476-0 doi (DE-627)SPR010330267 (SPR)s10470-019-01476-0-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Dabas, Shweta verfasserin aut A CMOS based low power digitally controlled oscillator design with MOS varactor 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this paper, a new low power DCO structure is proposed with NMOS transistor as the switching network and utilizing the NMOS varactor as shunt-capacitive loads for the delay cells. The new DCO is capable of producing much higher output frequencies and comprises of components that are fully digital. The proposed DCO structure is designed for three, five and seven stages in CMOS 0.18 µm technology. Variable capacitance is achieved by the use of control word which is applied through NMOS switches conditionally selecting combinations of capacitance and hence determining the delay of the circuit. A 3-stages digitally controlled oscillator shows output frequency variation from 1.986 to 3.526 GHz with a power consumption of 1.484 mW. In the 5-stages DCO, the output frequency varies from 1.154 to 2.210 GHz with a power consumption of 2.762 mW. For 7-stages DCO, the output oscillation frequency is in the range from 0.835 to 1.658 GHz with a power consumption of 4.04 mW. A 3-stages DCO shows a phase noise of − 100.06 dBc/Hz with the offset of 1 MHz with the corresponding figure of merit (FoM) of 165.37 dBc/Hz. Five and seven-stages DCO show phase noise of − 102.08 dBc/Hz and − 105.52 dBc/Hz at 1 MHz respectively. The figure of merit (FoM) for 5 and 7-stages is 160.92 dBc/Hz and 159.07 dBc/Hz respectively. The digital tuning range for 3, 5, and 7-stages DCO is 55.96%, 62.78%, and 66.05% respectively. Further, the results show that the designed DCO has a maximum supply voltage tuning range of 101.45% with the variation of $ V_{DD} $ from 1 to 1.8 V. Comparison with earlier reported circuits has been made based on output frequency, power consumption, and phase noise. ADPLL (dpeaa)DE-He213 Delay cell (dpeaa)DE-He213 Digitally controlled oscillators (DCO) (dpeaa)DE-He213 NMOS (dpeaa)DE-He213 Power consumption (dpeaa)DE-He213 Varactor (dpeaa)DE-He213 Kumar, Manoj verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 100(2019), 3 vom: 19. Juni, Seite 565-575 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:100 year:2019 number:3 day:19 month:06 pages:565-575 https://dx.doi.org/10.1007/s10470-019-01476-0 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 100 2019 3 19 06 565-575 |
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Enthalten in Analog integrated circuits and signal processing 100(2019), 3 vom: 19. Juni, Seite 565-575 volume:100 year:2019 number:3 day:19 month:06 pages:565-575 |
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Enthalten in Analog integrated circuits and signal processing 100(2019), 3 vom: 19. Juni, Seite 565-575 volume:100 year:2019 number:3 day:19 month:06 pages:565-575 |
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ADPLL Delay cell Digitally controlled oscillators (DCO) NMOS Power consumption Varactor |
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Analog integrated circuits and signal processing |
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Dabas, Shweta @@aut@@ Kumar, Manoj @@aut@@ |
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2019-06-19T00:00:00Z |
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Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this paper, a new low power DCO structure is proposed with NMOS transistor as the switching network and utilizing the NMOS varactor as shunt-capacitive loads for the delay cells. The new DCO is capable of producing much higher output frequencies and comprises of components that are fully digital. The proposed DCO structure is designed for three, five and seven stages in CMOS 0.18 µm technology. Variable capacitance is achieved by the use of control word which is applied through NMOS switches conditionally selecting combinations of capacitance and hence determining the delay of the circuit. A 3-stages digitally controlled oscillator shows output frequency variation from 1.986 to 3.526 GHz with a power consumption of 1.484 mW. In the 5-stages DCO, the output frequency varies from 1.154 to 2.210 GHz with a power consumption of 2.762 mW. For 7-stages DCO, the output oscillation frequency is in the range from 0.835 to 1.658 GHz with a power consumption of 4.04 mW. A 3-stages DCO shows a phase noise of − 100.06 dBc/Hz with the offset of 1 MHz with the corresponding figure of merit (FoM) of 165.37 dBc/Hz. Five and seven-stages DCO show phase noise of − 102.08 dBc/Hz and − 105.52 dBc/Hz at 1 MHz respectively. The figure of merit (FoM) for 5 and 7-stages is 160.92 dBc/Hz and 159.07 dBc/Hz respectively. The digital tuning range for 3, 5, and 7-stages DCO is 55.96%, 62.78%, and 66.05% respectively. Further, the results show that the designed DCO has a maximum supply voltage tuning range of 101.45% with the variation of $ V_{DD} $ from 1 to 1.8 V. Comparison with earlier reported circuits has been made based on output frequency, power consumption, and phase noise.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">ADPLL</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Delay cell</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Digitally controlled oscillators (DCO)</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">NMOS</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Power consumption</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Varactor</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kumar, Manoj</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Analog integrated circuits and signal processing</subfield><subfield code="d">Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991</subfield><subfield code="g">100(2019), 3 vom: 19. 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Dabas, Shweta |
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Dabas, Shweta ddc 004 bkl 53.55 bkl 53.73 misc ADPLL misc Delay cell misc Digitally controlled oscillators (DCO) misc NMOS misc Power consumption misc Varactor A CMOS based low power digitally controlled oscillator design with MOS varactor |
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004 ASE 53.55 bkl 53.73 bkl A CMOS based low power digitally controlled oscillator design with MOS varactor ADPLL (dpeaa)DE-He213 Delay cell (dpeaa)DE-He213 Digitally controlled oscillators (DCO) (dpeaa)DE-He213 NMOS (dpeaa)DE-He213 Power consumption (dpeaa)DE-He213 Varactor (dpeaa)DE-He213 |
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ddc 004 bkl 53.55 bkl 53.73 misc ADPLL misc Delay cell misc Digitally controlled oscillators (DCO) misc NMOS misc Power consumption misc Varactor |
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ddc 004 bkl 53.55 bkl 53.73 misc ADPLL misc Delay cell misc Digitally controlled oscillators (DCO) misc NMOS misc Power consumption misc Varactor |
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cmos based low power digitally controlled oscillator design with mos varactor |
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A CMOS based low power digitally controlled oscillator design with MOS varactor |
| abstract |
Abstract With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this paper, a new low power DCO structure is proposed with NMOS transistor as the switching network and utilizing the NMOS varactor as shunt-capacitive loads for the delay cells. The new DCO is capable of producing much higher output frequencies and comprises of components that are fully digital. The proposed DCO structure is designed for three, five and seven stages in CMOS 0.18 µm technology. Variable capacitance is achieved by the use of control word which is applied through NMOS switches conditionally selecting combinations of capacitance and hence determining the delay of the circuit. A 3-stages digitally controlled oscillator shows output frequency variation from 1.986 to 3.526 GHz with a power consumption of 1.484 mW. In the 5-stages DCO, the output frequency varies from 1.154 to 2.210 GHz with a power consumption of 2.762 mW. For 7-stages DCO, the output oscillation frequency is in the range from 0.835 to 1.658 GHz with a power consumption of 4.04 mW. A 3-stages DCO shows a phase noise of − 100.06 dBc/Hz with the offset of 1 MHz with the corresponding figure of merit (FoM) of 165.37 dBc/Hz. Five and seven-stages DCO show phase noise of − 102.08 dBc/Hz and − 105.52 dBc/Hz at 1 MHz respectively. The figure of merit (FoM) for 5 and 7-stages is 160.92 dBc/Hz and 159.07 dBc/Hz respectively. The digital tuning range for 3, 5, and 7-stages DCO is 55.96%, 62.78%, and 66.05% respectively. Further, the results show that the designed DCO has a maximum supply voltage tuning range of 101.45% with the variation of $ V_{DD} $ from 1 to 1.8 V. Comparison with earlier reported circuits has been made based on output frequency, power consumption, and phase noise. |
| abstractGer |
Abstract With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this paper, a new low power DCO structure is proposed with NMOS transistor as the switching network and utilizing the NMOS varactor as shunt-capacitive loads for the delay cells. The new DCO is capable of producing much higher output frequencies and comprises of components that are fully digital. The proposed DCO structure is designed for three, five and seven stages in CMOS 0.18 µm technology. Variable capacitance is achieved by the use of control word which is applied through NMOS switches conditionally selecting combinations of capacitance and hence determining the delay of the circuit. A 3-stages digitally controlled oscillator shows output frequency variation from 1.986 to 3.526 GHz with a power consumption of 1.484 mW. In the 5-stages DCO, the output frequency varies from 1.154 to 2.210 GHz with a power consumption of 2.762 mW. For 7-stages DCO, the output oscillation frequency is in the range from 0.835 to 1.658 GHz with a power consumption of 4.04 mW. A 3-stages DCO shows a phase noise of − 100.06 dBc/Hz with the offset of 1 MHz with the corresponding figure of merit (FoM) of 165.37 dBc/Hz. Five and seven-stages DCO show phase noise of − 102.08 dBc/Hz and − 105.52 dBc/Hz at 1 MHz respectively. The figure of merit (FoM) for 5 and 7-stages is 160.92 dBc/Hz and 159.07 dBc/Hz respectively. The digital tuning range for 3, 5, and 7-stages DCO is 55.96%, 62.78%, and 66.05% respectively. Further, the results show that the designed DCO has a maximum supply voltage tuning range of 101.45% with the variation of $ V_{DD} $ from 1 to 1.8 V. Comparison with earlier reported circuits has been made based on output frequency, power consumption, and phase noise. |
| abstract_unstemmed |
Abstract With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this paper, a new low power DCO structure is proposed with NMOS transistor as the switching network and utilizing the NMOS varactor as shunt-capacitive loads for the delay cells. The new DCO is capable of producing much higher output frequencies and comprises of components that are fully digital. The proposed DCO structure is designed for three, five and seven stages in CMOS 0.18 µm technology. Variable capacitance is achieved by the use of control word which is applied through NMOS switches conditionally selecting combinations of capacitance and hence determining the delay of the circuit. A 3-stages digitally controlled oscillator shows output frequency variation from 1.986 to 3.526 GHz with a power consumption of 1.484 mW. In the 5-stages DCO, the output frequency varies from 1.154 to 2.210 GHz with a power consumption of 2.762 mW. For 7-stages DCO, the output oscillation frequency is in the range from 0.835 to 1.658 GHz with a power consumption of 4.04 mW. A 3-stages DCO shows a phase noise of − 100.06 dBc/Hz with the offset of 1 MHz with the corresponding figure of merit (FoM) of 165.37 dBc/Hz. Five and seven-stages DCO show phase noise of − 102.08 dBc/Hz and − 105.52 dBc/Hz at 1 MHz respectively. The figure of merit (FoM) for 5 and 7-stages is 160.92 dBc/Hz and 159.07 dBc/Hz respectively. The digital tuning range for 3, 5, and 7-stages DCO is 55.96%, 62.78%, and 66.05% respectively. Further, the results show that the designed DCO has a maximum supply voltage tuning range of 101.45% with the variation of $ V_{DD} $ from 1 to 1.8 V. Comparison with earlier reported circuits has been made based on output frequency, power consumption, and phase noise. |
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| container_issue |
3 |
| title_short |
A CMOS based low power digitally controlled oscillator design with MOS varactor |
| url |
https://dx.doi.org/10.1007/s10470-019-01476-0 |
| remote_bool |
true |
| author2 |
Kumar, Manoj |
| author2Str |
Kumar, Manoj |
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c |
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false |
| hochschulschrift_bool |
false |
| doi_str |
10.1007/s10470-019-01476-0 |
| up_date |
2024-07-03T15:25:22.912Z |
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| score |
7.402936 |