Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning

Abstract This paper presents a three-bit digital controlled oscillator (DCO) with three-stage ring topology. The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally co...
Ausführliche Beschreibung

Gespeichert in:

Autor*in:	Dwivedi, Dileep [verfasserIn] Kumar, Manoj [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2019

Schlagwörter:	Delay cell Digital controlled oscillator (DCO) IMOS varactor NAND gate Phase noise

Übergeordnetes Werk:	Enthalten in: Analog integrated circuits and signal processing - Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991, 100(2019), 3 vom: 19. Juli, Seite 613-620
Übergeordnetes Werk:	volume:100 ; year:2019 ; number:3 ; day:19 ; month:07 ; pages:613-620

Links:	Volltext

DOI / URN:	10.1007/s10470-019-01506-x

Katalog-ID:	SPR010330356

Internformat


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520			\|a Abstract This paper presents a three-bit digital controlled oscillator (DCO) with three-stage ring topology. The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally controlled load element is added at the output node of inverter to control the tuning range of proposed DCO circuit. Load element of DCO circuit has been implemented using three IMOS varactors to provide a better frequency tuning capability at low supply voltage ($ V_{dd} $). The digital control bit varies the driving current across the load element that causes to change the oscillation frequency of proposed DCO. A tunable range of frequency from 0.818 to 0.872 GHz has been obtained with different combination of digital control bit with $ V_{dd} $ of 1.8 V. Effect of $ V_{dd} $ variations has also been observed. For control bits CBA = ‘000’ the proposed DCO operates from 0.711 to 1.278 GHz with $ V_{dd} $ variations from 1.6 to 3 V. Further, at control bits CBA = ‘111’, DCO oscillates form 0.755 to 1.296 GHz with $ V_{dd} $ variation. The proposed DCO shows a phase noise of − 101.24 dBc/Hz at an offset of 1 MHz from carrier frequency with 0.248 mW power consumption at 0.872 GHz operating frequency. Figure of merit for the proposed DCO circuit is 166.10 dBc/Hz.
650		4	\|a Delay cell \|7 (dpeaa)DE-He213
650		4	\|a Digital controlled oscillator (DCO) \|7 (dpeaa)DE-He213
650		4	\|a IMOS varactor \|7 (dpeaa)DE-He213
650		4	\|a NAND gate \|7 (dpeaa)DE-He213
650		4	\|a Phase noise \|7 (dpeaa)DE-He213
700	1		\|a Kumar, Manoj \|e verfasserin \|4 aut
773	0	8	\|i Enthalten in \|t Analog integrated circuits and signal processing \|d Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 \|g 100(2019), 3 vom: 19. Juli, Seite 613-620 \|w (DE-627)271348925 \|w (DE-600)1479772-0 \|x 1573-1979 \|7 nnns
773	1	8	\|g volume:100 \|g year:2019 \|g number:3 \|g day:19 \|g month:07 \|g pages:613-620
856	4	0	\|u https://dx.doi.org/10.1007/s10470-019-01506-x \|z lizenzpflichtig \|3 Volltext
912			\|a GBV_USEFLAG_A
912			\|a SYSFLAG_A
912			\|a GBV_SPRINGER
912			\|a GBV_ILN_11
912			\|a GBV_ILN_20
912			\|a GBV_ILN_22
912			\|a GBV_ILN_23
912			\|a GBV_ILN_24
912			\|a GBV_ILN_31
912			\|a GBV_ILN_32
912			\|a GBV_ILN_39
912			\|a GBV_ILN_40
912			\|a GBV_ILN_60
912			\|a GBV_ILN_62
912			\|a GBV_ILN_63
912			\|a GBV_ILN_69
912			\|a GBV_ILN_70
912			\|a GBV_ILN_73
912			\|a GBV_ILN_74
912			\|a GBV_ILN_90
912			\|a GBV_ILN_95
912			\|a GBV_ILN_100
912			\|a GBV_ILN_101
912			\|a GBV_ILN_105
912			\|a GBV_ILN_110
912			\|a GBV_ILN_120
912			\|a GBV_ILN_138
912			\|a GBV_ILN_150
912			\|a GBV_ILN_151
912			\|a GBV_ILN_152
912			\|a GBV_ILN_161
912			\|a GBV_ILN_170
912			\|a GBV_ILN_171
912			\|a GBV_ILN_187
912			\|a GBV_ILN_213
912			\|a GBV_ILN_224
912			\|a GBV_ILN_230
912			\|a GBV_ILN_250
912			\|a GBV_ILN_281
912			\|a GBV_ILN_285
912			\|a GBV_ILN_293
912			\|a GBV_ILN_370
912			\|a GBV_ILN_602
912			\|a GBV_ILN_636
912			\|a GBV_ILN_702
912			\|a GBV_ILN_2001
912			\|a GBV_ILN_2003
912			\|a GBV_ILN_2004
912			\|a GBV_ILN_2005
912			\|a GBV_ILN_2006
912			\|a GBV_ILN_2007
912			\|a GBV_ILN_2008
912			\|a GBV_ILN_2009
912			\|a GBV_ILN_2010
912			\|a GBV_ILN_2011
912			\|a GBV_ILN_2014
912			\|a GBV_ILN_2015
912			\|a GBV_ILN_2020
912			\|a GBV_ILN_2021
912			\|a GBV_ILN_2025
912			\|a GBV_ILN_2026
912			\|a GBV_ILN_2027
912			\|a GBV_ILN_2031
912			\|a GBV_ILN_2034
912			\|a GBV_ILN_2037
912			\|a GBV_ILN_2038
912			\|a GBV_ILN_2039
912			\|a GBV_ILN_2044
912			\|a GBV_ILN_2048
912			\|a GBV_ILN_2049
912			\|a GBV_ILN_2050
912			\|a GBV_ILN_2055
912			\|a GBV_ILN_2057
912			\|a GBV_ILN_2059
912			\|a GBV_ILN_2061
912			\|a GBV_ILN_2064
912			\|a GBV_ILN_2065
912			\|a GBV_ILN_2068
912			\|a GBV_ILN_2070
912			\|a GBV_ILN_2086
912			\|a GBV_ILN_2088
912			\|a GBV_ILN_2093
912			\|a GBV_ILN_2106
912			\|a GBV_ILN_2107
912			\|a GBV_ILN_2108
912			\|a GBV_ILN_2110
912			\|a GBV_ILN_2111
912			\|a GBV_ILN_2112
912			\|a GBV_ILN_2113
912			\|a GBV_ILN_2116
912			\|a GBV_ILN_2118
912			\|a GBV_ILN_2119
912			\|a GBV_ILN_2122
912			\|a GBV_ILN_2129
912			\|a GBV_ILN_2143
912			\|a GBV_ILN_2144
912			\|a GBV_ILN_2147
912			\|a GBV_ILN_2148
912			\|a GBV_ILN_2152
912			\|a GBV_ILN_2153
912			\|a GBV_ILN_2188
912			\|a GBV_ILN_2190
912			\|a GBV_ILN_2232
912			\|a GBV_ILN_2336
912			\|a GBV_ILN_2446
912			\|a GBV_ILN_2470
912			\|a GBV_ILN_2472
912			\|a GBV_ILN_2507
912			\|a GBV_ILN_2522
912			\|a GBV_ILN_2548
912			\|a GBV_ILN_4035
912			\|a GBV_ILN_4037
912			\|a GBV_ILN_4046
912			\|a GBV_ILN_4112
912			\|a GBV_ILN_4125
912			\|a GBV_ILN_4242
912			\|a GBV_ILN_4246
912			\|a GBV_ILN_4249
912			\|a GBV_ILN_4251
912			\|a GBV_ILN_4305
912			\|a GBV_ILN_4306
912			\|a GBV_ILN_4307
912			\|a GBV_ILN_4313
912			\|a GBV_ILN_4322
912			\|a GBV_ILN_4323
912			\|a GBV_ILN_4324
912			\|a GBV_ILN_4325
912			\|a GBV_ILN_4326
912			\|a GBV_ILN_4333
912			\|a GBV_ILN_4334
912			\|a GBV_ILN_4335
912			\|a GBV_ILN_4336
912			\|a GBV_ILN_4338
912			\|a GBV_ILN_4393
912			\|a GBV_ILN_4700
936	b	k	\|a 53.55 \|q ASE
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952			\|d 100 \|j 2019 \|e 3 \|b 19 \|c 07 \|h 613-620

Indexfelder

author_variant	d d dd m k mk
matchkey_str	article:15731979:2019----::einf3idgtlotooclaodosn
hierarchy_sort_str	2019
bklnumber	53.55 53.73
publishDate	2019
allfields	10.1007/s10470-019-01506-x doi (DE-627)SPR010330356 (SPR)s10470-019-01506-x-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Dwivedi, Dileep verfasserin aut Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents a three-bit digital controlled oscillator (DCO) with three-stage ring topology. The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally controlled load element is added at the output node of inverter to control the tuning range of proposed DCO circuit. Load element of DCO circuit has been implemented using three IMOS varactors to provide a better frequency tuning capability at low supply voltage ($ V_{dd} $). The digital control bit varies the driving current across the load element that causes to change the oscillation frequency of proposed DCO. A tunable range of frequency from 0.818 to 0.872 GHz has been obtained with different combination of digital control bit with $ V_{dd} $ of 1.8 V. Effect of $ V_{dd} $ variations has also been observed. For control bits CBA = ‘000’ the proposed DCO operates from 0.711 to 1.278 GHz with $ V_{dd} $ variations from 1.6 to 3 V. Further, at control bits CBA = ‘111’, DCO oscillates form 0.755 to 1.296 GHz with $ V_{dd} $ variation. The proposed DCO shows a phase noise of − 101.24 dBc/Hz at an offset of 1 MHz from carrier frequency with 0.248 mW power consumption at 0.872 GHz operating frequency. Figure of merit for the proposed DCO circuit is 166.10 dBc/Hz. Delay cell (dpeaa)DE-He213 Digital controlled oscillator (DCO) (dpeaa)DE-He213 IMOS varactor (dpeaa)DE-He213 NAND gate (dpeaa)DE-He213 Phase noise (dpeaa)DE-He213 Kumar, Manoj verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 100(2019), 3 vom: 19. Juli, Seite 613-620 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:100 year:2019 number:3 day:19 month:07 pages:613-620 https://dx.doi.org/10.1007/s10470-019-01506-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 100 2019 3 19 07 613-620
spelling	10.1007/s10470-019-01506-x doi (DE-627)SPR010330356 (SPR)s10470-019-01506-x-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Dwivedi, Dileep verfasserin aut Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents a three-bit digital controlled oscillator (DCO) with three-stage ring topology. The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally controlled load element is added at the output node of inverter to control the tuning range of proposed DCO circuit. Load element of DCO circuit has been implemented using three IMOS varactors to provide a better frequency tuning capability at low supply voltage ($ V_{dd} $). The digital control bit varies the driving current across the load element that causes to change the oscillation frequency of proposed DCO. A tunable range of frequency from 0.818 to 0.872 GHz has been obtained with different combination of digital control bit with $ V_{dd} $ of 1.8 V. Effect of $ V_{dd} $ variations has also been observed. For control bits CBA = ‘000’ the proposed DCO operates from 0.711 to 1.278 GHz with $ V_{dd} $ variations from 1.6 to 3 V. Further, at control bits CBA = ‘111’, DCO oscillates form 0.755 to 1.296 GHz with $ V_{dd} $ variation. The proposed DCO shows a phase noise of − 101.24 dBc/Hz at an offset of 1 MHz from carrier frequency with 0.248 mW power consumption at 0.872 GHz operating frequency. Figure of merit for the proposed DCO circuit is 166.10 dBc/Hz. Delay cell (dpeaa)DE-He213 Digital controlled oscillator (DCO) (dpeaa)DE-He213 IMOS varactor (dpeaa)DE-He213 NAND gate (dpeaa)DE-He213 Phase noise (dpeaa)DE-He213 Kumar, Manoj verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 100(2019), 3 vom: 19. Juli, Seite 613-620 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:100 year:2019 number:3 day:19 month:07 pages:613-620 https://dx.doi.org/10.1007/s10470-019-01506-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 100 2019 3 19 07 613-620
allfields_unstemmed	10.1007/s10470-019-01506-x doi (DE-627)SPR010330356 (SPR)s10470-019-01506-x-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Dwivedi, Dileep verfasserin aut Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents a three-bit digital controlled oscillator (DCO) with three-stage ring topology. The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally controlled load element is added at the output node of inverter to control the tuning range of proposed DCO circuit. Load element of DCO circuit has been implemented using three IMOS varactors to provide a better frequency tuning capability at low supply voltage ($ V_{dd} $). The digital control bit varies the driving current across the load element that causes to change the oscillation frequency of proposed DCO. A tunable range of frequency from 0.818 to 0.872 GHz has been obtained with different combination of digital control bit with $ V_{dd} $ of 1.8 V. Effect of $ V_{dd} $ variations has also been observed. For control bits CBA = ‘000’ the proposed DCO operates from 0.711 to 1.278 GHz with $ V_{dd} $ variations from 1.6 to 3 V. Further, at control bits CBA = ‘111’, DCO oscillates form 0.755 to 1.296 GHz with $ V_{dd} $ variation. The proposed DCO shows a phase noise of − 101.24 dBc/Hz at an offset of 1 MHz from carrier frequency with 0.248 mW power consumption at 0.872 GHz operating frequency. Figure of merit for the proposed DCO circuit is 166.10 dBc/Hz. Delay cell (dpeaa)DE-He213 Digital controlled oscillator (DCO) (dpeaa)DE-He213 IMOS varactor (dpeaa)DE-He213 NAND gate (dpeaa)DE-He213 Phase noise (dpeaa)DE-He213 Kumar, Manoj verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 100(2019), 3 vom: 19. Juli, Seite 613-620 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:100 year:2019 number:3 day:19 month:07 pages:613-620 https://dx.doi.org/10.1007/s10470-019-01506-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 100 2019 3 19 07 613-620
allfieldsGer	10.1007/s10470-019-01506-x doi (DE-627)SPR010330356 (SPR)s10470-019-01506-x-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Dwivedi, Dileep verfasserin aut Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents a three-bit digital controlled oscillator (DCO) with three-stage ring topology. The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally controlled load element is added at the output node of inverter to control the tuning range of proposed DCO circuit. Load element of DCO circuit has been implemented using three IMOS varactors to provide a better frequency tuning capability at low supply voltage ($ V_{dd} $). The digital control bit varies the driving current across the load element that causes to change the oscillation frequency of proposed DCO. A tunable range of frequency from 0.818 to 0.872 GHz has been obtained with different combination of digital control bit with $ V_{dd} $ of 1.8 V. Effect of $ V_{dd} $ variations has also been observed. For control bits CBA = ‘000’ the proposed DCO operates from 0.711 to 1.278 GHz with $ V_{dd} $ variations from 1.6 to 3 V. Further, at control bits CBA = ‘111’, DCO oscillates form 0.755 to 1.296 GHz with $ V_{dd} $ variation. The proposed DCO shows a phase noise of − 101.24 dBc/Hz at an offset of 1 MHz from carrier frequency with 0.248 mW power consumption at 0.872 GHz operating frequency. Figure of merit for the proposed DCO circuit is 166.10 dBc/Hz. Delay cell (dpeaa)DE-He213 Digital controlled oscillator (DCO) (dpeaa)DE-He213 IMOS varactor (dpeaa)DE-He213 NAND gate (dpeaa)DE-He213 Phase noise (dpeaa)DE-He213 Kumar, Manoj verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 100(2019), 3 vom: 19. Juli, Seite 613-620 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:100 year:2019 number:3 day:19 month:07 pages:613-620 https://dx.doi.org/10.1007/s10470-019-01506-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 100 2019 3 19 07 613-620
allfieldsSound	10.1007/s10470-019-01506-x doi (DE-627)SPR010330356 (SPR)s10470-019-01506-x-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Dwivedi, Dileep verfasserin aut Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning 2019 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents a three-bit digital controlled oscillator (DCO) with three-stage ring topology. The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally controlled load element is added at the output node of inverter to control the tuning range of proposed DCO circuit. Load element of DCO circuit has been implemented using three IMOS varactors to provide a better frequency tuning capability at low supply voltage ($ V_{dd} $). The digital control bit varies the driving current across the load element that causes to change the oscillation frequency of proposed DCO. A tunable range of frequency from 0.818 to 0.872 GHz has been obtained with different combination of digital control bit with $ V_{dd} $ of 1.8 V. Effect of $ V_{dd} $ variations has also been observed. For control bits CBA = ‘000’ the proposed DCO operates from 0.711 to 1.278 GHz with $ V_{dd} $ variations from 1.6 to 3 V. Further, at control bits CBA = ‘111’, DCO oscillates form 0.755 to 1.296 GHz with $ V_{dd} $ variation. The proposed DCO shows a phase noise of − 101.24 dBc/Hz at an offset of 1 MHz from carrier frequency with 0.248 mW power consumption at 0.872 GHz operating frequency. Figure of merit for the proposed DCO circuit is 166.10 dBc/Hz. Delay cell (dpeaa)DE-He213 Digital controlled oscillator (DCO) (dpeaa)DE-He213 IMOS varactor (dpeaa)DE-He213 NAND gate (dpeaa)DE-He213 Phase noise (dpeaa)DE-He213 Kumar, Manoj verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 100(2019), 3 vom: 19. Juli, Seite 613-620 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:100 year:2019 number:3 day:19 month:07 pages:613-620 https://dx.doi.org/10.1007/s10470-019-01506-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 100 2019 3 19 07 613-620
language	English
source	Enthalten in Analog integrated circuits and signal processing 100(2019), 3 vom: 19. Juli, Seite 613-620 volume:100 year:2019 number:3 day:19 month:07 pages:613-620
sourceStr	Enthalten in Analog integrated circuits and signal processing 100(2019), 3 vom: 19. Juli, Seite 613-620 volume:100 year:2019 number:3 day:19 month:07 pages:613-620
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	Delay cell Digital controlled oscillator (DCO) IMOS varactor NAND gate Phase noise
dewey-raw	004
isfreeaccess_bool	false
container_title	Analog integrated circuits and signal processing
authorswithroles_txt_mv	Dwivedi, Dileep @@aut@@ Kumar, Manoj @@aut@@
publishDateDaySort_date	2019-07-19T00:00:00Z
hierarchy_top_id	271348925
dewey-sort	14
id	SPR010330356
language_de	englisch
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The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally controlled load element is added at the output node of inverter to control the tuning range of proposed DCO circuit. Load element of DCO circuit has been implemented using three IMOS varactors to provide a better frequency tuning capability at low supply voltage ($ V_{dd} $). The digital control bit varies the driving current across the load element that causes to change the oscillation frequency of proposed DCO. A tunable range of frequency from 0.818 to 0.872 GHz has been obtained with different combination of digital control bit with $ V_{dd} $ of 1.8 V. Effect of $ V_{dd} $ variations has also been observed. For control bits CBA = ‘000’ the proposed DCO operates from 0.711 to 1.278 GHz with $ V_{dd} $ variations from 1.6 to 3 V. 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author	Dwivedi, Dileep
spellingShingle	Dwivedi, Dileep ddc 004 bkl 53.55 bkl 53.73 misc Delay cell misc Digital controlled oscillator (DCO) misc IMOS varactor misc NAND gate misc Phase noise Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning
authorStr	Dwivedi, Dileep
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topic_title	004 ASE 53.55 bkl 53.73 bkl Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning Delay cell (dpeaa)DE-He213 Digital controlled oscillator (DCO) (dpeaa)DE-He213 IMOS varactor (dpeaa)DE-He213 NAND gate (dpeaa)DE-He213 Phase noise (dpeaa)DE-He213
topic	ddc 004 bkl 53.55 bkl 53.73 misc Delay cell misc Digital controlled oscillator (DCO) misc IMOS varactor misc NAND gate misc Phase noise
topic_unstemmed	ddc 004 bkl 53.55 bkl 53.73 misc Delay cell misc Digital controlled oscillator (DCO) misc IMOS varactor misc NAND gate misc Phase noise
topic_browse	ddc 004 bkl 53.55 bkl 53.73 misc Delay cell misc Digital controlled oscillator (DCO) misc IMOS varactor misc NAND gate misc Phase noise
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title	Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning
ctrlnum	(DE-627)SPR010330356 (SPR)s10470-019-01506-x-e
title_full	Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning
author_sort	Dwivedi, Dileep
journal	Analog integrated circuits and signal processing
journalStr	Analog integrated circuits and signal processing
lang_code	eng
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author_browse	Dwivedi, Dileep Kumar, Manoj
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class	004 ASE 53.55 bkl 53.73 bkl
format_se	Elektronische Aufsätze
author-letter	Dwivedi, Dileep
doi_str_mv	10.1007/s10470-019-01506-x
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title_sort	design of a 3-bit digital control oscillator (dco) using imos varactor tuning
title_auth	Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning
abstract	Abstract This paper presents a three-bit digital controlled oscillator (DCO) with three-stage ring topology. The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally controlled load element is added at the output node of inverter to control the tuning range of proposed DCO circuit. Load element of DCO circuit has been implemented using three IMOS varactors to provide a better frequency tuning capability at low supply voltage ($ V_{dd} $). The digital control bit varies the driving current across the load element that causes to change the oscillation frequency of proposed DCO. A tunable range of frequency from 0.818 to 0.872 GHz has been obtained with different combination of digital control bit with $ V_{dd} $ of 1.8 V. Effect of $ V_{dd} $ variations has also been observed. For control bits CBA = ‘000’ the proposed DCO operates from 0.711 to 1.278 GHz with $ V_{dd} $ variations from 1.6 to 3 V. Further, at control bits CBA = ‘111’, DCO oscillates form 0.755 to 1.296 GHz with $ V_{dd} $ variation. The proposed DCO shows a phase noise of − 101.24 dBc/Hz at an offset of 1 MHz from carrier frequency with 0.248 mW power consumption at 0.872 GHz operating frequency. Figure of merit for the proposed DCO circuit is 166.10 dBc/Hz.
abstractGer	Abstract This paper presents a three-bit digital controlled oscillator (DCO) with three-stage ring topology. The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally controlled load element is added at the output node of inverter to control the tuning range of proposed DCO circuit. Load element of DCO circuit has been implemented using three IMOS varactors to provide a better frequency tuning capability at low supply voltage ($ V_{dd} $). The digital control bit varies the driving current across the load element that causes to change the oscillation frequency of proposed DCO. A tunable range of frequency from 0.818 to 0.872 GHz has been obtained with different combination of digital control bit with $ V_{dd} $ of 1.8 V. Effect of $ V_{dd} $ variations has also been observed. For control bits CBA = ‘000’ the proposed DCO operates from 0.711 to 1.278 GHz with $ V_{dd} $ variations from 1.6 to 3 V. Further, at control bits CBA = ‘111’, DCO oscillates form 0.755 to 1.296 GHz with $ V_{dd} $ variation. The proposed DCO shows a phase noise of − 101.24 dBc/Hz at an offset of 1 MHz from carrier frequency with 0.248 mW power consumption at 0.872 GHz operating frequency. Figure of merit for the proposed DCO circuit is 166.10 dBc/Hz.
abstract_unstemmed	Abstract This paper presents a three-bit digital controlled oscillator (DCO) with three-stage ring topology. The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally controlled load element is added at the output node of inverter to control the tuning range of proposed DCO circuit. Load element of DCO circuit has been implemented using three IMOS varactors to provide a better frequency tuning capability at low supply voltage ($ V_{dd} $). The digital control bit varies the driving current across the load element that causes to change the oscillation frequency of proposed DCO. A tunable range of frequency from 0.818 to 0.872 GHz has been obtained with different combination of digital control bit with $ V_{dd} $ of 1.8 V. Effect of $ V_{dd} $ variations has also been observed. For control bits CBA = ‘000’ the proposed DCO operates from 0.711 to 1.278 GHz with $ V_{dd} $ variations from 1.6 to 3 V. Further, at control bits CBA = ‘111’, DCO oscillates form 0.755 to 1.296 GHz with $ V_{dd} $ variation. The proposed DCO shows a phase noise of − 101.24 dBc/Hz at an offset of 1 MHz from carrier frequency with 0.248 mW power consumption at 0.872 GHz operating frequency. Figure of merit for the proposed DCO circuit is 166.10 dBc/Hz.
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title_short	Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning
url	https://dx.doi.org/10.1007/s10470-019-01506-x
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doi_str	10.1007/s10470-019-01506-x
up_date	2024-07-03T15:25:24.910Z
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fullrecord_marcxml	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR010330356</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20220110220052.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201005s2019 xx \|\|\|\|\|o 00\| \|\|eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s10470-019-01506-x</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR010330356</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s10470-019-01506-x-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">004</subfield><subfield code="q">ASE</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.55</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">53.73</subfield><subfield code="2">bkl</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Dwivedi, Dileep</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2019</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This paper presents a three-bit digital controlled oscillator (DCO) with three-stage ring topology. The proposed DCO circuit has been realized in TSMC 0.18-μm CMOS technology. DCO circuit has been designed with NAND gate based inverter delay cell for low power consumption and a digitally controlled load element is added at the output node of inverter to control the tuning range of proposed DCO circuit. Load element of DCO circuit has been implemented using three IMOS varactors to provide a better frequency tuning capability at low supply voltage ($ V_{dd} $). The digital control bit varies the driving current across the load element that causes to change the oscillation frequency of proposed DCO. A tunable range of frequency from 0.818 to 0.872 GHz has been obtained with different combination of digital control bit with $ V_{dd} $ of 1.8 V. Effect of $ V_{dd} $ variations has also been observed. For control bits CBA = ‘000’ the proposed DCO operates from 0.711 to 1.278 GHz with $ V_{dd} $ variations from 1.6 to 3 V. Further, at control bits CBA = ‘111’, DCO oscillates form 0.755 to 1.296 GHz with $ V_{dd} $ variation. The proposed DCO shows a phase noise of − 101.24 dBc/Hz at an offset of 1 MHz from carrier frequency with 0.248 mW power consumption at 0.872 GHz operating frequency. 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Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning

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